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JFFS for WNR3500Lv2
[tomato.git] / release / src-rt / linux / linux-2.6 / drivers / mtd / 47xxnand / brcmnand_47xx.c
blob04ef70562fd2745416ec77eca31afacb2d2ec70f
1 /*
2 * Broadcom NAND flash controller interface
3 *
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id $
19 */
20
21 #include <linux/config.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/ioport.h>
25 #include <linux/mtd/compatmac.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/errno.h>
30 #include <linux/pci.h>
31 #include <linux/delay.h>
32 #include <asm/io.h>
33
34 #include <typedefs.h>
35 #include <osl.h>
36 #include <bcmutils.h>
37 #include <bcmdevs.h>
38 #include <bcmnvram.h>
39 #include <siutils.h>
40 #include <hndpci.h>
41 #include <pcicfg.h>
42 #include <hndsoc.h>
43 #include <sbchipc.h>
44 #include <nflash.h>
45
46 #include "brcmnand_priv.h"
47
48 struct mutex *partitions_mutex_init(void);
49 #ifdef CONFIG_MTD_PARTITIONS
50 #include <linux/mtd/partitions.h>
51
52 extern struct mtd_partition * init_brcmnand_mtd_partitions(struct mtd_info *mtd, size_t size);
53 #endif
54
55 static int nflash_lock = 0;
56
57 #define PLATFORM_IOFLUSH_WAR() __sync()
58
59 #define BRCMNAND_POLL_TIMEOUT 3000
60
61 #define BRCMNAND_CORRECTABLE_ECC_ERROR (1)
62 #define BRCMNAND_SUCCESS (0)
63 #define BRCMNAND_UNCORRECTABLE_ECC_ERROR (-1)
64 #define BRCMNAND_FLASH_STATUS_ERROR (-2)
65 #define BRCMNAND_TIMED_OUT (-3)
66
67 #define BRCMNAND_OOBBUF(pbuf) (&((pbuf)->databuf[NAND_MAX_PAGESIZE]))
68
69 /*
70 * Number of required ECC bytes per 512B slice
71 */
72 static const unsigned int brcmnand_eccbytes[16] = {
73 [BRCMNAND_ECC_DISABLE] = 0,
74 [BRCMNAND_ECC_BCH_1] = 2,
75 [BRCMNAND_ECC_BCH_2] = 4,
76 [BRCMNAND_ECC_BCH_3] = 5,
77 [BRCMNAND_ECC_BCH_4] = 7,
78 [BRCMNAND_ECC_BCH_5] = 9,
79 [BRCMNAND_ECC_BCH_6] = 10,
80 [BRCMNAND_ECC_BCH_7] = 12,
81 [BRCMNAND_ECC_BCH_8] = 13,
82 [BRCMNAND_ECC_BCH_9] = 15,
83 [BRCMNAND_ECC_BCH_10] = 17,
84 [BRCMNAND_ECC_BCH_11] = 18,
85 [BRCMNAND_ECC_BCH_12] = 20,
86 [BRCMNAND_ECC_RESVD_1] = 0,
87 [BRCMNAND_ECC_RESVD_2] = 0,
88 [BRCMNAND_ECC_HAMMING] = 3,
89 };
90
91 static const unsigned char ffchars[] = {
92 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
93 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
94 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
95 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
96 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
97 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
98 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
99 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
100 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
101 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
102 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
103 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
104 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
105 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
106 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
107 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
108 };
109
110 static struct nand_ecclayout brcmnand_oob_128 = {
111 .eccbytes = 24,
112 .eccpos =
113 {
114 6, 7, 8,
115 22, 23, 24,
116 38, 39, 40,
117 54, 55, 56,
118 70, 71, 72,
119 86, 87, 88,
120 102, 103, 104,
121 118, 119, 120
122 },
123 .oobfree =
124 {
125 /* 0-1 used for BBT and/or manufacturer bad block marker,
126 * first slice loses 2 bytes for BBT
127 */
128 {.offset = 2, .length = 4},
129 {.offset = 9, .length = 13},
130 /* First slice {9,7} 2nd slice {16,6}are combined */
131 /* ST uses 6th byte (offset=5) as Bad Block Indicator,
132 * in addition to the 1st byte, and will be adjusted at run time
133 */
134 {.offset = 25, .length = 13}, /* 2nd slice */
135 {.offset = 41, .length = 13}, /* 4th slice */
136 {.offset = 57, .length = 13}, /* 5th slice */
137 {.offset = 73, .length = 13}, /* 6th slice */
138 {.offset = 89, .length = 13}, /* 7th slice */
139 {.offset = 105, .length = 13}, /* 8th slice */
140 {.offset = 121, .length = 7}, /* 9th slice */
141 {.offset = 0, .length = 0} /* End marker */
142 }
143 };
144
145 static struct nand_ecclayout brcmnand_oob_64 = {
146 .eccbytes = 12,
147 .eccpos =
148 {
149 6, 7, 8,
150 22, 23, 24,
151 38, 39, 40,
152 54, 55, 56
153 },
154 .oobfree =
155 {
156 /* 0-1 used for BBT and/or manufacturer bad block marker,
157 * first slice loses 2 bytes for BBT
158 */
159 {.offset = 2, .length = 4},
160 {.offset = 9, .length = 13},
161 /* First slice {9,7} 2nd slice {16,6}are combined */
162 /* ST uses 6th byte (offset=5) as Bad Block Indicator,
163 * in addition to the 1st byte, and will be adjusted at run time
164 */
165 {.offset = 25, .length = 13}, /* 2nd slice */
166 {.offset = 41, .length = 13}, /* 3rd slice */
167 {.offset = 57, .length = 7}, /* 4th slice */
168 {.offset = 0, .length = 0} /* End marker */
169 }
170 };
171
172 /**
173 * brcmnand_oob oob info for 512 page
174 */
175 static struct nand_ecclayout brcmnand_oob_16 = {
176 .eccbytes = 3,
177 .eccpos = {6, 7, 8},
178 .oobfree = {
179 {.offset = 0, .length = 5},
180 {.offset = 9, .length = 7}, /* Byte 5 (6th byte) used for BI */
181 {.offset = 0, .length = 0}} /* End marker */
182 /* Bytes offset 4&5 are used by BBT. Actually only byte 5 is used,
183 * but in order to accomodate for 16 bit bus width, byte 4 is also not used.
184 * If we only use byte-width chip, (We did)
185 * then we can also use byte 4 as free bytes.
186 */
187 };
188
189 /* Small page with BCH-4 */
190 static struct nand_ecclayout brcmnand_oob_bch4_512 = {
191 .eccbytes = 7,
192 .eccpos = {9, 10, 11, 12, 13, 14, 15},
193 .oobfree = {
194 {.offset = 0, .length = 5},
195 {.offset = 7, .length = 2}, /* Byte 5 (6th byte) used for BI */
196 {.offset = 0, .length = 0}} /* End marker */
197 };
198
199 /*
200 * 2K page SLC/MLC with BCH-4 ECC, uses 7 ECC bytes per 512B ECC step
201 */
202 static struct nand_ecclayout brcmnand_oob_bch4_2k = {
203 .eccbytes = 7 * 8, /* 7 * 8 = 56 bytes */
204 .eccpos =
205 {
206 9, 10, 11, 12, 13, 14, 15,
207 25, 26, 27, 28, 29, 30, 31,
208 41, 42, 43, 44, 45, 46, 47,
209 57, 58, 59, 60, 61, 62, 63
210 },
211 .oobfree =
212 {
213 /* 0 used for BBT and/or manufacturer bad block marker,
214 * first slice loses 1 byte for BBT
215 */
216 {.offset = 1, .length = 8}, /* 1st slice loses byte 0 */
217 {.offset = 16, .length = 9}, /* 2nd slice */
218 {.offset = 32, .length = 9}, /* 3rd slice */
219 {.offset = 48, .length = 9}, /* 4th slice */
220 {.offset = 0, .length = 0} /* End marker */
221 }
222 };
223
224
225 static void *page_buffer = NULL;
226
227 /* Private global state */
228 struct brcmnand_mtd brcmnand_info;
229
230 static INLINE void
231 brcmnand_cmd(osl_t *osh, chipcregs_t *cc, uint opcode)
232 {
233 W_REG(osh, &cc->nand_cmd_start, opcode);
234 /* read after write to flush the command */
235 R_REG(osh, &cc->nand_cmd_start);
236 }
237
238 int brcmnand_ctrl_verify_ecc(struct nand_chip *chip, int state)
239 {
240 si_t *sih = brcmnand_info.sih;
241 chipcregs_t *cc = brcmnand_info.cc;
242 osl_t *osh;
243 uint32_t addr, ext_addr;
244 int err = 0;
245
246 if (state != FL_READING)
247 return BRCMNAND_SUCCESS;
248 osh = si_osh(sih);
249 addr = R_REG(osh, &cc->nand_ecc_corr_addr);
250 if (addr) {
251 ext_addr = R_REG(osh, &cc->nand_ecc_corr_addr_x);
252 /* clear */
253 W_REG(osh, &cc->nand_ecc_corr_addr, 0);
254 W_REG(osh, &cc->nand_ecc_corr_addr_x, 0);
255 err = BRCMNAND_CORRECTABLE_ECC_ERROR;
256 }
257 addr = R_REG(osh, &cc->nand_ecc_unc_addr);
258 if (addr) {
259 ext_addr = R_REG(osh, &cc->nand_ecc_unc_addr_x);
260 /* clear */
261 W_REG(osh, &cc->nand_ecc_unc_addr, 0);
262 W_REG(osh, &cc->nand_ecc_unc_addr_x, 0);
263 /* If the block was just erased, and have not yet been written to,
264 * this will be flagged, so this could be a false alarm
265 */
266 err = BRCMNAND_UNCORRECTABLE_ECC_ERROR;
267 }
268 return (err);
269 }
270
271 uint32 brcmnand_poll(uint32 pollmask)
272 {
273 si_t *sih = brcmnand_info.sih;
274 chipcregs_t *cc = brcmnand_info.cc;
275 osl_t *osh;
276 uint32 status;
277
278 osh = si_osh(sih);
279 status = R_REG(osh, &cc->nand_intfc_status);
280 status &= pollmask;
281
282 return status;
283 }
284
285 int brcmnand_cache_is_valid(struct mtd_info *mtd, struct nand_chip *chip, int state)
286 {
287 uint32 pollmask = NIST_CTRL_READY | 0x1;
288 unsigned long timeout = msecs_to_jiffies(BRCMNAND_POLL_TIMEOUT);
289 unsigned long now = jiffies;
290 uint32 status = 0;
291 int ret;
292
293 for (;;) {
294 if ((status = brcmnand_poll(pollmask)) != 0) {
295 break;
296 }
297 if (time_after(jiffies, now + timeout)) {
298 status = brcmnand_poll(pollmask);
299 break;
300 }
301 udelay(1);
302 }
303
304 if (status == 0)
305 ret = BRCMNAND_TIMED_OUT;
306 else if (status & 0x1)
307 ret = BRCMNAND_FLASH_STATUS_ERROR;
308 else
309 ret = brcmnand_ctrl_verify_ecc(chip, state);
310
311 return ret;
312 }
313
314 int brcmnand_spare_is_valid(struct mtd_info *mtd, struct nand_chip *chip, int state)
315 {
316 uint32 pollmask = NIST_CTRL_READY;
317 unsigned long timeout = msecs_to_jiffies(BRCMNAND_POLL_TIMEOUT);
318 unsigned long now = jiffies;
319 uint32 status = 0;
320 int ret;
321
322 for (;;) {
323 if ((status = brcmnand_poll(pollmask)) != 0) {
324 break;
325 }
326 if (time_after(jiffies, now + timeout)) {
327 status = brcmnand_poll(pollmask);
328 break;
329 }
330 udelay(1);
331 }
332
333 if (status == 0)
334 ret = 0 /* timed out */;
335 else
336 ret = 1;
337
338 return ret;
339 }
340
341 /**
342 * nand_release_device - [GENERIC] release chip
343 * @mtd: MTD device structure
344 *
345 * Deselect, release chip lock and wake up anyone waiting on the device
346 */
347 static void brcmnand_release_device(struct mtd_info *mtd)
348 {
349 if (nflash_lock == 1) {
350 nflash_enable(brcmnand_info.sih, 0);
351 mutex_unlock(mtd->mutex);
352 }
353 nflash_lock --;
354 }
355
356 /**
357 * brcmnand_get_device - [GENERIC] Get chip for selected access
358 * @param chip the nand chip descriptor
359 * @param mtd MTD device structure
360 * @param new_state the state which is requested
361 *
362 * Get the device and lock it for exclusive access
363 */
364 static int brcmnand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
365 {
366 if (nflash_lock == 0) {
367 mutex_lock(mtd->mutex);
368 nflash_enable(brcmnand_info.sih, 1);
369 }
370 nflash_lock ++;
371 return 0;
372 }
373
374 /**
375 * brcmnand_release_device_bcm4706 - [GENERIC] release chip
376 * @mtd: MTD device structure
377 *
378 * Deselect, release chip lock and wake up anyone waiting on the device
379 */
380 static void
381 brcmnand_release_device_bcm4706(struct mtd_info *mtd)
382 {
383 mutex_unlock(mtd->mutex);
384 }
385
386 /**
387 * brcmnand_get_device_bcm4706 - [GENERIC] Get chip for selected access
388 * @param chip the nand chip descriptor
389 * @param mtd MTD device structure
390 * @param new_state the state which is requested
391 *
392 * Get the device and lock it for exclusive access
393 */
394 static int
395 brcmnand_get_device_bcm4706(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
396 {
397 mutex_lock(mtd->mutex);
398 return 0;
399 }
400
401 /**
402 * brcmnand_block_checkbad - [GENERIC] Check if a block is marked bad
403 * @mtd: MTD device structure
404 * @ofs: offset from device start
405 * @getchip: 0, if the chip is already selected
406 * @allowbbt: 1, if its allowed to access the bbt area
407 *
408 * Check, if the block is bad. Either by reading the bad block table or
409 * calling of the scan function.
410 */
411 static int brcmnand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
412 int allowbbt)
413 {
414 struct nand_chip *chip = mtd->priv;
415 int ret;
416
417 if (getchip)
418 brcmnand_get_device(chip, mtd, FL_READING);
419
420 if (!chip->bbt)
421 ret = chip->block_bad(mtd, ofs, getchip);
422 else
423 ret = brcmnand_isbad_bbt(mtd, ofs, allowbbt);
424
425 if (getchip)
426 brcmnand_release_device(mtd);
427 return (ret);
428 }
429
430 /*
431 * Returns 0 on success
432 */
433 static int brcmnand_handle_false_read_ecc_unc_errors(struct mtd_info *mtd,
434 struct nand_chip *chip, uint8_t *buf, uint8_t *oob, uint32_t offset)
435 {
436 static uint32_t oobbuf[4];
437 uint32_t *p32 = (oob ? (uint32_t *)oob : (uint32_t *)&oobbuf[0]);
438 int ret = 0;
439 uint8_t *oobarea;
440 int erased = 0, allFF = 0;
441 int i;
442 si_t *sih = brcmnand_info.sih;
443 chipcregs_t *cc = brcmnand_info.cc;
444 osl_t *osh;
445
446 osh = si_osh(sih);
447 oobarea = (uint8_t *)p32;
448 for (i = 0; i < 4; i++) {
449 p32[i] = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + (i * 4)));
450 }
451 if (chip->ecc.level == BRCMNAND_ECC_HAMMING) {
452 erased =
453 (oobarea[6] == 0xff && oobarea[7] == 0xff && oobarea[8] == 0xff);
454 allFF =
455 (oobarea[6] == 0x00 && oobarea[7] == 0x00 && oobarea[8] == 0x00);
456 } else if (chip->ecc.level >= BRCMNAND_ECC_BCH_1 &&
457 chip->ecc.level <= BRCMNAND_ECC_BCH_12) {
458 erased = allFF = 1;
459 /* For BCH-n, the ECC bytes are at the end of the OOB area */
460 for (i = chip->ecc.oobsize - chip->ecc.bytes; i < chip->ecc.oobsize; i++) {
461 erased = erased && (oobarea[i] == 0xff);
462 allFF = allFF && (oobarea[i] == 0x00);
463 }
464 } else {
465 printk("BUG: Unsupported ECC level %d\n", chip->ecc.level);
466 BUG();
467 }
468
469 if (erased || allFF) {
470 /*
471 * For the first case, the slice is an erased block, and the ECC bytes
472 * are all 0xFF, for the 2nd, all bytes are 0xFF, so the Hamming Codes
473 * for it are all zeroes. The current version of the BrcmNAND
474 * controller treats these as un-correctable errors. For either case,
475 * fill data buffer with 0xff and return success. The error has
476 * already been cleared inside brcmnand_verify_ecc. Both case will be
477 * handled correctly by the BrcmNand controller in later releases.
478 */
479 p32 = (uint32_t *)buf;
480 for (i = 0; i < chip->ecc.size/4; i++) {
481 p32[i] = 0xFFFFFFFF;
482 }
483 ret = 0; /* Success */
484 } else {
485 /* Real error: Disturb read returns uncorrectable errors */
486 ret = -EBADMSG;
487 printk("<-- %s: ret -EBADMSG\n", __FUNCTION__);
488 }
489 return ret;
490 }
491
492 static int brcmnand_posted_read_cache(struct mtd_info *mtd, struct nand_chip *chip,
493 uint8_t *buf, uint8_t *oob, uint32_t offset)
494 {
495 uint32_t mask = chip->ecc.size - 1;
496 si_t *sih = brcmnand_info.sih;
497 chipcregs_t *cc = brcmnand_info.cc;
498 osl_t *osh;
499 int valid;
500 uint32_t *to;
501 int ret = 0, i;
502
503 if (offset & mask)
504 return -EINVAL;
505
506 osh = si_osh(sih);
507 W_REG(osh, &cc->nand_cmd_addr, offset);
508 PLATFORM_IOFLUSH_WAR();
509 brcmnand_cmd(osh, cc, NCMD_PAGE_RD);
510 valid = brcmnand_cache_is_valid(mtd, chip, FL_READING);
511
512 switch (valid) {
513 case BRCMNAND_CORRECTABLE_ECC_ERROR:
514 case BRCMNAND_SUCCESS:
515 if (buf) {
516 to = (uint32_t *)buf;
517 PLATFORM_IOFLUSH_WAR();
518 for (i = 0; i < chip->ecc.size; i += 4, to++) {
519 *to = R_REG(osh, &cc->nand_cache_data);
520 }
521 }
522 if (oob) {
523 to = (uint32_t *)oob;
524 PLATFORM_IOFLUSH_WAR();
525 for (i = 0; i < chip->ecc.oobsize; i += 4, to++) {
526 *to = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + i));
527 }
528 }
529 break;
530 case BRCMNAND_UNCORRECTABLE_ECC_ERROR:
531 ret = brcmnand_handle_false_read_ecc_unc_errors(mtd, chip, buf, oob, offset);
532 break;
533 case BRCMNAND_FLASH_STATUS_ERROR:
534 ret = -EBADMSG;
535 break;
536 case BRCMNAND_TIMED_OUT:
537 ret = -ETIMEDOUT;
538 break;
539 default:
540 ret = -EFAULT;
541 break;
542 }
543
544 return (ret);
545 }
546
547 /**
548 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
549 * @mtd: mtd info structure
550 * @chip: nand chip info structure
551 * @buf: buffer to store read data
552 *
553 * Not for syndrome calculating ecc controllers which need a special oob layout
554 */
555 static int brcmnand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
556 uint8_t *buf)
557 {
558 int eccsteps;
559 int data_read = 0;
560 int oob_read = 0;
561 int corrected = 0;
562 int ret = 0;
563 uint32_t offset = chip->pageidx << chip->page_shift;
564 uint8_t *oob = chip->oob_poi;
565
566 brcmnand_get_device(chip, mtd, FL_READING);
567 for (eccsteps = 0; eccsteps < chip->ecc.steps; eccsteps++) {
568 ret = brcmnand_posted_read_cache(mtd, chip, &buf[data_read],
569 oob ? &oob[oob_read]: NULL, offset + data_read);
570 if (ret == BRCMNAND_CORRECTABLE_ECC_ERROR && !corrected) {
571 mtd->ecc_stats.corrected++;
572 corrected = 1;
573 ret = 0;
574 } else {
575 if (ret < 0)
576 break;
577 }
578 data_read += chip->ecc.size;
579 oob_read += chip->ecc.oobsize;
580 }
581 brcmnand_release_device(mtd);
582 return (ret);
583 }
584
585 /**
586 * brcmnand_transfer_oob - [Internal] Transfer oob to client buffer
587 * @chip: nand chip structure
588 * @oob: oob destination address
589 * @ops: oob ops structure
590 * @len: size of oob to transfer
591 */
592 static uint8_t *brcmnand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
593 struct mtd_oob_ops *ops, size_t len)
594 {
595 switch (ops->mode) {
596
597 case MTD_OOB_PLACE:
598 case MTD_OOB_RAW:
599 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
600 return oob + len;
601
602 case MTD_OOB_AUTO: {
603 struct nand_oobfree *free = chip->ecc.layout->oobfree;
604 uint32_t boffs = 0, roffs = ops->ooboffs;
605 size_t bytes = 0;
606
607 for (; free->length && len; free++, len -= bytes) {
608 /* Read request not from offset 0 ? */
609 if (unlikely(roffs)) {
610 if (roffs >= free->length) {
611 roffs -= free->length;
612 continue;
613 }
614 boffs = free->offset + roffs;
615 bytes = min_t(size_t, len,
616 (free->length - roffs));
617 roffs = 0;
618 } else {
619 bytes = min_t(size_t, len, free->length);
620 boffs = free->offset;
621 }
622 memcpy(oob, chip->oob_poi + boffs, bytes);
623 oob += bytes;
624 }
625 return oob;
626 }
627 default:
628 BUG();
629 }
630 return NULL;
631 }
632
633 /**
634 * brcmnand_do_read_ops - [Internal] Read data with ECC
635 *
636 * @mtd: MTD device structure
637 * @from: offset to read from
638 * @ops: oob ops structure
639 *
640 * Internal function. Called with chip held.
641 */
642 static int brcmnand_do_read_ops(struct mtd_info *mtd, loff_t from,
643 struct mtd_oob_ops *ops)
644 {
645 int page, realpage, col, bytes, aligned;
646 struct nand_chip *chip = mtd->priv;
647 struct mtd_ecc_stats stats;
648 int ret = 0;
649 uint32_t readlen = ops->len;
650 uint32_t oobreadlen = ops->ooblen;
651 uint8_t *bufpoi, *oob, *buf;
652
653 stats = mtd->ecc_stats;
654
655 realpage = (int)(from >> chip->page_shift);
656 page = realpage & chip->pagemask;
657
658 col = (int)(from & (mtd->writesize - 1));
659
660 buf = ops->datbuf;
661 oob = ops->oobbuf;
662
663 while (1) {
664 bytes = min(mtd->writesize - col, readlen);
665 aligned = (bytes == mtd->writesize);
666
667 /* Is the current page in the buffer ? */
668 if (realpage != chip->pagebuf || oob) {
669 bufpoi = aligned ? buf : chip->buffers->databuf;
670 chip->pageidx = page;
671 /* Now read the page into the buffer */
672 ret = chip->ecc.read_page(mtd, chip, bufpoi);
673 if (ret < 0)
674 break;
675
676 /* Transfer not aligned data */
677 if (!aligned) {
678 chip->pagebuf = realpage;
679 memcpy(buf, chip->buffers->databuf + col, bytes);
680 }
681
682 buf += bytes;
683
684 if (unlikely(oob)) {
685 if (ops->mode != MTD_OOB_RAW) {
686 int toread = min(oobreadlen,
687 chip->ecc.layout->oobavail);
688 if (toread) {
689 oob = brcmnand_transfer_oob(chip,
690 oob, ops, toread);
691 oobreadlen -= toread;
692 }
693 } else
694 buf = brcmnand_transfer_oob(chip,
695 buf, ops, mtd->oobsize);
696 }
697 } else {
698 memcpy(buf, chip->buffers->databuf + col, bytes);
699 buf += bytes;
700 }
701
702 readlen -= bytes;
703
704 if (!readlen)
705 break;
706
707 /* For subsequent reads align to page boundary. */
708 col = 0;
709 /* Increment page address */
710 realpage++;
711
712 page = realpage & chip->pagemask;
713 }
714
715 ops->retlen = ops->len - (size_t) readlen;
716 if (oob)
717 ops->oobretlen = ops->ooblen - oobreadlen;
718
719 if (ret)
720 return ret;
721
722 if (mtd->ecc_stats.failed - stats.failed)
723 return -EBADMSG;
724
725 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
726 }
727
728 /**
729 * brcmnand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
730 * @mtd: MTD device structure
731 * @from: offset to read from
732 * @len: number of bytes to read
733 * @retlen: pointer to variable to store the number of read bytes
734 * @buf: the databuffer to put data
735 *
736 * Get hold of the chip and call nand_do_read
737 */
738 static int
739 brcmnand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
740 {
741 struct nand_chip *chip = mtd->priv;
742 int ret;
743
744 if ((from + len) > mtd->size)
745 return -EINVAL;
746 if (!len)
747 return 0;
748
749 brcmnand_get_device(chip, mtd, FL_READING);
750 chip->ops.len = len;
751 chip->ops.datbuf = buf;
752 chip->ops.oobbuf = NULL;
753
754 ret = brcmnand_do_read_ops(mtd, from, &chip->ops);
755
756 *retlen = chip->ops.retlen;
757
758 brcmnand_release_device(mtd);
759
760 return ret;
761 }
762
763 static int brcmnand_posted_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
764 uint8_t *oob, uint32_t offset)
765 {
766 uint32_t mask = chip->ecc.size - 1;
767 si_t *sih = brcmnand_info.sih;
768 chipcregs_t *cc = brcmnand_info.cc;
769 osl_t *osh;
770 int valid;
771 uint32 *to;
772 int ret = 0, i;
773
774 if (offset & mask)
775 return -EINVAL;
776
777 osh = si_osh(sih);
778 W_REG(osh, &cc->nand_cmd_addr, offset);
779 PLATFORM_IOFLUSH_WAR();
780 brcmnand_cmd(osh, cc, NCMD_SPARE_RD);
781 valid = brcmnand_spare_is_valid(mtd, chip, FL_READING);
782
783 switch (valid) {
784 case 1:
785 if (oob) {
786 to = (uint32 *)oob;
787 for (i = 0; i < chip->ecc.oobsize; i += 4, to++) {
788 *to = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + i));
789 }
790 }
791 break;
792 case 0:
793 ret = -ETIMEDOUT;
794 break;
795 default:
796 ret = -EFAULT;
797 break;
798 }
799 return (ret);
800 }
801
802 /**
803 * brcmnand_read_oob_hwecc - [REPLACABLE] the most common OOB data read function
804 * @mtd: mtd info structure
805 * @chip: nand chip info structure
806 * @page: page number to read
807 * @sndcmd: flag whether to issue read command or not
808 */
809 static int brcmnand_read_oob_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
810 int page, int sndcmd)
811 {
812 int eccsteps;
813 int data_read = 0;
814 int oob_read = 0;
815 int corrected = 0;
816 int ret = 0;
817 uint32_t offset = page << chip->page_shift;
818 uint8_t *oob = chip->oob_poi;
819
820 for (eccsteps = 0; eccsteps < chip->ecc.steps; eccsteps++) {
821 ret = brcmnand_posted_read_oob(mtd, chip, &oob[oob_read], offset + data_read);
822 if (ret == BRCMNAND_CORRECTABLE_ECC_ERROR && !corrected) {
823 mtd->ecc_stats.corrected++;
824 /* Only update stats once per page */
825 corrected = 1;
826 ret = 0;
827 } else {
828 if (ret < 0)
829 break;
830 }
831 data_read += chip->ecc.size;
832 oob_read += chip->ecc.oobsize;
833 }
834
835 return (ret);
836 }
837
838 /**
839 * brcmnand_do_read_oob - [Intern] NAND read out-of-band
840 * @mtd: MTD device structure
841 * @from: offset to read from
842 * @ops: oob operations description structure
843 *
844 * NAND read out-of-band data from the spare area
845 */
846 static int brcmnand_do_read_oob(struct mtd_info *mtd, loff_t from,
847 struct mtd_oob_ops *ops)
848 {
849 int page, realpage;
850 struct nand_chip *chip = mtd->priv;
851 int readlen = ops->ooblen;
852 int len;
853 uint8_t *buf = ops->oobbuf;
854 int ret;
855
856 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
857 (unsigned long long)from, readlen);
858
859 if (ops->mode == MTD_OOB_AUTO)
860 len = chip->ecc.layout->oobavail;
861 else
862 len = mtd->oobsize;
863
864 if (unlikely(ops->ooboffs >= len)) {
865 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
866 "Attempt to start read outside oob\n");
867 return -EINVAL;
868 }
869
870 /* Do not allow reads past end of device */
871 if (unlikely(from >= mtd->size ||
872 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
873 (from >> chip->page_shift)) * len)) {
874 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
875 "Attempt read beyond end of device\n");
876 return -EINVAL;
877 }
878 /* Shift to get page */
879 realpage = (int)(from >> chip->page_shift);
880 page = realpage & chip->pagemask;
881
882 while (1) {
883 ret = chip->ecc.read_oob(mtd, chip, page, 0);
884 if (ret)
885 break;
886 len = min(len, readlen);
887 buf = brcmnand_transfer_oob(chip, buf, ops, len);
888
889 readlen -= len;
890 if (!readlen)
891 break;
892
893 /* Increment page address */
894 realpage++;
895
896 page = realpage & chip->pagemask;
897 }
898
899 ops->oobretlen = ops->ooblen;
900 return (ret);
901 }
902
903 /**
904 * brcmnand_read_oob - [MTD Interface] NAND read data and/or out-of-band
905 * @mtd: MTD device structure
906 * @from: offset to read from
907 * @ops: oob operation description structure
908 *
909 * NAND read data and/or out-of-band data
910 */
911 static int brcmnand_read_oob(struct mtd_info *mtd, loff_t from,
912 struct mtd_oob_ops *ops)
913 {
914 struct nand_chip *chip = mtd->priv;
915 int ret = -ENOTSUPP;
916
917 ops->retlen = 0;
918
919 /* Do not allow reads past end of device */
920 if (ops->datbuf && (from + ops->len) > mtd->size) {
921 DEBUG(MTD_DEBUG_LEVEL0, "brcmnand_read_oob: "
922 "Attempt read beyond end of device\n");
923 return -EINVAL;
924 }
925
926 brcmnand_get_device(chip, mtd, FL_READING);
927
928 switch (ops->mode) {
929 case MTD_OOB_PLACE:
930 case MTD_OOB_AUTO:
931 case MTD_OOB_RAW:
932 break;
933
934 default:
935 goto out;
936 }
937
938 if (!ops->datbuf)
939 ret = brcmnand_do_read_oob(mtd, from, ops);
940 else
941 ret = brcmnand_do_read_ops(mtd, from, ops);
942
943 out:
944 brcmnand_release_device(mtd);
945 return ret;
946 }
947
948 static int brcmnand_ctrl_write_is_complete(struct mtd_info *mtd, struct nand_chip *chip,
949 int *need_bbt)
950 {
951 uint32 pollmask = NIST_CTRL_READY | 0x1;
952 unsigned long timeout = msecs_to_jiffies(BRCMNAND_POLL_TIMEOUT);
953 unsigned long now = jiffies;
954 uint32 status = 0;
955 int ret;
956
957 for (;;) {
958 if ((status = brcmnand_poll(pollmask)) != 0) {
959 break;
960 }
961 if (time_after(jiffies, now + timeout)) {
962 status = brcmnand_poll(pollmask);
963 break;
964 }
965 udelay(1);
966 }
967
968 *need_bbt = 0;
969 if (status == 0)
970 ret = 0; /* timed out */
971 else {
972 ret = 1;
973 if (status & 0x1)
974 *need_bbt = 1;
975 }
976
977 return ret;
978 }
979
980 /**
981 * brcmnand_posted_write - [BrcmNAND Interface] Write a buffer to the flash
982 * cache
983 * Assuming brcmnand_get_device() has been called to obtain exclusive lock
984 *
985 * @param mtd MTD data structure
986 * @param chip nand chip info structure
987 * @param buf the databuffer to put/get data
988 * @param oob Spare area, pass NULL if not interested
989 * @param offset offset to write to, and must be 512B aligned
990 *
991 */
992 static int brcmnand_posted_write_cache(struct mtd_info *mtd, struct nand_chip *chip,
993 const uint8_t *buf, uint8_t *oob, uint32_t offset)
994 {
995 uint32_t mask = chip->ecc.size - 1;
996 si_t *sih = brcmnand_info.sih;
997 chipcregs_t *cc = brcmnand_info.cc;
998 osl_t *osh;
999 int i, ret = 0;
1000 uint32_t *from;
1001
1002 if (offset & mask) {
1003 ret = -EINVAL;
1004 goto out;
1005 }
1006
1007 osh = si_osh(sih);
1008 from = (uint32_t *)buf;
1009 for (i = 0; i < chip->ecc.size; i += 4, from++) {
1010 W_REG(osh, &cc->nand_cache_data, *from);
1011 }
1012 out:
1013 return (ret);
1014 }
1015
1016 /**
1017 * brcmnand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1018 * @mtd: mtd info structure
1019 * @chip: nand chip info structure
1020 * @buf: data buffer
1021 */
1022 static void brcmnand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1023 const uint8_t *buf)
1024 {
1025 int eccsize = chip->ecc.size;
1026 int eccsteps;
1027 int data_written = 0;
1028 int oob_written = 0;
1029 si_t *sih = brcmnand_info.sih;
1030 chipcregs_t *cc = brcmnand_info.cc;
1031 osl_t *osh;
1032 uint32_t reg;
1033 int ret = 0, need_bbt = 0;
1034 uint32_t offset = chip->pageidx << chip->page_shift;
1035
1036 uint8_t oob_buf[NAND_MAX_OOBSIZE];
1037 int *eccpos = chip->ecc.layout->eccpos;
1038 int i;
1039 uint8_t *oob = chip->oob_poi;
1040
1041 brcmnand_get_device(chip, mtd, FL_READING);
1042 osh = si_osh(sih);
1043 /* full page write */
1044 /* disable partial page enable */
1045 reg = R_REG(osh, &cc->nand_acc_control);
1046 reg &= ~NAC_PARTIAL_PAGE_EN;
1047 W_REG(osh, &cc->nand_acc_control, reg);
1048
1049 for (eccsteps = 0; eccsteps < chip->ecc.steps; eccsteps++) {
1050 W_REG(osh, &cc->nand_cache_addr, 0);
1051 W_REG(osh, &cc->nand_cmd_addr, data_written);
1052 ret = brcmnand_posted_write_cache(mtd, chip, &buf[data_written],
1053 oob ? &oob[oob_written]: NULL, offset + data_written);
1054 if (ret < 0) {
1055 goto out;
1056 }
1057 data_written += eccsize;
1058 oob_written += chip->ecc.oobsize;
1059 }
1060
1061 W_REG(osh, &cc->nand_cmd_addr, offset + mtd->writesize - NFL_SECTOR_SIZE);
1062 brcmnand_cmd(osh, cc, NCMD_PAGE_PROG);
1063 if (brcmnand_ctrl_write_is_complete(mtd, chip, &need_bbt)) {
1064 if (!need_bbt) {
1065 /* write the oob */
1066 if (oob) {
1067 /* Enable partial page program so that we can
1068 * overwrite the spare area
1069 */
1070 reg = R_REG(osh, &cc->nand_acc_control);
1071 reg |= NAC_PARTIAL_PAGE_EN;
1072 W_REG(osh, &cc->nand_acc_control, reg);
1073
1074 memcpy(oob_buf, oob, NAND_MAX_OOBSIZE);
1075 /* read from the spare area first */
1076 ret = chip->ecc.read_oob(mtd, chip, chip->pageidx, 0);
1077 if (ret != 0)
1078 goto out;
1079 /* merge the oob */
1080 for (i = 0; i < chip->ecc.total; i++)
1081 oob_buf[eccpos[i]] = chip->oob_poi[eccpos[i]];
1082 memcpy(chip->oob_poi, oob_buf, NAND_MAX_OOBSIZE);
1083 /* write back to the spare area */
1084 ret = chip->ecc.write_oob(mtd, chip, chip->pageidx);
1085 }
1086 goto out;
1087 } else {
1088 ret = chip->block_markbad(mtd, offset);
1089 goto out;
1090 }
1091 }
1092 /* timed out */
1093 ret = -ETIMEDOUT;
1094
1095 out:
1096 if (ret != 0)
1097 printk(KERN_ERR "brcmnand_write_page_hwecc failed\n");
1098 brcmnand_release_device(mtd);
1099 return;
1100 }
1101
1102 /*
1103 * brcmnand_posted_write_oob - [BrcmNAND Interface] Write the spare area
1104 * @mtd: MTD data structure
1105 * @chip: nand chip info structure
1106 * @oob: Spare area, pass NULL if not interested. Must be able to
1107 * hold mtd->oobsize (16) bytes.
1108 * @offset: offset to write to, and must be 512B aligned
1109 *
1110 */
1111 static int brcmnand_posted_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1112 uint8_t *oob, uint32_t offset)
1113 {
1114 uint32_t mask = chip->ecc.size - 1;
1115 si_t *sih = brcmnand_info.sih;
1116 chipcregs_t *cc = brcmnand_info.cc;
1117 osl_t *osh;
1118 int i, ret = 0, need_bbt = 0;
1119 uint32_t *from;
1120 uint32_t reg;
1121 uint8_t oob_buf0[16];
1122
1123 if (offset & mask) {
1124 ret = -EINVAL;
1125 goto out;
1126 }
1127
1128 osh = si_osh(sih);
1129 /* Make sure we are in partial page program mode */
1130 reg = R_REG(osh, &cc->nand_acc_control);
1131 reg |= NAC_PARTIAL_PAGE_EN;
1132 W_REG(osh, &cc->nand_acc_control, reg);
1133
1134 W_REG(osh, &cc->nand_cmd_addr, offset);
1135 if (!oob) {
1136 ret = -EINVAL;
1137 goto out;
1138 }
1139 memcpy(oob_buf0, oob, chip->ecc.oobsize);
1140 from = (uint32_t *)oob_buf0;
1141 for (i = 0; i < chip->ecc.oobsize; i += 4, from++) {
1142 W_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_wr0 + i), *from);
1143 }
1144 PLATFORM_IOFLUSH_WAR();
1145 brcmnand_cmd(osh, cc, NCMD_SPARE_PROG);
1146 if (brcmnand_ctrl_write_is_complete(mtd, chip, &need_bbt)) {
1147 if (!need_bbt) {
1148 ret = 0;
1149 goto out;
1150 } else {
1151 ret = chip->block_markbad(mtd, offset);
1152 goto out;
1153 }
1154 }
1155 /* timed out */
1156 ret = -ETIMEDOUT;
1157 out:
1158 return ret;
1159 }
1160
1161
1162 /**
1163 * brcmnand_write_page - [REPLACEABLE] write one page
1164 * @mtd: MTD device structure
1165 * @chip: NAND chip descriptor
1166 * @buf: the data to write
1167 * @page: page number to write
1168 * @cached: cached programming
1169 * @raw: use _raw version of write_page
1170 */
1171 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1172 const uint8_t *buf, int page, int cached, int raw)
1173 {
1174 chip->pageidx = page;
1175 chip->ecc.write_page(mtd, chip, buf);
1176
1177 return 0;
1178 }
1179
1180 /**
1181 * brcmnand_fill_oob - [Internal] Transfer client buffer to oob
1182 * @chip: nand chip structure
1183 * @oob: oob data buffer
1184 * @ops: oob ops structure
1185 */
1186 static uint8_t *brcmnand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1187 struct mtd_oob_ops *ops)
1188 {
1189 size_t len = ops->ooblen;
1190
1191 switch (ops->mode) {
1192
1193 case MTD_OOB_PLACE:
1194 case MTD_OOB_RAW:
1195 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1196 return oob + len;
1197
1198 case MTD_OOB_AUTO: {
1199 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1200 uint32_t boffs = 0, woffs = ops->ooboffs;
1201 size_t bytes = 0;
1202
1203 for (; free->length && len; free++, len -= bytes) {
1204 /* Write request not from offset 0 ? */
1205 if (unlikely(woffs)) {
1206 if (woffs >= free->length) {
1207 woffs -= free->length;
1208 continue;
1209 }
1210 boffs = free->offset + woffs;
1211 bytes = min_t(size_t, len,
1212 (free->length - woffs));
1213 woffs = 0;
1214 } else {
1215 bytes = min_t(size_t, len, free->length);
1216 boffs = free->offset;
1217 }
1218 memcpy(chip->oob_poi + boffs, oob, bytes);
1219 oob += bytes;
1220 }
1221 return oob;
1222 }
1223 default:
1224 BUG();
1225 }
1226 return NULL;
1227 }
1228
1229 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1230
1231 /**
1232 * brcmnand_do_write_ops - [Internal] NAND write with ECC
1233 * @mtd: MTD device structure
1234 * @to: offset to write to
1235 * @ops: oob operations description structure
1236 *
1237 * NAND write with ECC
1238 */
1239 static int brcmnand_do_write_ops(struct mtd_info *mtd, loff_t to,
1240 struct mtd_oob_ops *ops)
1241 {
1242 int realpage, page, blockmask;
1243 struct nand_chip *chip = mtd->priv;
1244 uint32_t writelen = ops->len;
1245 uint8_t *oob = ops->oobbuf;
1246 uint8_t *buf = ops->datbuf;
1247 int ret;
1248
1249 ops->retlen = 0;
1250 if (!writelen)
1251 return 0;
1252
1253 /* reject writes, which are not page aligned */
1254 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1255 printk(KERN_NOTICE "nand_write: "
1256 "Attempt to write not page aligned data\n");
1257 return -EINVAL;
1258 }
1259
1260
1261 realpage = (int)(to >> chip->page_shift);
1262 page = realpage & chip->pagemask;
1263 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1264
1265 /* Invalidate the page cache, when we write to the cached page */
1266 if (to <= (chip->pagebuf << chip->page_shift) &&
1267 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1268 chip->pagebuf = -1;
1269
1270 /* If we're not given explicit OOB data, let it be 0xFF */
1271 if (likely(!oob))
1272 memset(chip->oob_poi, 0xff, mtd->oobsize);
1273
1274 while (1) {
1275 int bytes = mtd->writesize;
1276 int cached = writelen > bytes && page != blockmask;
1277 uint8_t *wbuf = buf;
1278
1279 if (unlikely(oob))
1280 oob = brcmnand_fill_oob(chip, oob, ops);
1281
1282 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1283 (ops->mode == MTD_OOB_RAW));
1284 if (ret)
1285 break;
1286
1287 writelen -= bytes;
1288 if (!writelen)
1289 break;
1290
1291 buf += bytes;
1292 realpage++;
1293
1294 page = realpage & chip->pagemask;
1295 }
1296
1297 ops->retlen = ops->len - writelen;
1298 if (unlikely(oob))
1299 ops->oobretlen = ops->ooblen;
1300 return ret;
1301 }
1302
1303 /**
1304 * brcmnand_write - [MTD Interface] NAND write with ECC
1305 * @mtd: MTD device structure
1306 * @to: offset to write to
1307 * @len: number of bytes to write
1308 * @retlen: pointer to variable to store the number of written bytes
1309 * @buf: the data to write
1310 *
1311 * NAND write with ECC
1312 */
1313 static int brcmnand_write(struct mtd_info *mtd, loff_t to, size_t len,
1314 size_t *retlen, const uint8_t *buf)
1315 {
1316 struct nand_chip *chip = mtd->priv;
1317 int ret;
1318
1319 /* Do not allow reads past end of device */
1320 if ((to + len) > mtd->size)
1321 return -EINVAL;
1322 if (!len)
1323 return 0;
1324
1325 brcmnand_get_device(chip, mtd, FL_WRITING);
1326
1327 chip->ops.len = len;
1328 chip->ops.datbuf = (uint8_t *)buf;
1329 chip->ops.oobbuf = NULL;
1330
1331 ret = brcmnand_do_write_ops(mtd, to, &chip->ops);
1332
1333 *retlen = chip->ops.retlen;
1334
1335 brcmnand_release_device(mtd);
1336
1337 return ret;
1338 }
1339
1340 /**
1341 * brcmnand_write_oob_hwecc - [INTERNAL] write one page
1342 * @mtd: MTD device structure
1343 * @chip: NAND chip descriptor. The oob_poi ptr points to the OOB buffer.
1344 * @page: page number to write
1345 */
1346 static int brcmnand_write_oob_hwecc(struct mtd_info *mtd, struct nand_chip *chip, int page)
1347 {
1348 int eccsteps;
1349 int oob_written = 0, data_written = 0;
1350 uint32_t offset = page << chip->page_shift;
1351 uint8_t *oob = chip->oob_poi;
1352 int ret = 0;
1353
1354 for (eccsteps = 0; eccsteps < chip->ecc.steps; eccsteps++) {
1355 ret = brcmnand_posted_write_oob(mtd, chip, oob + oob_written,
1356 offset + data_written);
1357 if (ret < 0)
1358 break;
1359 data_written += chip->ecc.size;
1360 oob_written += chip->ecc.oobsize;
1361 }
1362 return (ret);
1363 }
1364
1365 /**
1366 * brcmnand_do_write_oob - [MTD Interface] NAND write out-of-band
1367 * @mtd: MTD device structure
1368 * @to: offset to write to
1369 * @ops: oob operation description structure
1370 *
1371 * NAND write out-of-band
1372 */
1373 static int brcmnand_do_write_oob(struct mtd_info *mtd, loff_t to,
1374 struct mtd_oob_ops *ops)
1375 {
1376 int page, status, len;
1377 struct nand_chip *chip = mtd->priv;
1378
1379 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1380 (unsigned int)to, (int)ops->ooblen);
1381
1382 if (ops->mode == MTD_OOB_AUTO)
1383 len = chip->ecc.layout->oobavail;
1384 else
1385 len = mtd->oobsize;
1386
1387 /* Do not allow write past end of page */
1388 if ((ops->ooboffs + ops->ooblen) > len) {
1389 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1390 "Attempt to write past end of page\n");
1391 return -EINVAL;
1392 }
1393
1394 if (unlikely(ops->ooboffs >= len)) {
1395 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1396 "Attempt to start write outside oob\n");
1397 return -EINVAL;
1398 }
1399
1400 /* Do not allow reads past end of device */
1401 if (unlikely(to >= mtd->size ||
1402 ops->ooboffs + ops->ooblen >
1403 ((mtd->size >> chip->page_shift) -
1404 (to >> chip->page_shift)) * len)) {
1405 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1406 "Attempt write beyond end of device\n");
1407 return -EINVAL;
1408 }
1409
1410
1411 /* Shift to get page */
1412 page = (int)(to >> chip->page_shift);
1413
1414 /* Invalidate the page cache, if we write to the cached page */
1415 if (page == chip->pagebuf)
1416 chip->pagebuf = -1;
1417
1418 memset(chip->oob_poi, 0xff, mtd->oobsize);
1419 brcmnand_fill_oob(chip, ops->oobbuf, ops);
1420 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1421 memset(chip->oob_poi, 0xff, mtd->oobsize);
1422
1423 if (status)
1424 return status;
1425
1426 ops->oobretlen = ops->ooblen;
1427
1428 return 0;
1429 }
1430
1431 /**
1432 * brcmnand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1433 * @mtd: MTD device structure
1434 * @to: offset to write to
1435 * @ops: oob operation description structure
1436 */
1437 static int brcmnand_write_oob(struct mtd_info *mtd, loff_t to,
1438 struct mtd_oob_ops *ops)
1439 {
1440 struct nand_chip *chip = mtd->priv;
1441 int ret = -ENOTSUPP;
1442
1443 ops->retlen = 0;
1444
1445 /* Do not allow writes past end of device */
1446 if (ops->datbuf && (to + ops->len) > mtd->size) {
1447 DEBUG(MTD_DEBUG_LEVEL0, "brcmnand_write_oob: "
1448 "Attempt write beyond end of device\n");
1449 return -EINVAL;
1450 }
1451
1452 brcmnand_get_device(chip, mtd, FL_WRITING);
1453
1454 switch (ops->mode) {
1455 case MTD_OOB_PLACE:
1456 case MTD_OOB_AUTO:
1457 case MTD_OOB_RAW:
1458 break;
1459
1460 default:
1461 goto out;
1462 }
1463
1464 if (!ops->datbuf)
1465 ret = brcmnand_do_write_oob(mtd, to, ops);
1466 else
1467 ret = brcmnand_do_write_ops(mtd, to, ops);
1468
1469 out:
1470 brcmnand_release_device(mtd);
1471 return ret;
1472 }
1473
1474 static int brcmnand_erase_bbt(struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
1475 {
1476 struct nand_chip * chip = mtd->priv;
1477 int page, len, pages_per_block, block_size;
1478 loff_t addr;
1479 int ret = 0;
1480 int need_bbt = 0;
1481 si_t *sih = brcmnand_info.sih;
1482 chipcregs_t *cc = brcmnand_info.cc;
1483 osl_t *osh;
1484
1485 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1486 (unsigned int)instr->addr, (unsigned int)instr->len);
1487
1488 block_size = 1 << chip->phys_erase_shift;
1489
1490 /* Start address must align on block boundary */
1491 if (instr->addr & (block_size - 1)) {
1492 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1493 return -EINVAL;
1494 }
1495
1496 /* Length must align on block boundary */
1497 if (instr->len & (block_size - 1)) {
1498 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1499 "Length not block aligned\n");
1500 return -EINVAL;
1501 }
1502
1503 /* Do not allow erase past end of device */
1504 if ((instr->len + instr->addr) > mtd->size) {
1505 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1506 "Erase past end of device\n");
1507 return -EINVAL;
1508 }
1509
1510 instr->fail_addr = 0xffffffff;
1511
1512 /* Grab the lock and see if the device is available */
1513 brcmnand_get_device(chip, mtd, FL_ERASING);
1514
1515 /* Shift to get first page */
1516 page = (int)(instr->addr >> chip->page_shift);
1517
1518 /* Calculate pages in each block */
1519 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1520
1521 osh = si_osh(sih);
1522 /* Clear ECC registers */
1523 W_REG(osh, &cc->nand_ecc_corr_addr, 0);
1524 W_REG(osh, &cc->nand_ecc_corr_addr_x, 0);
1525 W_REG(osh, &cc->nand_ecc_unc_addr, 0);
1526 W_REG(osh, &cc->nand_ecc_unc_addr_x, 0);
1527
1528 /* Loop throught the pages */
1529 len = instr->len;
1530 addr = instr->addr;
1531 instr->state = MTD_ERASING;
1532
1533 while (len) {
1534 /*
1535 * heck if we have a bad block, we do not erase bad blocks !
1536 */
1537 if (brcmnand_block_checkbad(mtd, ((loff_t) page) <<
1538 chip->page_shift, 0, allowbbt)) {
1539 printk(KERN_WARNING "nand_erase: attempt to erase a "
1540 "bad block at page 0x%08x\n", page);
1541 instr->state = MTD_ERASE_FAILED;
1542 goto erase_exit;
1543 }
1544
1545 /*
1546 * Invalidate the page cache, if we erase the block which
1547 * contains the current cached page
1548 */
1549 if (page <= chip->pagebuf && chip->pagebuf <
1550 (page + pages_per_block))
1551 chip->pagebuf = -1;
1552
1553 W_REG(osh, &cc->nand_cmd_addr, (page << chip->page_shift));
1554 brcmnand_cmd(osh, cc, NCMD_BLOCK_ERASE);
1555
1556 /* Wait until flash is ready */
1557 ret = brcmnand_ctrl_write_is_complete(mtd, chip, &need_bbt);
1558
1559 if (need_bbt) {
1560 if (!allowbbt) {
1561 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1562 "Failed erase, page 0x%08x\n", page);
1563 instr->state = MTD_ERASE_FAILED;
1564 instr->fail_addr = (page << chip->page_shift);
1565 chip->block_markbad(mtd, addr);
1566 goto erase_exit;
1567 }
1568 }
1569
1570 /* Increment page address and decrement length */
1571 len -= (1 << chip->phys_erase_shift);
1572 page += pages_per_block;
1573 }
1574 instr->state = MTD_ERASE_DONE;
1575
1576 erase_exit:
1577
1578 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1579 /* Do call back function */
1580 if (!ret)
1581 mtd_erase_callback(instr);
1582
1583 /* Deselect and wake up anyone waiting on the device */
1584 brcmnand_release_device(mtd);
1585
1586 return ret;
1587 }
1588
1589 static int
1590 brcmnand_erase(struct mtd_info *mtd, struct erase_info *instr)
1591 {
1592 int allowbbt = 0;
1593 int ret = 0;
1594
1595 /* do not allow erase of bbt */
1596 ret = brcmnand_erase_bbt(mtd, instr, allowbbt);
1597
1598 return ret;
1599 }
1600
1601 /**
1602 * brcmnand_sync - [MTD Interface] sync
1603 * @mtd: MTD device structure
1604 *
1605 * Sync is actually a wait for chip ready function
1606 */
1607 static void brcmnand_sync(struct mtd_info *mtd)
1608 {
1609 struct nand_chip *chip = mtd->priv;
1610
1611 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1612
1613 /* Grab the lock and see if the device is available */
1614 brcmnand_get_device(chip, mtd, FL_SYNCING);
1615 PLATFORM_IOFLUSH_WAR();
1616
1617 /* Release it and go back */
1618 brcmnand_release_device(mtd);
1619 }
1620
1621 /**
1622 * brcmnand_block_isbad - [MTD Interface] Check if block at offset is bad
1623 * @mtd: MTD device structure
1624 * @offs: offset relative to mtd start
1625 */
1626 static int brcmnand_block_isbad(struct mtd_info *mtd, loff_t offs)
1627 {
1628 /* Check for invalid offset */
1629 if (offs > mtd->size)
1630 return -EINVAL;
1631
1632 return brcmnand_block_checkbad(mtd, offs, 1, 0);
1633 }
1634
1635 /**
1636 * brcmnand_default_block_markbad - [DEFAULT] mark a block bad
1637 * @mtd: MTD device structure
1638 * @ofs: offset from device start
1639 *
1640 * This is the default implementation, which can be overridden by
1641 * a hardware specific driver.
1642 */
1643 static int brcmnand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
1644 {
1645 struct nand_chip *chip = mtd->priv;
1646 uint8_t bbmarker[1] = {0};
1647 uint8_t *buf = chip->oob_poi;
1648 int block, ret;
1649 int page, dir;
1650
1651 /* Get block number */
1652 block = (int)(ofs >> chip->bbt_erase_shift);
1653 /* Get page number */
1654 page = block << (chip->bbt_erase_shift - chip->page_shift);
1655 dir = 1;
1656
1657 if (chip->bbt)
1658 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1659 memcpy(buf, ffchars, NAND_MAX_OOBSIZE);
1660 memcpy(buf + chip->badblockpos, bbmarker, sizeof(bbmarker));
1661 ret = chip->ecc.write_oob(mtd, chip, page);
1662 page += dir;
1663 ret = chip->ecc.write_oob(mtd, chip, page);
1664
1665 /* According to the HW guy, even if the write fails, the controller have
1666 * written a 0 pattern that certainly would have written a non 0xFF value
1667 * into the BI marker.
1668 *
1669 * Ignoring ret. Even if we fail to write the BI bytes, just ignore it,
1670 * and mark the block as bad in the BBT
1671 */
1672 ret = brcmnand_update_bbt(mtd, ofs);
1673 mtd->ecc_stats.badblocks++;
1674 return ret;
1675 }
1676
1677 /**
1678 * brcmnand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1679 * @mtd: MTD device structure
1680 * @ofs: offset relative to mtd start
1681 */
1682 static int brcmnand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1683 {
1684 struct nand_chip *chip = mtd->priv;
1685 int ret;
1686
1687 if ((ret = brcmnand_block_isbad(mtd, ofs))) {
1688 /* If it was bad already, return success and do nothing. */
1689 if (ret > 0)
1690 return 0;
1691 return ret;
1692 }
1693
1694 return chip->block_markbad(mtd, ofs);
1695 }
1696
1697 /**
1698 * brcmnand_suspend - [MTD Interface] Suspend the NAND flash
1699 * @mtd: MTD device structure
1700 */
1701 static int brcmnand_suspend(struct mtd_info *mtd)
1702 {
1703 struct nand_chip *chip = mtd->priv;
1704
1705 return brcmnand_get_device(chip, mtd, FL_PM_SUSPENDED);
1706 }
1707
1708 /**
1709 * brcmnand_resume - [MTD Interface] Resume the NAND flash
1710 * @mtd: MTD device structure
1711 */
1712 static void brcmnand_resume(struct mtd_info *mtd)
1713 {
1714 struct nand_chip *chip = mtd->priv;
1715
1716 if (chip->state == FL_PM_SUSPENDED)
1717 brcmnand_release_device(mtd);
1718 else
1719 printk(KERN_ERR "brcmnand_resume() called for a chip which is not "
1720 "in suspended state\n");
1721 }
1722
1723 struct mtd_partition brcmnand_parts[] = {
1724 {
1725 .name = "brcmnand",
1726 .size = 0,
1727 .offset = 0
1728 },
1729 {
1730 .name = 0,
1731 .size = 0,
1732 .offset = 0
1733 }
1734 };
1735
1736 struct mtd_partition *init_brcmnand_mtd_partitions(struct mtd_info *mtd, size_t size)
1737 {
1738 brcmnand_parts[0].offset = NFL_BOOT_OS_SIZE;
1739 brcmnand_parts[0].size = size - NFL_BOOT_OS_SIZE - NFL_BBT_SIZE;
1740
1741 return brcmnand_parts;
1742 }
1743
1744 /**
1745 * brcmnand_check_command_done - [DEFAULT] check if command is done
1746 * @mtd: MTD device structure
1747 *
1748 * Return 0 to process next command
1749 */
1750 static int
1751 brcmnand_check_command_done(void)
1752 {
1753 si_t *sih = brcmnand_info.sih;
1754 chipcregs_t *cc = brcmnand_info.cc;
1755 osl_t *osh;
1756 int count = 0;
1757
1758 osh = si_osh(sih);
1759
1760 while (R_REG(osh, &cc->nflashctrl) & NFC_START) {
1761 if (++count > BRCMNAND_POLL_TIMEOUT) {
1762 printk("brcmnand_check_command_done: command timeout\n");
1763 return -1;
1764 }
1765 }
1766
1767 return 0;
1768 }
1769
1770 /**
1771 * brcmnand_hwcontrol - [DEFAULT] Issue command and address cycles to the chip
1772 * @mtd: MTD device structure
1773 * @cmd: the command to be sent
1774 * @ctrl: the control code to be sent
1775 *
1776 * Issue command and address cycles to the chip
1777 */
1778 static void
1779 brcmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
1780 {
1781 si_t *sih = brcmnand_info.sih;
1782 chipcregs_t *cc = brcmnand_info.cc;
1783 osl_t *osh;
1784 unsigned int val = 0;
1785
1786 osh = si_osh(sih);
1787
1788 if (cmd == NAND_CMD_NONE)
1789 return;
1790
1791 if (ctrl & NAND_CLE) {
1792 val = cmd | NFC_CMD0;
1793 }
1794 else {
1795 switch (ctrl & (NAND_ALE_COL | NAND_ALE_ROW)) {
1796 case NAND_ALE_COL:
1797 W_REG(osh, &cc->nflashcoladdr, cmd);
1798 val = NFC_COL;
1799 break;
1800 case NAND_ALE_ROW:
1801 W_REG(osh, &cc->nflashrowaddr, cmd);
1802 val = NFC_ROW;
1803 break;
1804 default:
1805 BUG();
1806 }
1807 }
1808
1809 /* nCS is not needed for reset command */
1810 if (cmd != NAND_CMD_RESET)
1811 val |= NFC_CSA;
1812
1813 val |= NFC_START;
1814 W_REG(osh, &cc->nflashctrl, val);
1815
1816 brcmnand_check_command_done();
1817 }
1818
1819 /**
1820 * brcmnand_command_lp - [DEFAULT] Send command to NAND large page device
1821 * @mtd: MTD device structure
1822 * @command: the command to be sent
1823 * @column: the column address for this command, -1 if none
1824 * @page_addr: the page address for this command, -1 if none
1825 *
1826 * Send command to NAND device. This is the version for the new large page
1827 * devices We dont have the separate regions as we have in the small page
1828 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1829 */
1830 static void
1831 brcmnand_command_lp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
1832 {
1833 register struct nand_chip *chip = mtd->priv;
1834
1835 /* Emulate NAND_CMD_READOOB */
1836 if (command == NAND_CMD_READOOB) {
1837 column += mtd->writesize;
1838 command = NAND_CMD_READ0;
1839 }
1840
1841 /* Command latch cycle */
1842 chip->cmd_ctrl(mtd, command & 0xff, NAND_NCE | NAND_CLE);
1843
1844 if (column != -1 || page_addr != -1) {
1845 int ctrl = NAND_NCE | NAND_ALE;
1846
1847 /* Serially input address */
1848 if (column != -1) {
1849 ctrl |= NAND_ALE_COL;
1850
1851 /* Adjust columns for 16 bit buswidth */
1852 if (chip->options & NAND_BUSWIDTH_16)
1853 column >>= 1;
1854
1855 chip->cmd_ctrl(mtd, column, ctrl);
1856 }
1857
1858 if (page_addr != -1) {
1859 ctrl &= ~NAND_ALE_COL;
1860 ctrl |= NAND_ALE_ROW;
1861
1862 chip->cmd_ctrl(mtd, page_addr, ctrl);
1863 }
1864 }
1865
1866 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
1867
1868 /*
1869 * program and erase have their own busy handlers
1870 * status, sequential in, and deplete1 need no delay
1871 */
1872 switch (command) {
1873
1874 case NAND_CMD_CACHEDPROG:
1875 case NAND_CMD_PAGEPROG:
1876 case NAND_CMD_ERASE1:
1877 case NAND_CMD_ERASE2:
1878 case NAND_CMD_SEQIN:
1879 case NAND_CMD_RNDIN:
1880 case NAND_CMD_STATUS:
1881 case NAND_CMD_DEPLETE1:
1882 return;
1883
1884 /*
1885 * read error status commands require only a short delay
1886 */
1887 case NAND_CMD_STATUS_ERROR:
1888 case NAND_CMD_STATUS_ERROR0:
1889 case NAND_CMD_STATUS_ERROR1:
1890 case NAND_CMD_STATUS_ERROR2:
1891 case NAND_CMD_STATUS_ERROR3:
1892 udelay(chip->chip_delay);
1893 return;
1894
1895 case NAND_CMD_RESET:
1896 if (chip->dev_ready)
1897 break;
1898
1899 udelay(chip->chip_delay);
1900
1901 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE);
1902 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
1903
1904 while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
1905 return;
1906
1907 case NAND_CMD_RNDOUT:
1908 /* No ready / busy check necessary */
1909 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_NCE | NAND_CLE);
1910 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
1911 return;
1912
1913 case NAND_CMD_READ0:
1914 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE);
1915 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
1916
1917 /* This applies to read commands */
1918 default:
1919 /*
1920 * If we don't have access to the busy pin, we apply the given
1921 * command delay
1922 */
1923 if (!chip->dev_ready) {
1924 udelay(chip->chip_delay);
1925 return;
1926 }
1927 }
1928
1929 /* Apply this short delay always to ensure that we do wait tWB in
1930 * any case on any machine.
1931 */
1932 ndelay(100);
1933
1934 nand_wait_ready(mtd);
1935 }
1936
1937 /**
1938 * brcmnand_command - [DEFAULT] Send command to NAND device
1939 * @mtd: MTD device structure
1940 * @command: the command to be sent
1941 * @column: the column address for this command, -1 if none
1942 * @page_addr: the page address for this command, -1 if none
1943 *
1944 * Send command to NAND device. This function is used for small page
1945 * devices (256/512 Bytes per page)
1946 */
1947 static void
1948 brcmnand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
1949 {
1950 register struct nand_chip *chip = mtd->priv;
1951 int ctrl = NAND_CTRL_CLE;
1952
1953 /* Invoke large page command function */
1954 if (mtd->writesize > 512) {
1955 brcmnand_command_lp(mtd, command, column, page_addr);
1956 return;
1957 }
1958
1959 /*
1960 * Write out the command to the device.
1961 */
1962 if (command == NAND_CMD_SEQIN) {
1963 int readcmd;
1964
1965 if (column >= mtd->writesize) {
1966 /* OOB area */
1967 column -= mtd->writesize;
1968 readcmd = NAND_CMD_READOOB;
1969 } else if (column < 256) {
1970 /* First 256 bytes --> READ0 */
1971 readcmd = NAND_CMD_READ0;
1972 } else {
1973 column -= 256;
1974 readcmd = NAND_CMD_READ1;
1975 }
1976
1977 chip->cmd_ctrl(mtd, readcmd, ctrl);
1978 }
1979
1980 chip->cmd_ctrl(mtd, command, ctrl);
1981
1982 /*
1983 * Address cycle, when necessary
1984 */
1985 ctrl = NAND_CTRL_ALE;
1986
1987 /* Serially input address */
1988 if (column != -1) {
1989 ctrl |= NAND_ALE_COL;
1990
1991 /* Adjust columns for 16 bit buswidth */
1992 if (chip->options & NAND_BUSWIDTH_16)
1993 column >>= 1;
1994
1995 chip->cmd_ctrl(mtd, column, ctrl);
1996 }
1997
1998 if (page_addr != -1) {
1999 ctrl &= ~NAND_ALE_COL;
2000 ctrl |= NAND_ALE_ROW;
2001
2002 chip->cmd_ctrl(mtd, page_addr, ctrl);
2003 }
2004
2005 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
2006
2007 /*
2008 * program and erase have their own busy handlers
2009 * status and sequential in needs no delay
2010 */
2011 switch (command) {
2012
2013 case NAND_CMD_PAGEPROG:
2014 case NAND_CMD_ERASE1:
2015 case NAND_CMD_ERASE2:
2016 case NAND_CMD_SEQIN:
2017 case NAND_CMD_STATUS:
2018 return;
2019
2020 case NAND_CMD_RESET:
2021 if (chip->dev_ready)
2022 break;
2023
2024 udelay(chip->chip_delay);
2025
2026 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_CTRL_CLE);
2027
2028 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
2029
2030 while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
2031
2032 return;
2033
2034 /* This applies to read commands */
2035 default:
2036 /*
2037 * If we don't have access to the busy pin, we apply the given
2038 * command delay
2039 */
2040 if (!chip->dev_ready) {
2041 udelay(chip->chip_delay);
2042 return;
2043 }
2044 }
2045
2046 /* Apply this short delay always to ensure that we do wait tWB in
2047 * any case on any machine.
2048 */
2049 ndelay(100);
2050
2051 nand_wait_ready(mtd);
2052 }
2053
2054 /**
2055 * brcmnand_read_byte - [DEFAULT] read one byte from the chip
2056 * @mtd: MTD device structure
2057 *
2058 * Default read function for 8bit bus width
2059 */
2060 static uint8_t
2061 brcmnand_read_byte(struct mtd_info *mtd)
2062 {
2063 si_t *sih = brcmnand_info.sih;
2064 chipcregs_t *cc = brcmnand_info.cc;
2065 osl_t *osh;
2066 register struct nand_chip *chip = mtd->priv;
2067 unsigned int val;
2068
2069 osh = si_osh(sih);
2070
2071 val = NFC_DREAD | NFC_CSA | NFC_START;
2072 W_REG(osh, &cc->nflashctrl, val);
2073
2074 brcmnand_check_command_done();
2075
2076 return readb(chip->IO_ADDR_R);
2077 }
2078
2079 /**
2080 * brcmnand_write_byte - [DEFAULT] write one byte from the chip
2081 * @mtd: MTD device structure
2082 *
2083 * Default write function for 8bit bus width
2084 */
2085 static int
2086 brcmnand_write_byte(struct mtd_info *mtd, u_char ch)
2087 {
2088 si_t *sih = brcmnand_info.sih;
2089 chipcregs_t *cc = brcmnand_info.cc;
2090 osl_t *osh;
2091 unsigned int val;
2092
2093 osh = si_osh(sih);
2094
2095 W_REG(osh, &cc->nflashdata, (unsigned int)ch);
2096
2097 val = NFC_DWRITE | NFC_CSA | NFC_START;
2098 W_REG(osh, &cc->nflashctrl, val);
2099
2100 brcmnand_check_command_done();
2101
2102 return 0;
2103 }
2104
2105 /**
2106 * brcmnand_read_buf - [DEFAULT] read data from chip into buf
2107 * @mtd: MTD device structure
2108 * @buf: data buffer
2109 * @len: number of bytes to read
2110 *
2111 * Default read function for 8bit bus width
2112 */
2113 static void
2114 brcmnand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2115 {
2116 int count = 0;
2117
2118 while (len > 0) {
2119 buf[count++] = brcmnand_read_byte(mtd);
2120 len--;
2121 }
2122 }
2123
2124 /**
2125 * brcmnand_write_buf - [DEFAULT] write buffer to chip
2126 * @mtd: MTD device structure
2127 * @buf: data buffer
2128 * @len: number of bytes to write
2129 *
2130 * Default write function for 8bit bus width
2131 */
2132 static void
2133 brcmnand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2134 {
2135 int count = 0;
2136
2137 while (len > 0) {
2138 brcmnand_write_byte(mtd, buf[count++]);
2139 len--;
2140 }
2141 }
2142
2143 /**
2144 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
2145 * @mtd: MTD device structure
2146 * @buf: buffer containing the data to compare
2147 * @len: number of bytes to compare
2148 *
2149 * Default verify function for 8bit buswith
2150 */
2151 static int
2152 brcmnand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
2153 {
2154 int i;
2155 struct nand_chip *chip = mtd->priv;
2156 uint8_t chbuf;
2157
2158 for (i = 0; i < len; i++) {
2159 chbuf = chip->read_byte(mtd);
2160 if (buf[i] != chbuf) {
2161 return -EFAULT;
2162 }
2163 }
2164
2165 return 0;
2166 }
2167
2168 /**
2169 * brcmnand_devready - [DEFAULT] Check if nand flash device is ready
2170 * @mtd: MTD device structure
2171 *
2172 * Return 0 if nand flash device is busy
2173 */
2174 static int
2175 brcmnand_devready(struct mtd_info *mtd)
2176 {
2177 si_t *sih = brcmnand_info.sih;
2178 chipcregs_t *cc = brcmnand_info.cc;
2179 osl_t *osh;
2180 int status;
2181
2182 osh = si_osh(sih);
2183
2184 status = (R_REG(osh, &cc->nflashctrl) & NFC_RDYBUSY) ? 1 : 0;
2185
2186 return status;
2187 }
2188
2189 /**
2190 * brcmnand_select_chip - [DEFAULT] select chip
2191 * @mtd: MTD device structure
2192 * @chip: chip to be selected
2193 *
2194 * For BCM4706 just return because of only one chip is used
2195 */
2196 static void
2197 brcmnand_select_chip(struct mtd_info *mtd, int chip)
2198 {
2199 return;
2200 }
2201
2202 /**
2203 * brcmnand_init_nandchip - [DEFAULT] init mtd_info and nand_chip
2204 * @mtd: MTD device structure
2205 * @chip: chip to be selected
2206 *
2207 */
2208 static int
2209 brcmnand_init_nandchip(struct mtd_info *mtd, struct nand_chip *chip)
2210 {
2211 chipcregs_t *cc = brcmnand_info.cc;
2212 int ret = 0;
2213
2214 chip->cmdfunc = brcmnand_command;
2215 chip->read_byte = brcmnand_read_byte;
2216 chip->write_buf = brcmnand_write_buf;
2217 chip->read_buf = brcmnand_read_buf;
2218 chip->verify_buf = brcmnand_verify_buf;
2219 chip->select_chip = brcmnand_select_chip;
2220 chip->cmd_ctrl = brcmnand_hwcontrol;
2221 chip->dev_ready = brcmnand_devready;
2222 chip->get_device = brcmnand_get_device_bcm4706;
2223 chip->release_device = brcmnand_release_device_bcm4706;
2224
2225 chip->numchips = 1;
2226 chip->chip_shift = 0;
2227 chip->chip_delay = 50;
2228 chip->priv = mtd;
2229 chip->options = NAND_USE_FLASH_BBT;
2230
2231 chip->controller = &chip->hwcontrol;
2232 spin_lock_init(&chip->controller->lock);
2233 init_waitqueue_head(&chip->controller->wq);
2234
2235 chip->IO_ADDR_W = (void __iomem *)&cc->nflashdata;
2236 chip->IO_ADDR_R = chip->IO_ADDR_W;
2237
2238 /* BCM4706 only support software ECC mode */
2239 chip->ecc.mode = NAND_ECC_SOFT;
2240 chip->ecc.layout = NULL;
2241
2242 mtd->name = "brcmnand";
2243 mtd->priv = chip;
2244 mtd->owner = THIS_MODULE;
2245
2246 mtd->mutex = partitions_mutex_init();
2247 if (!mtd->mutex)
2248 ret = -ENOMEM;
2249
2250 return ret;
2251 }
2252
2253 static int __init
2254 brcmnand_mtd_init(void)
2255 {
2256 int ret = 0;
2257 struct nflash *info;
2258 struct pci_dev *dev = NULL;
2259 struct nand_chip *chip;
2260 struct mtd_info *mtd;
2261 #ifdef CONFIG_MTD_PARTITIONS
2262 struct mtd_partition *parts;
2263 int i;
2264 #endif
2265
2266 list_for_each_entry(dev, &((pci_find_bus(0, 0))->devices), bus_list) {
2267 if ((dev != NULL) && (dev->device == CC_CORE_ID))
2268 break;
2269 }
2270
2271 if (dev == NULL) {
2272 printk(KERN_ERR "brcmnand: chipcommon not found\n");
2273 return -ENODEV;
2274 }
2275
2276 memset(&brcmnand_info, 0, sizeof(struct brcmnand_mtd));
2277
2278 /* attach to the backplane */
2279 if (!(brcmnand_info.sih = si_kattach(SI_OSH))) {
2280 printk(KERN_ERR "brcmnand: error attaching to backplane\n");
2281 ret = -EIO;
2282 goto fail;
2283 }
2284
2285 /* Map registers and flash base */
2286 if (!(brcmnand_info.cc = ioremap_nocache(
2287 pci_resource_start(dev, 0),
2288 pci_resource_len(dev, 0)))) {
2289 printk(KERN_ERR "brcmnand: error mapping registers\n");
2290 ret = -EIO;
2291 goto fail;
2292 }
2293
2294 /* Initialize serial flash access */
2295 if (!(info = nflash_init(brcmnand_info.sih, brcmnand_info.cc))) {
2296 printk(KERN_ERR "brcmnand: found no supported devices\n");
2297 ret = -ENODEV;
2298 goto fail;
2299 }
2300
2301 if (CHIPID(brcmnand_info.sih->chip) == BCM4706_CHIP_ID) {
2302 mtd = &brcmnand_info.mtd;
2303 chip = &brcmnand_info.chip;
2304
2305 if ((ret = brcmnand_init_nandchip(mtd, chip)) != 0) {
2306 printk(KERN_ERR "brcmnand_mtd_init: brcmnand_init_nandchip failed\n");
2307 goto fail;
2308 }
2309
2310 if ((ret = nand_scan(mtd, chip->numchips)) != 0) {
2311 printk(KERN_ERR "brcmnand_mtd_init: nand_scan failed\n");
2312 goto fail;
2313 }
2314
2315 goto init_partitions;
2316 }
2317
2318 page_buffer = kmalloc(sizeof(struct nand_buffers), GFP_KERNEL);
2319 if (!page_buffer) {
2320 printk(KERN_ERR "brcmnand: cannot allocate memory for page buffer\n");
2321 return -ENOMEM;
2322 }
2323 memset(page_buffer, 0, sizeof(struct nand_buffers));
2324
2325 chip = &brcmnand_info.chip;
2326 mtd = &brcmnand_info.mtd;
2327
2328 chip->ecc.mode = NAND_ECC_HW;
2329
2330 chip->buffers = (struct nand_buffers *)page_buffer;
2331 chip->numchips = 1;
2332 chip->chip_shift = 0;
2333 chip->priv = mtd;
2334 chip->options |= NAND_USE_FLASH_BBT;
2335 /* At most 2GB is supported */
2336 chip->chipsize = (info->size >= (1 << 11)) ? (1 << 31) : (info->size << 20);
2337 chip->ecc.level = info->ecclevel;
2338
2339 /* Register with MTD */
2340 mtd->name = "brcmnand";
2341 mtd->priv = &brcmnand_info.chip;
2342 mtd->owner = THIS_MODULE;
2343 mtd->mutex = partitions_mutex_init();
2344 if (!mtd->mutex) {
2345 ret = -ENOMEM;
2346 goto fail;
2347 }
2348
2349 mtd->size = chip->chipsize;
2350 mtd->erasesize = info->blocksize;
2351 mtd->writesize = info->pagesize;
2352 /* 16B oob for 512B page, 64B for 2KB page, etc.. */
2353 mtd->oobsize = (info->pagesize >> 5);
2354
2355 /* Calculate the address shift from the page size */
2356 chip->page_shift = ffs(mtd->writesize) - 1;
2357 /* Convert chipsize to number of pages per chip -1. */
2358 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2359
2360 chip->bbt_erase_shift = chip->phys_erase_shift =
2361 ffs(mtd->erasesize) - 1;
2362 chip->chip_shift = ffs(chip->chipsize) - 1;
2363
2364 /* Set the bad block position */
2365 chip->badblockpos = (mtd->writesize > 512) ?
2366 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2367
2368 if (!chip->controller) {
2369 chip->controller = &chip->hwcontrol;
2370 spin_lock_init(&chip->controller->lock);
2371 init_waitqueue_head(&chip->controller->wq);
2372 }
2373
2374 /* Preset the internal oob write buffer */
2375 memset(BRCMNAND_OOBBUF(chip->buffers), 0xff, mtd->oobsize);
2376
2377 /* Set the internal oob buffer location, just after the page data */
2378 chip->oob_poi = BRCMNAND_OOBBUF(chip->buffers);
2379
2380 /*
2381 * If no default placement scheme is given, select an appropriate one
2382 */
2383 if (!chip->ecc.layout) {
2384 switch (mtd->oobsize) {
2385 case 16:
2386 if (chip->ecc.level == BRCMNAND_ECC_HAMMING)
2387 chip->ecc.layout = &brcmnand_oob_16;
2388 else
2389 chip->ecc.layout = &brcmnand_oob_bch4_512;
2390 break;
2391 case 64:
2392 if (chip->ecc.level == BRCMNAND_ECC_HAMMING)
2393 chip->ecc.layout = &brcmnand_oob_64;
2394 else if (chip->ecc.level == BRCMNAND_ECC_BCH_4) {
2395 if (mtd->writesize == 2048)
2396 chip->ecc.layout = &brcmnand_oob_bch4_2k;
2397 else {
2398 printk(KERN_ERR "Unsupported page size of %d\n",
2399 mtd->writesize);
2400 BUG();
2401 }
2402 }
2403 break;
2404 case 128:
2405 if (chip->ecc.level == BRCMNAND_ECC_HAMMING)
2406 chip->ecc.layout = &brcmnand_oob_128;
2407 else {
2408 printk(KERN_ERR "Unsupported page size of %d\n",
2409 mtd->writesize);
2410 BUG();
2411 }
2412 break;
2413 default:
2414 printk(KERN_WARNING "No oob scheme defined for "
2415 "oobsize %d\n", mtd->oobsize);
2416 BUG();
2417 }
2418 }
2419
2420 if (!chip->write_page)
2421 chip->write_page = brcmnand_write_page;
2422
2423 switch (chip->ecc.mode) {
2424 case NAND_ECC_HW:
2425 if (!chip->ecc.read_page)
2426 chip->ecc.read_page = brcmnand_read_page_hwecc;
2427 if (!chip->ecc.write_page)
2428 chip->ecc.write_page = brcmnand_write_page_hwecc;
2429 if (!chip->ecc.read_oob)
2430 chip->ecc.read_oob = brcmnand_read_oob_hwecc;
2431 if (!chip->ecc.write_oob)
2432 chip->ecc.write_oob = brcmnand_write_oob_hwecc;
2433 break;
2434 case NAND_ECC_SOFT:
2435 break;
2436 case NAND_ECC_NONE:
2437 break;
2438 default:
2439 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2440 chip->ecc.mode);
2441 BUG();
2442 break;
2443 }
2444
2445 /*
2446 * The number of bytes available for a client to place data into
2447 * the out of band area
2448 */
2449 chip->ecc.layout->oobavail = 0;
2450 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2451 chip->ecc.layout->oobavail +=
2452 chip->ecc.layout->oobfree[i].length;
2453 mtd->oobavail = chip->ecc.layout->oobavail;
2454
2455 /*
2456 * Set the number of read / write steps for one page
2457 */
2458 chip->ecc.size = NFL_SECTOR_SIZE; /* Fixed for Broadcom controller. */
2459 chip->ecc.oobsize = 16; /* Fixed for Hamming code or 4-bit BCH for now. */
2460 chip->ecc.bytes = brcmnand_eccbytes[chip->ecc.level];
2461 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2462 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2463 printk(KERN_WARNING "Invalid ecc parameters\n");
2464 BUG();
2465 }
2466 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2467
2468 /*
2469 * Allow subpage writes up to ecc.steps. Not possible for MLC
2470 * FLASH.
2471 */
2472 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2473 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2474 switch (chip->ecc.steps) {
2475 case 2:
2476 mtd->subpage_sft = 1;
2477 break;
2478 case 4:
2479 mtd->subpage_sft = 2;
2480 break;
2481 case 8:
2482 mtd->subpage_sft = 3;
2483 break;
2484 }
2485 }
2486 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2487
2488 /* Initialize state */
2489 chip->state = FL_READY;
2490
2491 /* Invalidate the pagebuffer reference */
2492 chip->pagebuf = -1;
2493
2494 if (!chip->block_markbad)
2495 chip->block_markbad = brcmnand_default_block_markbad;
2496 if (!chip->scan_bbt)
2497 chip->scan_bbt = brcmnand_default_bbt;
2498 if (!chip->erase_bbt)
2499 chip->erase_bbt = brcmnand_erase_bbt;
2500
2501 if (!chip->get_device)
2502 chip->get_device = brcmnand_get_device;
2503 if (!chip->release_device)
2504 chip->release_device = brcmnand_release_device;
2505
2506 mtd->type = MTD_NANDFLASH;
2507 mtd->flags = MTD_CAP_NANDFLASH;
2508 mtd->erase = brcmnand_erase;
2509 mtd->point = NULL;
2510 mtd->unpoint = NULL;
2511 mtd->read = brcmnand_read;
2512 mtd->write = brcmnand_write;
2513 mtd->read_oob = brcmnand_read_oob;
2514 mtd->write_oob = brcmnand_write_oob;
2515 mtd->sync = brcmnand_sync;
2516 mtd->lock = NULL;
2517 mtd->unlock = NULL;
2518 mtd->suspend = brcmnand_suspend;
2519 mtd->resume = brcmnand_resume;
2520 mtd->block_isbad = brcmnand_block_isbad;
2521 mtd->block_markbad = brcmnand_block_markbad;
2522
2523 /* propagate ecc.layout to mtd_info */
2524 mtd->ecclayout = chip->ecc.layout;
2525
2526 ret = chip->scan_bbt(mtd);
2527 if (ret) {
2528 printk(KERN_ERR "brcmnand: scan_bbt failed\n");
2529 goto fail;
2530 }
2531
2532 init_partitions:
2533 #ifdef CONFIG_MTD_PARTITIONS
2534 parts = init_brcmnand_mtd_partitions(mtd, mtd->size);
2535 if (!parts)
2536 goto fail;
2537 for (i = 0; parts[i].name; i++);
2538 ret = add_mtd_partitions(mtd, parts, i);
2539 if (ret) {
2540 printk(KERN_ERR "brcmnand: add_mtd failed\n");
2541 goto fail;
2542 }
2543 brcmnand_info.parts = parts;
2544 #endif
2545 return 0;
2546
2547 fail:
2548 if (brcmnand_info.cc)
2549 iounmap((void *) brcmnand_info.cc);
2550 if (brcmnand_info.sih)
2551 si_detach(brcmnand_info.sih);
2552 if (page_buffer)
2553 kfree(page_buffer);
2554 return ret;
2555 }
2556
2557 static void __exit
2558 brcmnand_mtd_exit(void)
2559 {
2560 #ifdef CONFIG_MTD_PARTITIONS
2561 del_mtd_partitions(&brcmnand_info.mtd);
2562 #else
2563 del_mtd_device(&brcmnand_info.mtd);
2564 #endif
2565 iounmap((void *) brcmnand_info.cc);
2566 si_detach(brcmnand_info.sih);
2567 }
2568
2569 module_init(brcmnand_mtd_init);
2570 module_exit(brcmnand_mtd_exit);
Tomato firmware and modifications.