release/src/router/utils/mii.h

   1 /*
   2  * mii.h 1.4 2000/04/25 22:06:15
   3  *
   4  * Media Independent Interface support: register layout and ioctl's
   5  *
   6  * Copyright (C) 2000 David A. Hinds -- dhinds@pcmcia.sourceforge.org
   7  */
   8
   9 #ifndef _LINUX_MII_H
  10 #define _LINUX_MII_H
  11
  12 /* network interface ioctl's for MII commands */
  13 #ifndef SIOCGMIIPHY
  14 #define SIOCGMIIPHY (SIOCDEVPRIVATE)    /* Read from current PHY */
  15 #define SIOCGMIIREG (SIOCDEVPRIVATE+1)  /* Read any PHY register */
  16 #define SIOCSMIIREG (SIOCDEVPRIVATE+2)  /* Write any PHY register */
  17 #define SIOCGPARAMS (SIOCDEVPRIVATE+3)  /* Read operational parameters */
  18 #define SIOCSPARAMS (SIOCDEVPRIVATE+4)  /* Set operational parameters */
  19 #endif
  20
  21 #include <linux/types.h>
  22
  23 /* This data structure is used for all the MII ioctl's */
  24 struct mii_data {
  25     __u16       phy_id;
  26     __u16       reg_num;
  27     __u16       val_in;
  28     __u16       val_out;
  29 };
  30
  31 /* Basic Mode Control Register */
  32 #define MII_BMCR                0x00
  33 #define  MII_BMCR_RESET         0x8000
  34 #define  MII_BMCR_LOOPBACK      0x4000
  35 #define  MII_BMCR_100MBIT       0x2000
  36 #define  MII_BMCR_AN_ENA        0x1000
  37 #define  MII_BMCR_POWERDONW     0x0800
  38 #define  MII_BMCR_ISOLATE       0x0400
  39 #define  MII_BMCR_RESTART       0x0200
  40 #define  MII_BMCR_DUPLEX        0x0100
  41 #define  MII_BMCR_COLTEST       0x0080
  42 #define  MII_BMCR_1000MBIT      0x0040
  43
  44 /* Basic Mode Status Register */
  45 #define MII_BMSR                0x01
  46 #define  MII_BMSR_CAP_MASK      0xf800
  47 #define  MII_BMSR_100BASET4     0x8000  /* Can do 100mbps, 4k packets  */
  48 #define  MII_BMSR_100BASETX_FD  0x4000  /* Can do 100mbps, full-duplex */
  49 #define  MII_BMSR_100BASETX_HD  0x2000  /* Can do 100mbps, half-duplex */
  50 #define  MII_BMSR_10BASET_FD    0x1000  /* Can do 10mbps, full-duplex  */
  51 #define  MII_BMSR_10BASET_HD    0x0800  /* Can do 10mbps, half-duplex  */
  52 #define  MII_BMSR_100FULL2      0x0400  /* Can do 100BASE-T2 FDX */
  53 #define  MII_BMSR_100HALF2      0x0200  /* Can do 100BASE-T2 HDX */
  54 #define  MII_BMSR_ESTATEN       0x0100  /* Extended Status in R15 */
  55 #define  MII_BMSR_NO_PREAMBLE   0x0040
  56 #define  MII_BMSR_AN_COMPLETE   0x0020  /* Auto-negotiation complete   */
  57 #define  MII_BMSR_REMOTE_FAULT  0x0010  /* Remote fault detected       */
  58 #define  MII_BMSR_AN_ABLE       0x0008  /* Able to do auto-negotiation */
  59 #define  MII_BMSR_LINK_VALID    0x0004  /* Link status                 */
  60 #define  MII_BMSR_JABBER        0x0002  /* Jabber detected             */
  61 #define  MII_BMSR_ERCAP         0x0001  /* Ext-reg capability          */
  62
  63 #define MII_PHY_ID1             0x02
  64 #define MII_PHY_ID2             0x03
  65
  66 /* Auto-Negotiation Advertisement Register */
  67 #define MII_ANAR                0x04
  68 /* Auto-Negotiation Link Partner Ability Register */
  69 #define MII_ANLPAR              0x05
  70 #define  MII_AN_NEXT_PAGE       0x8000
  71 #define  MII_AN_ACK             0x4000
  72 #define  MII_AN_REMOTE_FAULT    0x2000
  73 #define  MII_AN_ABILITY_MASK    (MII_AN_FLOW_CONTROL|MII_AN_100BASET4|MII_AN_100BASETX_FD|MII_AN_100BASETX_HD|MII_AN_10BASET_FD|MII_AN_10BASET_HD)
  74 #define  MII_AN_FLOW_CONTROL    0x0400
  75 #define  MII_AN_100BASET4       0x0200
  76 #define  MII_AN_100BASETX_FD    0x0100
  77 #define  MII_AN_100BASETX_HD    0x0080
  78 #define  MII_AN_10BASET_FD      0x0040
  79 #define  MII_AN_10BASET_HD      0x0020
  80 #define  MII_AN_PROT_MASK       0x001f
  81 #define  MII_AN_PROT_802_3      0x0001
  82
  83 /* Auto-Negotiation Expansion Register */
  84 #define MII_ANER                0x06
  85 #define  MII_ANER_MULT_FAULT    0x0010
  86 #define  MII_ANER_LP_NP_ABLE    0x0008
  87 #define  MII_ANER_NP_ABLE       0x0004
  88 #define  MII_ANER_PAGE_RX       0x0002
  89 #define  MII_ANER_LP_AN_ABLE    0x0001
  90
  91 /* Gigabit Registers */
  92 #define MII_CTRL1000            0x09
  93 #define   MII_AN2_UNKNOWN1      0x0800
  94 #define   MII_AN2_UNKNOWN2      0x0400
  95 #define   MII_AN2_1000FULL      0x0200
  96 #define   MII_AN2_1000HALF      0x0100
  97
  98 #define MII_STAT1000            0x0a
  99 #define   MII_LPA2_UNKNOWN1     0x4000
 100 #define   MII_LPA2_1000LOCALOK  0x2000
 101 #define   MII_LPA2_1000REMRXOK  0x1000
 102 #define   MII_LPA2_1000FULL     0x0800
 103 #define   MII_LPA2_1000HALF     0x0400
 104
 105 #define MII_ESTAT1000           0x0f
 106 #define   MII_EST_1000THALF     0x1000          /* 1000BASE-T half duplex capable */
 107 #define   MII_EST_1000TFULL     0x2000          /* 1000BASE-T full duplex capable */
 108 #define   MII_EST_1000XHALF     0x4000          /* 1000BASE-X half duplex capable */
 109 #define   MII_EST_1000XFULL     0x8000          /* 1000BASE-X full duplex capable */
 110
 111 /* Last register we need for show_basic_mii() */
 112 #define MII_BASIC_MAX           MII_STAT1000
 113
 114 #define MII_MAXPHYREG           32
 115 #define EPHY_NONE               31      /* nvram: no phy present at all */
 116 #define EPHY_NOREG              30      /* nvram: no local phy regs */
 117
 118 #endif /* _LINUX_MII_H */