release/src/router/utils/etc53xx.h

   1 /*
   2  * Broadcom Home Gateway Reference Design
   3  * BCM53xx Register definitions
   4  *
   5  * Copyright 2004, Broadcom Corporation
   6  * All Rights Reserved.
   7  *
   8  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   9  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  10  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  11  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  12  * $Id: etc53xx.h,v 1.1 2005/05/14 13:15:46 nbd Exp $
  13  */
  14
  15 #ifndef __BCM535M_H_
  16 #define __BCM535M_H_
  17
  18 /* ROBO embedded device type */
  19 #define ROBO_DEV_5380  1
  20 #define ROBO_DEV_5365  2
  21 #define ROBO_DEV_5350  3
  22 #define ROBO_DEV_53115 4
  23
  24 /* BCM5325m GLOBAL PAGE REGISTER MAP */
  25 #ifndef _CFE_
  26 #pragma pack(1)
  27 #endif
  28
  29 /* BCM5325m Serial Management Port (SMP) Page offsets */
  30 #define ROBO_CTRL_PAGE        0x00  /* Control registers */
  31 #define ROBO_STAT_PAGE        0x01  /* Status register */
  32 #define ROBO_MGMT_PAGE        0x02  /* Management Mode registers */
  33 #define ROBO_MIB_AC_PAGE      0x03  /* MIB Autocast registers */
  34 #define ROBO_ARLCTRL_PAGE     0x04  /* ARL Control Registers */
  35 #define ROBO_ARLIO_PAGE       0x05  /* ARL Access Registers */
  36 #define ROBO_FRAMEBUF_PAGE    0x06  /* Management frame access registers */
  37 #define ROBO_MEM_ACCESS_PAGE  0x08  /* Memory access registers */
  38
  39 /* PHY Registers */
  40 #define ROBO_PORT0_MII_PAGE    0x10 /* Port 0 MII Registers */
  41 #define ROBO_PORT1_MII_PAGE    0x11 /* Port 1 MII Registers */
  42 #define ROBO_PORT2_MII_PAGE    0x12 /* Port 2 MII Registers */
  43 #define ROBO_PORT3_MII_PAGE    0x13 /* Port 3 MII Registers */
  44 #define ROBO_PORT4_MII_PAGE    0x14 /* Port 4 MII Registers */
  45 /* (start) registers only for BCM5380 */
  46 #define ROBO_PORT5_MII_PAGE    0x15 /* Port 5 MII Registers */
  47 #define ROBO_PORT6_MII_PAGE    0x16 /* Port 6 MII Registers */
  48 #define ROBO_PORT7_MII_PAGE    0x17 /* Port 7 MII Registers */
  49 /* (end) registers only for BCM5380 */
  50 #define ROBO_IM_PORT_PAGE      0x18 /* Inverse MII Port (to EMAC) */
  51 #define ROBO_ALL_PORT_PAGE     0x19 /* All ports MII Registers (broadcast)*/
  52
  53 /* MAC Statistics registers */
  54 #define ROBO_PORT0_MIB_PAGE       0x20 /* Port 0 10/100 MIB Statistics */
  55 #define ROBO_PORT1_MIB_PAGE       0x21 /* Port 1 10/100 MIB Statistics */
  56 #define ROBO_PORT2_MIB_PAGE       0x22 /* Port 2 10/100 MIB Statistics */
  57 #define ROBO_PORT3_MIB_PAGE       0x23 /* Port 3 10/100 MIB Statistics */
  58 #define ROBO_PORT4_MIB_PAGE       0x24 /* Port 4 10/100 MIB Statistics */
  59 /* (start) registers only for BCM5380 */
  60 #define ROBO_PORT5_MIB_PAGE       0x25 /* Port 5 10/100 MIB Statistics */
  61 #define ROBO_PORT6_MIB_PAGE       0x26 /* Port 6 10/100 MIB Statistics */
  62 #define ROBO_PORT7_MIB_PAGE       0x27 /* Port 7 10/100 MIB Statistics */
  63 /* (end) registers only for BCM5380 */
  64 #define ROBO_IM_PORT_MIB_PAGE     0x28 /* Inverse MII Port MIB Statistics */
  65
  66 /* Quality of Service (QoS) Registers */
  67 #define ROBO_QOS_PAGE             0x30 /* QoS Registers */
  68
  69 /* VLAN Registers */
  70 #define ROBO_VLAN_PAGE            0x34 /* VLAN Registers */
  71
  72 /* Note SPI Data/IO Registers not used */
  73 #define ROBO_SPI_DATA_IO_0_PAGE   0xf0 /* SPI Data I/O 0 */
  74 #define ROBO_SPI_DATA_IO_1_PAGE   0xf1 /* SPI Data I/O 1 */
  75 #define ROBO_SPI_DATA_IO_2_PAGE   0xf2 /* SPI Data I/O 2 */
  76 #define ROBO_SPI_DATA_IO_3_PAGE   0xf3 /* SPI Data I/O 3 */
  77 #define ROBO_SPI_DATA_IO_4_PAGE   0xf4 /* SPI Data I/O 4 */
  78 #define ROBO_SPI_DATA_IO_5_PAGE   0xf5 /* SPI Data I/O 5 */
  79 #define ROBO_SPI_DATA_IO_6_PAGE   0xf6 /* SPI Data I/O 6 */
  80 #define ROBO_SPI_DATA_IO_7_PAGE   0xf7 /* SPI Data I/O 7 */
  81
  82 #define ROBO_SPI_STATUS_PAGE      0xfe /* SPI Status Registers */
  83 #define ROBO_PAGE_PAGE            0xff /* Page Registers */
  84
  85
  86 /* BCM5325m CONTROL PAGE (0x00) REGISTER MAP : 8bit (byte) registers */
  87 typedef struct _ROBO_PORT_CTRL_STRUC
  88 {
  89     unsigned char   rx_disable:1;   /* rx disable */
  90     unsigned char   tx_disable:1;   /* tx disable */
  91     unsigned char   rsvd:3;         /* reserved */
  92     unsigned char   stp_state:3;    /* spanning tree state */
  93 } ROBO_PORT_CTRL_STRUC;
  94
  95 #define ROBO_PORT0_CTRL           0x00 /* 10/100 Port 0 Control */
  96 #define ROBO_PORT1_CTRL           0x01 /* 10/100 Port 1 Control */
  97 #define ROBO_PORT2_CTRL           0x02 /* 10/100 Port 2 Control */
  98 #define ROBO_PORT3_CTRL           0x03 /* 10/100 Port 3 Control */
  99 #define ROBO_PORT4_CTRL           0x04 /* 10/100 Port 4 Control */
 100 /* (start) registers only for BCM5380 */
 101 #define ROBO_PORT5_CTRL           0x05 /* 10/100 Port 5 Control */
 102 #define ROBO_PORT6_CTRL           0x06 /* 10/100 Port 6 Control */
 103 #define ROBO_PORT7_CTRL           0x07 /* 10/100 Port 7 Control */
 104 /* (end) registers only for BCM5380 */
 105 #define ROBO_IM_PORT_CTRL         0x08 /* 10/100 Port 8 Control */
 106 #define ROBO_SMP_CTRL             0x0a /* SMP Control register */
 107 #define ROBO_SWITCH_MODE          0x0b /* Switch Mode Control */
 108 #define ROBO_PORT_OVERRIDE_CTRL   0x0e /* Port state override */
 109 #define ROBO_PORT_OVERRIDE_RVMII  (1<<4) /* Bit 4 enables RvMII */
 110 #define ROBO_PD_MODE_CTRL         0x0f /* Power-down mode control */
 111 #define ROBO_IP_MULTICAST_CTRL    0x21 /* IP Multicast control */
 112
 113 /* BCM5325m STATUS PAGE (0x01) REGISTER MAP : 16bit/48bit registers */
 114 #define ROBO_HALF_DUPLEX 0
 115 #define ROBO_FULL_DUPLEX 1
 116
 117 #define ROBO_LINK_STAT_SUMMARY    0x00 /* Link Status Summary: 16bit */
 118 #define ROBO_LINK_STAT_CHANGE     0x02 /* Link Status Change: 16bit */
 119 #define ROBO_SPEED_STAT_SUMMARY   0x04 /* Port Speed Summary: 16bit*/
 120 #define ROBO_DUPLEX_STAT_SUMMARY  0x06 /* Duplex Status Summary: 16bit */
 121 #define ROBO_PAUSE_STAT_SUMMARY   0x08 /* PAUSE Status Summary: 16bit */
 122 #define ROBO_SOURCE_ADDR_CHANGE   0x0C /* Source Address Change: 16bit  */
 123 #define ROBO_LSA_PORT0            0x10 /* Last Source Addr, Port 0: 48bits*/
 124 #define ROBO_LSA_PORT1            0x16 /* Last Source Addr, Port 1: 48bits*/
 125 #define ROBO_LSA_PORT2            0x1c /* Last Source Addr, Port 2: 48bits*/
 126 #define ROBO_LSA_PORT3            0x22 /* Last Source Addr, Port 3: 48bits*/
 127 #define ROBO_LSA_PORT4            0x28 /* Last Source Addr, Port 4: 48bits*/
 128 #define ROBO_LSA_IM_PORT          0x40 /* Last Source Addr, IM Port: 48bits*/
 129
 130 /* BCM5325m MANAGEMENT MODE REGISTERS (0x02) REGISTER MAP: 8/48 bit regs*/
 131 typedef struct _ROBO_GLOBAL_CONFIG_STRUC
 132 {
 133     unsigned char   resetMIB:1;         /* reset MIB counters */
 134     unsigned char   rxBPDU:1;           /* receive BDPU enable */
 135     unsigned char   rsvd1:2;            /* reserved */
 136     unsigned char   MIBacHdrCtrl:1;     /* MIB autocast header control */
 137     unsigned char   MIBac:1;            /* MIB autocast enable */
 138     unsigned char   frameMgmtPort:2;    /* frame management port */
 139 } ROBO_GLOBAL_CONFIG_STRUC;
 140 #define ROBO_GLOBAL_CONFIG        0x00 /* Global Management Config: 8bit*/
 141 #define ROBO_MGMT_PORT_ID         0x02 /* Management Port ID: 8bit*/
 142 #define ROBO_RMON_MIB_STEER       0x04 /* RMON Mib Steering: 16bit */
 143 #define ROBO_MIB_MODE_SELECT      0x04 /* MIB Mode select: 16bit (BCM5350) */
 144 #define ROBO_AGE_TIMER_CTRL       0x06 /* Age time control: 32bit */
 145 #define ROBO_MIRROR_CAP_CTRL      0x10 /* Mirror Capture : 16bit */
 146 #define ROBO_MIRROR_ING_CTRL      0x12 /* Mirror Ingress Control: 16bit */
 147 #define ROBO_MIRROR_ING_DIV_CTRL  0x14 /* Mirror Ingress Divider: 16bit */
 148 #define ROBO_MIRROR_ING_MAC_ADDR  0x16 /* Ingress Mirror MAC Addr: 48bit*/
 149 #define ROBO_MIRROR_EGR_CTRL      0x1c /* Mirror Egress Control: 16bit */
 150 #define ROBO_MIRROR_EGR_DIV_CTRL  0x1e /* Mirror Egress Divider: 16bit */
 151 #define ROBO_MIRROR_EGR_MAC_ADDR  0x20 /* Egress Mirror MAC Addr: 48bit*/
 152
 153 /* BCM5325m MIB AUTOCAST REGISTERS (0x03) REGISTER MAP: 8/16/48 bit regs */
 154 #define ROBO_MIB_AC_PORT          0x00 /* MIB Autocast Port: 16bit */
 155 #define ROBO_MIB_AC_HDR_PTR       0x02 /* MIB Autocast Header pointer:16bit*/
 156 #define ROBO_MIB_AC_HDR_LEN       0x04 /* MIB Autocast Header Len: 16bit */
 157 #define ROBO_MIB_AC_DA            0x06 /* MIB Autocast DA: 48bit */
 158 #define ROBO_MIB_AC_SA            0x0c /* MIB Autocast SA: 48bit */
 159 #define ROBO_MIB_AC_TYPE          0x12 /* MIB Autocast Type: 16bit */
 160 #define ROBO_MIB_AC_RATE          0x14 /* MIB Autocast Rate: 8bit */
 161 #define ROBO_GET_AC_RATE(secs) ((secs)*10)
 162 #define ROBO_AC_RATE_MAX          0xff
 163 #define ROBO_AC_RATE_DEFAULT      0x64  /* 10 secs */
 164 typedef struct _ROBO_MIB_AC_STRUCT
 165 {
 166     unsigned char   opcode:4;       /* Tx MIB Autocast opcode */
 167     unsigned char   portno:4;       /* zero-based port no. */
 168     unsigned char   portstate:8;    /* port state */
 169     unsigned long long TxOctets;
 170     unsigned int    TxDropPkts;
 171     unsigned int    rsvd;
 172     unsigned int    TxBroadcastPkts;
 173     unsigned int    TxMulticastPkts;
 174     unsigned int    TxUnicastPkts;
 175     unsigned int    TxCollisions;
 176     unsigned int    TxSingleCollision;
 177     unsigned int    TxMultiCollision;
 178     unsigned int    TxDeferredTransmit;
 179     unsigned int    TxLateCollision;
 180     unsigned int    TxExcessiveCollision;
 181     unsigned int    TxFrameInDiscards;
 182     unsigned int    TxPausePkts;
 183     unsigned int    rsvd1[2];
 184     unsigned long long RxOctets;
 185     unsigned int    RxUndersizePkts;
 186     unsigned int    RxPausePkts;
 187     unsigned int    RxPkts64Octets;
 188     unsigned int    RxPkts64to127Octets;
 189     unsigned int    RxPkts128to255Octets;
 190     unsigned int    RxPkts256to511Octets;
 191     unsigned int    RxPkts512to1023Octets;
 192     unsigned int    RxPkts1024to1522Octets;
 193     unsigned int    RxOversizePkts;
 194     unsigned int    RxJabbers;
 195     unsigned int    RxAlignmentErrors;
 196     unsigned int    RxFCSErrors;
 197     unsigned long long RxGoodOctets;
 198     unsigned int    RxDropPkts;
 199     unsigned int    RxUnicastPkts;
 200     unsigned int    RxMulticastPkts;
 201     unsigned int    RxBroadcastPkts;
 202     unsigned int    RxSAChanges;
 203     unsigned int    RxFragments;
 204     unsigned int    RxExcessSizeDisc;
 205     unsigned int    RxSymbolError;
 206 } ROBO_MIB_AC_STRUCT;
 207
 208 /* BCM5325m ARL CONTROL REGISTERS (0x04) REGISTER MAP: 8/16/48/64 bit regs */
 209 #define ROBO_ARL_CONFIG           0x00 /* ARL Global Configuration: 8bit*/
 210 #define ROBO_BPDU_MC_ADDR_REG     0x04 /* BPDU Multicast Address Reg:64bit*/
 211 #define ROBO_MULTIPORT_ADDR_1     0x10 /* Multiport Address 1: 48 bits*/
 212 #define ROBO_MULTIPORT_VECTOR_1   0x16 /* Multiport Vector 1: 16 bits */
 213 #define ROBO_MULTIPORT_ADDR_2     0x20 /* Multiport Address 2: 48 bits*/
 214 #define ROBO_MULTIPORT_VECTOR_2   0x26 /* Multiport Vector 2: 16 bits */
 215 #define ROBO_SECURE_SRC_PORT_MASK 0x30 /* Secure Source Port Mask: 16 bits*/
 216 #define ROBO_SECURE_DST_PORT_MASK 0x32 /* Secure Dest Port Mask: 16 bits */
 217
 218
 219 /* BCM5325m ARL IO REGISTERS (0x05) REGISTER MAP: 8/16/48/64 bit regs */
 220 #define ARL_TABLE_WRITE 0              /* for read/write state in control reg */
 221 #define ARL_TABLE_READ  1              /* for read/write state in control reg */
 222 #ifdef BCM5380
 223 #define ARL_VID_BYTES   2              /* number of bytes for VID */
 224 #else
 225 #define ARL_VID_BYTES   1              /* number of bytes for VID */
 226 #endif
 227 typedef struct _ROBO_ARL_RW_CTRL_STRUC
 228 {
 229     unsigned char   ARLrw:1;    /* ARL read/write (1=read) */
 230     unsigned char   rsvd:6;     /* reserved */
 231     unsigned char   ARLStart:1; /* ARL start/done (1=start) */
 232 } ROBO_ARL_RW_CTRL_STRUC;
 233 typedef struct _ROBO_ARL_SEARCH_CTRL_STRUC
 234 {
 235     unsigned char   valid:1;    /* ARL search result valid */
 236     unsigned char   rsvd:6;     /* reserved */
 237     unsigned char   ARLStart:1; /* ARL start/done (1=start) */
 238 } ROBO_ARL_SEARCH_CTRL_STRUC;
 239 typedef struct _ROBO_ARL_ENTRY_CTRL_STRUC
 240 {
 241     unsigned char   portID:4;   /* port id */
 242     unsigned char   chipID:2;   /* chip id */
 243     unsigned char   rsvd:5;     /* reserved */
 244     unsigned char   prio:2;     /* priority */
 245     unsigned char   age:1;      /* age */
 246     unsigned char   staticEn:1; /* static */
 247     unsigned char   valid:1;    /* valid */
 248 } ROBO_ARL_ENTRY_CTRL_STRUC;
 249 typedef struct _ROBO_ARL_SEARCH_RESULT_CTRL_STRUC
 250 {
 251     unsigned char   portID:4;   /* port id */
 252     unsigned char   rsvd:1;     /* reserved */
 253     unsigned char   vid:8;      /* vlan id */
 254     unsigned char   age:1;      /* age */
 255     unsigned char   staticEn:1; /* static */
 256     unsigned char   valid:1;    /* valid */
 257 } ROBO_ARL_SEARCH_RESULT_CTRL_STRUC;
 258 typedef struct _ROBO_ARL_ENTRY_MAC_STRUC
 259 {
 260     unsigned char   macBytes[6];    /* MAC address */
 261 } ROBO_ARL_ENTRY_MAC_STRUC;
 262
 263 typedef struct _ROBO_ARL_ENTRY_STRUC
 264 {
 265     ROBO_ARL_ENTRY_MAC_STRUC    mac;    /* MAC address */
 266     ROBO_ARL_ENTRY_CTRL_STRUC   ctrl;   /* control bits */
 267 } ROBO_ARL_ENTRY_STRUC;
 268
 269 typedef struct _ROBO_ARL_SEARCH_RESULT_STRUC
 270 {
 271     ROBO_ARL_ENTRY_MAC_STRUC    mac;                    /* MAC address */
 272     ROBO_ARL_SEARCH_RESULT_CTRL_STRUC   ctrl;   /* control bits */
 273 } ROBO_ARL_SEARCH_RESULT_STRUC;
 274
 275 /* multicast versions of ARL entry structs */
 276 typedef struct _ROBO_ARL_ENTRY_MCAST_CTRL_STRUC
 277 {
 278     unsigned int    portMask:12;/* multicast port mask */
 279     unsigned char   prio:1;     /* priority */
 280     unsigned char   gigPort:1;  /* gigabit port 1 mask */
 281     unsigned char   staticEn:1; /* static */
 282     unsigned char   valid:1;    /* valid */
 283 } ROBO_ARL_ENTRY_MCAST_CTRL_STRUC;
 284 typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC
 285 {
 286     unsigned int    portMask:13;        /* multicast port mask */
 287     unsigned char   age:1;              /* age */
 288     unsigned char   staticEn:1;         /* static */
 289     unsigned char   valid:1;            /* valid */
 290 } ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC;
 291 /* BCM5350 extension register */
 292 typedef struct _ROBO_ARL_SEARCH_RESULT_EXTENSION
 293 {
 294     unsigned int    prio:2;         /* priority */
 295     unsigned int    portMask:1;     /* MSB (MII) of port mask for multicast */
 296     unsigned int    reserved:5;
 297 } ROBO_ARL_SEARCH_RESULT_EXTENSION;
 298
 299 typedef struct _ROBO_ARL_ENTRY_MCAST_STRUC
 300 {
 301     ROBO_ARL_ENTRY_MAC_STRUC        mac;    /* MAC address */
 302     ROBO_ARL_ENTRY_MCAST_CTRL_STRUC ctrl;   /* control bits */
 303 } ROBO_ARL_ENTRY_MCAST_STRUC;
 304 typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_STRUC
 305 {
 306     ROBO_ARL_ENTRY_MAC_STRUC    mac;                                    /* MAC address */
 307     ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC   ctrl;     /* control bits */
 308 } ROBO_ARL_SEARCH_RESULT_MCAST_STRUC;
 309
 310 #define ROBO_ARL_RW_CTRL          0x00 /* ARL Read/Write Control :  8bit */
 311 #define ROBO_ARL_MAC_ADDR_IDX     0x02 /* MAC Address Index: 48bit */
 312 #define ROBO_ARL_VID_TABLE_IDX    0x08 /* VID Table Address Index: 8bit */
 313 #define ROBO_ARL_ENTRY0           0x10 /* ARL Entry 0 : 64 bit */
 314 #define ROBO_ARL_ENTRY1           0x18 /* ARL Entry 1 : 64 bit */
 315 #define ROBO_ARL_SEARCH_CTRL      0x20 /* ARL Search Control: 8bit */
 316 #define ROBO_ARL_SEARCH_ADDR      0x22 /* ARL Search Address: 16bit */
 317 #define ROBO_ARL_SEARCH_RESULT    0x24 /* ARL Search Result: 64bit */
 318 #define ROBO_ARL_SEARCH_RESULT_EXT 0x2c /* ARL Search Result Extension (5350): 8bit */
 319 #define ROBO_ARL_VID_ENTRY0       0x30 /* ARL VID Entry 0: 64bit */
 320 #define ROBO_ARL_VID_ENTRY1       0x32 /* ARL VID Entry 1: 64bit */
 321 #define ROBO_ARL_SEARCH_CTRL_53115       0x50 /* ARL Search Control: 8bit */
 322 #define ROBO_ARL_SEARCH_ADDR_53115       0x51 /* ARL Search Address: 16bit */
 323 #define ROBO_ARL_SEARCH_RESULT_53115     0x60 /* ARL Search Result: 64bit */
 324 #define ROBO_ARL_SEARCH_RESULT_EXT_53115 0x68 /* ARL Search Result Extension (53115): 16bit */
 325
 326 /* BCM5395/5397/5398/53115 */
 327 #define ROBO_VTBL_ACCESS          0x60 /* VLAN table access: 8bit */
 328 #define ROBO_VTBL_INDX            0x61 /* VLAN table address index: 16bit */
 329 #define ROBO_VTBL_ENTRY           0x63 /* VLAN table entry: 32bit */
 330 #define ROBO_VTBL_ACCESS_5395     0x80 /* VLAN table access: 8bit */
 331 #define ROBO_VTBL_INDX_5395       0x81 /* VLAN table address index: 16bit */
 332 #define ROBO_VTBL_ENTRY_5395      0x83 /* VLAN table entry: 32bit */
 333
 334 /* BCM5325m MANAGEMENT FRAME REGISTERS (0x6) REGISTER MAP: 8/16 bit regs */
 335 #define ROBO_MGMT_FRAME_RD_DATA   0x00 /* Management Frame Read Data :8bit*/
 336 #define ROBO_MGMT_FRAME_WR_DATA   0x01 /* Management Frame Write Data:8bit*/
 337 #define ROBO_MGMT_FRAME_WR_CTRL   0x02 /* Write Control: 16bit */
 338 #define ROBO_MGMT_FRAME_RD_STAT   0x04 /* Read Status: 16bit */
 339
 340 /* BCM5325m MEMORY ACCESS REGISTERS (Page 0x08) REGISTER MAP: 32 bit regs */
 341 #define MEM_TABLE_READ  1               /* for read/write state in mem access reg */
 342 #define MEM_TABLE_WRITE 0               /* for read/write state in mem access reg */
 343 #define MEM_TABLE_ACCESS_START 1        /* for mem access read/write start */
 344 #define MEM_TABLE_ACCESS_DONE  0        /* for mem access read/write done */
 345 #define VLAN_TABLE_ADDR 0x3800          /* BCM5380 only */
 346 #ifdef BCM5380
 347 #define NUM_ARL_TABLE_ENTRIES 4096      /* number of entries in ARL table */
 348 #define NUM_VLAN_TABLE_ENTRIES 2048     /* number of entries in VLAN table */
 349 #define ARL_TABLE_ADDR 0                /* offset of ARL table start */
 350 #else
 351 #define NUM_ARL_TABLE_ENTRIES 2048      /* number of entries in ARL table */
 352 #define NUM_VLAN_TABLE_ENTRIES 256      /* number of entries in VLAN table */
 353 #define ARL_TABLE_ADDR 0x3800           /* offset of ARL table start */
 354 /* corresponding values for 5350 */
 355 #define NUM_ARL_TABLE_ENTRIES_5350 1024 /* number of entries in ARL table (5350) */
 356 #define NUM_VLAN_TABLE_ENTRIES_5350 16  /* number of entries in VLAN table */
 357 #define ARL_TABLE_ADDR_5350 0x1c00      /* offset of ARL table start (5350) */
 358 #endif
 359 #define NUM_ARL_TABLE_ENTRIES_53115 4096 /* number of entries in ARL table (53115) */
 360 #define NUM_VLAN_TABLE_ENTRIES_53115 4096 /* number of entries in VLAN table */
 361 typedef struct _ROBO_MEM_ACCESS_CTRL_STRUC
 362 {
 363     unsigned int    memAddr:14; /* 64-bit memory address */
 364     unsigned char   rsvd:4;     /* reserved */
 365     unsigned char   readEn:1;   /* read enable (0 == write) */
 366     unsigned char   startDone:1;/* memory access start/done */
 367     unsigned int    rsvd1:12;   /* reserved */
 368 } ROBO_MEM_ACCESS_CTRL_STRUC;
 369 typedef struct _ROBO_MEM_ACCESS_DATA_STRUC
 370 {
 371     unsigned int    memData[2]; /* 64-bit data */
 372     unsigned short  rsvd;       /* reserved */
 373 } ROBO_MEM_ACCESS_DATA_STRUC;
 374
 375 #ifdef BCM5380
 376 typedef struct _ROBO_ARL_TABLE_DATA_STRUC
 377 {
 378     unsigned char   MACaddr[6]; /* MAC addr */
 379     unsigned int    portID:4;   /* port ID */
 380     unsigned int    chipID:2;   /* chip ID */
 381     unsigned int    rsvd:6;     /* reserved */
 382     unsigned int    highPrio:1; /* high priority address */
 383     unsigned int    age:1;      /* entry accessed/learned since ageing process */
 384     unsigned int    staticAddr:1;/* entry is static */
 385     unsigned int    valid:1;    /* entry is valid */
 386     unsigned int    vid:12;     /* vlan id */
 387     unsigned int    rsvd2:4;    /* reserved */
 388 } ROBO_ARL_TABLE_DATA_STRUC;
 389 #else
 390 typedef struct _ROBO_ARL_TABLE_DATA_STRUC
 391 {
 392     unsigned char   MACaddr[6]; /* MAC addr */
 393     unsigned int    portID:4;   /* port ID */
 394     unsigned int    chipID:2;   /* chip ID */
 395     unsigned int    rsvd:7;     /* reserved */
 396     unsigned int    age:1;      /* entry accessed/learned since ageing process */
 397     unsigned int    staticAddr:1;/* entry is static */
 398     unsigned int    valid:1;    /* entry is valid */
 399 } ROBO_ARL_TABLE_DATA_STRUC;
 400 #endif
 401
 402 /* multicast format*/
 403 typedef struct _ROBO_ARL_TABLE_MCAST_DATA_STRUC
 404 {
 405     unsigned char   MACaddr[6]; /* MAC addr */
 406     unsigned int    portMask:12;/* multicast port mask */
 407     unsigned char   prio:1;     /* priority */
 408     unsigned char   gigPort:1;  /* gigabit port 1 mask */
 409     unsigned char   staticEn:1; /* static */
 410     unsigned char   valid:1;    /* valid */
 411     unsigned int    vid:12;     /* vlan id */
 412     unsigned int    rsvd2:4;    /* reserved */
 413 } ROBO_ARL_TABLE_MCAST_DATA_STRUC;
 414 #define ROBO_MEM_ACCESS_CTRL      0x00 /* Memory Read/Write Control :32bit*/
 415 #define ROBO_MEM_ACCESS_DATA      0x04 /* Memory Read/Write Data:64bit*/
 416
 417 /* BCM5325m SWITCH PORT (0x10-18) REGISTER MAP: 8/16 bit regs */
 418 typedef struct _ROBO_MII_CTRL_STRUC
 419 {
 420     unsigned char   rsvd:8;     /* reserved */
 421     unsigned char   duplex:1;   /* duplex mode */
 422     unsigned char   restartAN:1;/* restart auto-negotiation */
 423     unsigned char   rsvd1:1;    /* reserved */
 424     unsigned char   powerDown:1;/* power down */
 425     unsigned char   ANenable:1; /* auto-negotiation enable */
 426     unsigned char   speed:1;    /* forced speed selection */
 427     unsigned char   loopback:1; /* loopback */
 428     unsigned char   reset:1;    /* reset */
 429 } ROBO_MII_CTRL_STRUC;
 430 typedef struct _ROBO_MII_AN_ADVERT_STRUC
 431 {
 432     unsigned char   selector:5;     /* advertise selector field */
 433     unsigned char   T10BaseT:1;     /* advertise 10BaseT */
 434     unsigned char   T10BaseTFull:1; /* advertise 10BaseT, full duplex */
 435     unsigned char   T100BaseX:1;    /* advertise 100BaseX */
 436     unsigned char   T100BaseXFull:1;/* advertise 100BaseX full duplex */
 437     unsigned char   noT4:1;         /* do not advertise T4 */
 438     unsigned char   pause:1;        /* advertise pause for full duplex */
 439     unsigned char   rsvd:2;         /* reserved */
 440     unsigned char   remoteFault:1;  /* transmit remote fault */
 441     unsigned char   rsvd1:1;        /* reserved */
 442     unsigned char   nextPage:1;     /* nex page operation supported */
 443 } ROBO_MII_AN_ADVERT_STRUC;
 444 #define ROBO_MII_CTRL                 0x00 /* Port MII Control */
 445 #define ROBO_MII_STAT                 0x01 /* Port MII Status  */
 446 /* Fields of link status register */
 447 #define ROBO_MII_STAT_JABBER          (1<<1) /* Jabber detected */
 448 #define ROBO_MII_STAT_LINK            (1<<2) /* Link status */
 449
 450 #define ROBO_MII_PHYID_HI             0x04 /* Port PHY ID High */
 451 #define ROBO_MII_PHYID_LO             0x06 /* Port PHY ID Low */
 452 #define ROBO_MII_ANA_REG              0x08 /* MII Auto-Neg Advertisement */
 453 #define ROBO_MII_ANP_REG              0x0a /* MII Auto-Neg Partner Ability */
 454 #define ROBO_MII_AN_EXP_REG           0x0c /* MII Auto-Neg Expansion */
 455 #define ROBO_MII_AN_NP_REG            0x0e /* MII next page */
 456 #define ROBO_MII_ANP_NP_REG           0x10 /* MII Partner next page */
 457 #define ROBO_MII_100BX_AUX_CTRL       0x20 /* 100BASE-X Auxiliary Control */
 458 #define ROBO_MII_100BX_AUX_STAT       0x22 /* 100BASE-X Auxiliary Status  */
 459 #define ROBO_MII_100BX_RCV_ERR_CTR    0x24 /* 100BASE-X Receive Error Ctr */
 460 #define ROBO_MII_100BX_RCV_FS_ERR     0x26 /* 100BASE-X Rcv False Sense Ctr */
 461 #define ROBO_MII_AUX_CTRL             0x30 /* Auxiliary Control/Status */
 462 /* Fields of Auxiliary control register */
 463 #define ROBO_MII_AUX_CTRL_FD         (1<<0) /* Full duplex link detected*/
 464 #define ROBO_MII_AUX_CTRL_SP100      (1<<1) /* Speed 100 indication */
 465 #define ROBO_MII_AUX_STATUS           0x32 /* Aux Status Summary */
 466 #define ROBO_MII_CONN_STATUS          0x34 /* Aux Connection Status */
 467 #define ROBO_MII_AUX_MODE2            0x36 /* Aux Mode 2 */
 468 #define ROBO_MII_AUX_ERR_STATUS       0x38 /* Aux Error and General Status */
 469 #define ROBO_MII_AUX_MULTI_PHY        0x3c /* Aux Multiple PHY Register*/
 470 #define ROBO_MII_BROADCOM_TEST        0x3e /* Broadcom Test Register */
 471
 472
 473 /* BCM5325m PORT MIB REGISTERS (Pages 0x20-0x24,0x28) REGISTER MAP: 64/32 */
 474 /* Tranmit Statistics */
 475 #define ROBO_MIB_TX_OCTETS            0x00 /* 64b: TxOctets */
 476 #define ROBO_MIB_TX_DROP_PKTS         0x08 /* 32b: TxDropPkts */
 477 #define ROBO_MIB_TX_BC_PKTS           0x10 /* 32b: TxBroadcastPkts */
 478 #define ROBO_MIB_TX_MC_PKTS           0x14 /* 32b: TxMulticastPkts */
 479 #define ROBO_MIB_TX_UC_PKTS           0x18 /* 32b: TxUnicastPkts */
 480 #define ROBO_MIB_TX_COLLISIONS        0x1c /* 32b: TxCollisions */
 481 #define ROBO_MIB_TX_SINGLE_COLLISIONS 0x20 /* 32b: TxSingleCollision */
 482 #define ROBO_MIB_TX_MULTI_COLLISIONS  0x24 /* 32b: TxMultiCollision */
 483 #define ROBO_MIB_TX_DEFER_TX          0x28 /* 32b: TxDeferred Transmit */
 484 #define ROBO_MIB_TX_LATE_COLLISIONS   0x2c /* 32b: TxLateCollision */
 485 #define ROBO_MIB_EXCESS_COLLISIONS    0x30 /* 32b: TxExcessiveCollision*/
 486 #define ROBO_MIB_FRAME_IN_DISCARDS    0x34 /* 32b: TxFrameInDiscards */
 487 #define ROBO_MIB_TX_PAUSE_PKTS        0x38 /* 32b: TxPausePkts */
 488
 489 /* Receive Statistics */
 490 #define ROBO_MIB_RX_OCTETS            0x44 /* 64b: RxOctets */
 491 #define ROBO_MIB_RX_UNDER_SIZE_PKTS   0x4c /* 32b: RxUndersizePkts(runts)*/
 492 #define ROBO_MIB_RX_PAUSE_PKTS        0x50 /* 32b: RxPausePkts */
 493 #define ROBO_MIB_RX_PKTS_64           0x54 /* 32b: RxPkts64Octets */
 494 #define ROBO_MIB_RX_PKTS_65_TO_127    0x58 /* 32b: RxPkts64to127Octets*/
 495 #define ROBO_MIB_RX_PKTS_128_TO_255   0x5c /* 32b: RxPkts128to255Octets*/
 496 #define ROBO_MIB_RX_PKTS_256_TO_511   0x60 /* 32b: RxPkts256to511Octets*/
 497 #define ROBO_MIB_RX_PKTS_512_TO_1023  0x64 /* 32b: RxPkts512to1023Octets*/
 498 #define ROBO_MIB_RX_PKTS_1024_TO_1522 0x68 /* 32b: RxPkts1024to1522Octets*/
 499 #define ROBO_MIB_RX_OVER_SIZE_PKTS    0x6c /* 32b: RxOversizePkts*/
 500 #define ROBO_MIB_RX_JABBERS           0x70 /* 32b: RxJabbers*/
 501 #define ROBO_MIB_RX_ALIGNMENT_ERRORS  0x74 /* 32b: RxAlignmentErrors*/
 502 #define ROBO_MIB_RX_FCS_ERRORS        0x78 /* 32b: RxFCSErrors */
 503 #define ROBO_MIB_RX_GOOD_OCTETS       0x7c /* 32b: RxGoodOctets */
 504 #define ROBO_MIB_RX_DROP_PKTS         0x84 /* 32b: RxDropPkts */
 505 #define ROBO_MIB_RX_UC_PKTS           0x88 /* 32b: RxUnicastPkts */
 506 #define ROBO_MIB_RX_MC_PKTS           0x8c /* 32b: RxMulticastPkts */
 507 #define ROBO_MIB_RX_BC_PKTS           0x90 /* 32b: RxBroadcastPkts */
 508 #define ROBO_MIB_RX_SA_CHANGES        0x94 /* 32b: RxSAChanges */
 509 #define ROBO_MIB_RX_FRAGMENTS         0x98 /* 32b: RxFragments */
 510 #define ROBO_MIB_RX_EXCESS_SZ_DISC    0x9c /* 32b: RxExcessSizeDisc*/
 511 #define ROBO_MIB_RX_SYMBOL_ERROR      0xa0 /* 32b: RxSymbolError */
 512
 513 /* BCM5350 MIB Statistics */
 514 /* Group 0 */
 515 #define ROBO_MIB_TX_GOOD_PKTS         0x00 /* 16b: TxGoodPkts */
 516 #define ROBO_MIB_TX_UNICAST_PKTS      0x02 /* 16b: TxUnicastPkts */
 517 #define ROBO_MIB_RX_GOOD_PKTS         0x04 /* 16b: RxGoodPkts */
 518 #define ROBO_MIB_RX_GOOD_UNICAST_PKTS 0x06 /* 16b: RxGoodUnicastPkts */
 519 /* Group 1 */
 520 #define ROBO_MIB_TX_COLLISION         0x00 /* 16b: TxCollision */
 521 #define ROBO_MIB_TX_OCTETS_5350       0x02 /* 16b: TxOctets */
 522 #define ROBO_MIB_RX_FCS_ERRORS_5350   0x04 /* 16b: RxFCSErrors */
 523 #define ROBO_MIB_RX_GOOD_OCTETS_5350  0x06 /* 16b: RxGoodOctets */
 524
 525 /* BCM5325m QoS REGISTERS (Page 0x30) REGISTER MAP: 8/16 */
 526 #define ROBO_QOS_CTRL                 0x00 /* 16b: QoS Control Register */
 527 #define ROBO_QOS_LOCAL_WEIGHT_CTRL    0x10 /* 8b: Local HQ/LQ Weight Register*/
 528 #define ROBO_QOS_CPU_WEIGHT_CTRL      0x12 /* 8b: CPU HQ/LQ Weight Register*/
 529 #define ROBO_QOS_PAUSE_ENA            0x13 /* 16b: Qos Pause Enable Register*/
 530 #define ROBO_QOS_PRIO_THRESHOLD       0x15 /* 8b: Priority Threshold Register*/
 531 #define ROBO_QOS_RESERVED             0x16 /* 8b: Qos Reserved Register */
 532
 533 /* BCM5325m VLAN REGISTERS (Page 0x34) REGISTER MAP: 8/16bit */
 534 typedef struct _ROBO_VLAN_CTRL0_STRUC
 535 {
 536     unsigned char   frameControlP:2;    /* 802.1P frame control */
 537     unsigned char   frameControlQ:2;    /* 802.1Q frame control */
 538     unsigned char   dropMissedVID:1;    /* enable drop missed VID packet */
 539     unsigned char   vidMacHash:1;       /* VID_MAC hash enable */
 540     unsigned char   vidMacCheck:1;      /* VID_MAC check enable */
 541     unsigned char   VLANen:1;           /* 802.1Q VLAN enable */
 542 } ROBO_VLAN_CTRL0_STRUC;
 543 #define VLAN_TABLE_WRITE 1              /* for read/write state in table access reg */
 544 #define VLAN_TABLE_READ 0               /* for read/write state in table access reg */
 545 #define VLAN_ID_HIGH_BITS 0             /* static high bits in table access reg */
 546 #define VLAN_ID_MAX 255                 /* max VLAN id */
 547 #define VLAN_ID_MAX5350 15              /* max VLAN id (5350) */
 548 #define VLAN_ID_MAX5395 4094            /* max VLAN id (5395) */
 549 #define VLAN_ID_MASK VLAN_ID_MAX        /* VLAN id mask */
 550 #ifdef BCM5380
 551 #define VLAN_UNTAG_SHIFT 13             /* for postioning untag bits in write reg */
 552 #define VLAN_VALID 0x4000000             /* valid bit in write reg */
 553 #else
 554 #define VLAN_UNTAG_SHIFT 7              /* for postioning untag bits in write reg */
 555 #define VLAN_VALID 0x4000               /* valid bit in write reg */
 556 /* corresponding values for 5350 */
 557 #define VLAN_UNTAG_SHIFT_5350 6         /* for postioning untag bits in write reg */
 558 #define VLAN_VALID_5350 0x00100000      /* valid bit in write reg */
 559 #endif
 560 typedef struct _ROBO_VLAN_TABLE_ACCESS_STRUC
 561 {
 562     unsigned char   VLANid:8;           /* VLAN ID (low 8 bits) */
 563     unsigned char   VLANidHi:4;         /* VLAN ID (fixed upper portion) */
 564     unsigned char   readWriteState:1;   /* read/write state (write = 1) */
 565     volatile unsigned char   readWriteEnable:1;  /* table read/write enable */
 566     unsigned char   rsvd:2;             /* reserved */
 567 } ROBO_VLAN_TABLE_ACCESS_STRUC;
 568 #ifdef BCM5380
 569 typedef struct _ROBO_VLAN_READ_WRITE_STRUC
 570 {
 571     unsigned int    VLANgroup:13;/* VLAN group mask */
 572     unsigned int    VLANuntag:13;/* VLAN untag enable mask */
 573     unsigned char   valid:1;     /* valid */
 574     unsigned char   rsvd:5;      /* reserved */
 575 } ROBO_VLAN_READ_WRITE_STRUC;
 576 #else
 577 typedef struct _ROBO_VLAN_READ_WRITE_STRUC
 578 {
 579     unsigned char   VLANgroup:7;         /* VLAN group mask */
 580     unsigned char   VLANuntag:7;         /* VLAN untag enable mask */
 581     unsigned char   valid:1;             /* valid */
 582     unsigned char   rsvd:1;              /* reserved */
 583 } ROBO_VLAN_READ_WRITE_STRUC;
 584 typedef struct _ROBO_VLAN_READ_WRITE_STRUC_5350
 585 {
 586     unsigned char   VLANgroup:6;         /* VLAN group mask */
 587     unsigned char   VLANuntag:6;         /* VLAN untag enable mask */
 588     unsigned char   highVID:8;           /* upper bits of vid */
 589     unsigned char   valid:1;             /* valid */
 590     unsigned int    rsvd:11;             /* reserved */
 591 } ROBO_VLAN_READ_WRITE_STRUC_5350;
 592 #endif
 593 #define ROBO_VLAN_CTRL0             0x00 /* 8b: VLAN Control 0 Register */
 594 #define ROBO_VLAN_CTRL1             0x01 /* 8b: VLAN Control 1 Register */
 595 #define ROBO_VLAN_CTRL2             0x02 /* 8b: VLAN Control 2 Register */
 596 #define ROBO_VLAN_CTRL3             0x03 /* 8b: VLAN Control 3 Register */
 597 #define ROBO_VLAN_CTRL4             0x04 /* 8b: VLAN Control 4 Register */
 598 #define ROBO_VLAN_CTRL5             0x05 /* 8b: VLAN Control 5 Register */
 599 #define ROBO_VLAN_TABLE_ACCESS      0x08 /* 14b: VLAN Table Access Register */
 600 #define ROBO_VLAN_TABLE_ACCESS_5350 0x06 /* 14b: VLAN Table Access Register (5350) */
 601 #define ROBO_VLAN_WRITE             0x0a /* 15b: VLAN Write Register */
 602 #define ROBO_VLAN_WRITE_5350        0x08 /* 15b: VLAN Write Register (5350) */
 603 #define ROBO_VLAN_READ              0x0c /* 15b: VLAN Read Register */
 604 #define ROBO_VLAN_PORT0_DEF_TAG     0x10 /* 16b: VLAN Port 0 Default Tag Register */
 605 #define ROBO_VLAN_PORT1_DEF_TAG     0x12 /* 16b: VLAN Port 1 Default Tag Register */
 606 #define ROBO_VLAN_PORT2_DEF_TAG     0x14 /* 16b: VLAN Port 2 Default Tag Register */
 607 #define ROBO_VLAN_PORT3_DEF_TAG     0x16 /* 16b: VLAN Port 3 Default Tag Register */
 608 #define ROBO_VLAN_PORT4_DEF_TAG     0x18 /* 16b: VLAN Port 4 Default Tag Register */
 609 #define ROBO_VLAN_PORTMII_DEF_TAG   0x1a /* 16b: VLAN Port MII Default Tag Register */
 610 /* 5380 only */
 611 #define ROBO_VLAN_PORT5_DEF_TAG     0x1a /* 16b: VLAN Port 5 Default Tag Register */
 612 #define ROBO_VLAN_PORT6_DEF_TAG     0x1c /* 16b: VLAN Port 6 Default Tag Register */
 613 #define ROBO_VLAN_PORT7_DEF_TAG     0x1e /* 16b: VLAN Port 7 Default Tag Register */
 614 #define ROBO_VLAN_PORT8_DEF_TAG     0x20 /* 16b: VLAN Port 8 Default Tag Register */
 615 /* 53115 only */
 616 #define ROBO_DUPLEX_STAT_SUMMARY_53115 0x08 /* Duplex Status Summary: 16bit */
 617 #define ROBO_JUMBO_PAGE                0x40
 618 #define ROBO_JUMBO_CTRL                0x01 /* 32bit */
 619 #define ROBO_JUMBO_SIZE                0x05 /* 16bit */
 620
 621 #ifndef _CFE_
 622 #pragma pack()
 623 #endif
 624
 625 #endif /* !__BCM535M_H_ */