2 * pcicfg.h: PCI configuration constants and structures.
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: pcicfg.h,v 1.50 2009-12-07 21:56:06 Exp $
24 #ifndef LINUX_POSTMOGRIFY_REMOVAL
25 /* The following inside ifndef's so we don't collide with NTDDK.H */
27 #define PCI_MAX_BUS 0x100
29 #ifndef PCI_MAX_DEVICES
30 #define PCI_MAX_DEVICES 0x20
32 #ifndef PCI_MAX_FUNCTION
33 #define PCI_MAX_FUNCTION 0x8
36 #ifndef PCI_INVALID_VENDORID
37 #define PCI_INVALID_VENDORID 0xffff
39 #ifndef PCI_INVALID_DEVICEID
40 #define PCI_INVALID_DEVICEID 0xffff
44 /* Convert between bus-slot-function-register and config addresses */
46 #define PCICFG_BUS_SHIFT 16 /* Bus shift */
47 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */
48 #define PCICFG_FUN_SHIFT 8 /* Function shift */
49 #define PCICFG_OFF_SHIFT 0 /* Register shift */
51 #define PCICFG_BUS_MASK 0xff /* Bus mask */
52 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */
53 #define PCICFG_FUN_MASK 7 /* Function mask */
54 #define PCICFG_OFF_MASK 0xff /* Bus mask */
56 #define PCI_CONFIG_ADDR(b, s, f, o) \
57 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
58 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
59 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
60 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
62 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
63 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
64 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
65 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
67 /* PCIE Config space accessing MACROS */
69 #define PCIECFG_BUS_SHIFT 24 /* Bus shift */
70 #define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
71 #define PCIECFG_FUN_SHIFT 16 /* Function shift */
72 #define PCIECFG_OFF_SHIFT 0 /* Register shift */
74 #define PCIECFG_BUS_MASK 0xff /* Bus mask */
75 #define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
76 #define PCIECFG_FUN_MASK 7 /* Function mask */
77 #define PCIECFG_OFF_MASK 0xfff /* Register mask */
79 #define PCIE_CONFIG_ADDR(b, s, f, o) \
80 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
81 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
82 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
83 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
85 #define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
86 #define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
87 #define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
88 #define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
90 /* The actual config space */
96 #define PCR_RSVDA_MAX 2
98 /* Bits in PCI bars' flags */
100 #define PCIBAR_FLAGS 0xf
101 #define PCIBAR_IO 0x1
102 #define PCIBAR_MEM1M 0x2
103 #define PCIBAR_MEM64 0x4
104 #define PCIBAR_PREFETCH 0x8
105 #define PCIBAR_MEM32_MASK 0xFFFFFF80
107 /* pci config status reg has a bit to indicate that capability ptr is present */
109 #define PCI_CAPPTR_PRESENT 0x0010
111 typedef struct _pci_config_regs
{
120 uint8 cache_line_size
;
124 uint32 base
[PCI_BAR_MAX
];
126 uint16 subsys_vendor
;
129 uint32 rsvd_a
[PCR_RSVDA_MAX
];
137 #define SZPCR (sizeof (pci_config_regs))
138 #define MINSZPCR 64 /* offsetof (dev_dep[0] */
140 /* A structure for the config registers is nice, but in most
141 * systems the config space is not memory mapped, so we need
142 * field offsetts. :-(
144 #define PCI_CFG_VID 0
145 #define PCI_CFG_DID 2
146 #define PCI_CFG_CMD 4
147 #define PCI_CFG_STAT 6
148 #define PCI_CFG_REV 8
149 #define PCI_CFG_PROGIF 9
150 #define PCI_CFG_SUBCL 0xa
151 #define PCI_CFG_BASECL 0xb
152 #define PCI_CFG_CLSZ 0xc
153 #define PCI_CFG_LATTIM 0xd
154 #define PCI_CFG_HDR 0xe
155 #define PCI_CFG_BIST 0xf
156 #define PCI_CFG_BAR0 0x10
157 #define PCI_CFG_BAR1 0x14
158 #define PCI_CFG_BAR2 0x18
159 #define PCI_CFG_BAR3 0x1c
160 #define PCI_CFG_BAR4 0x20
161 #define PCI_CFG_BAR5 0x24
162 #define PCI_CFG_CIS 0x28
163 #define PCI_CFG_SVID 0x2c
164 #define PCI_CFG_SSID 0x2e
165 #define PCI_CFG_ROMBAR 0x30
166 #define PCI_CFG_CAPPTR 0x34
167 #define PCI_CFG_INT 0x3c
168 #define PCI_CFG_PIN 0x3d
169 #define PCI_CFG_MINGNT 0x3e
170 #define PCI_CFG_MAXLAT 0x3f
173 #undef PCI_CLASS_DISPLAY
174 #undef PCI_CLASS_MEMORY
175 #undef PCI_CLASS_BRIDGE
176 #undef PCI_CLASS_INPUT
177 #undef PCI_CLASS_DOCK
178 #endif /* __NetBSD__ */
181 #undef PCI_CLASS_BRIDGE
183 #undef PCI_CLASS_DISPLAY
184 #undef PCI_CLASS_SERIAL
185 #undef PCI_CLASS_SATELLITE
188 /* Classes and subclasses */
204 PCI_CLASS_INTELLIGENT
= 0xe,
217 PCI_DASDI_OTHER
= 0x80
218 } pci_dasdi_subclasses
;
226 } pci_net_subclasses
;
232 PCI_DISPLAY_OTHER
= 0x80
233 } pci_display_subclasses
;
239 PCI_MEDIA_OTHER
= 0x80
240 } pci_mmedia_subclasses
;
245 PCI_MEMORY_OTHER
= 0x80
246 } pci_memory_subclasses
;
258 PCI_BRIDGE_OTHER
= 0x80
259 } pci_bridge_subclasses
;
266 PCI_COMM_OTHER
= 0x80
267 } pci_comm_subclasses
;
274 PCI_BASE_PCI_HOTPLUG
,
275 PCI_BASE_OTHER
= 0x80
276 } pci_base_subclasses
;
284 PCI_INPUT_OTHER
= 0x80
285 } pci_input_subclasses
;
289 PCI_DOCK_OTHER
= 0x80
290 } pci_dock_subclasses
;
296 PCI_CPU_ALPHA
= 0x10,
297 PCI_CPU_POWERPC
= 0x20,
299 PCI_CPU_COPROC
= 0x40,
301 } pci_cpu_subclasses
;
310 PCI_SERIAL_OTHER
= 0x80
311 } pci_serial_subclasses
;
315 } pci_intelligent_subclasses
;
322 PCI_SATELLITE_OTHER
= 0x80
323 } pci_satellite_subclasses
;
327 PCI_CRYPT_ENTERTAINMENT
,
328 PCI_CRYPT_OTHER
= 0x80
329 } pci_crypt_subclasses
;
334 } pci_dsp_subclasses
;
339 } pci_xor_subclasses
;
342 #define PCI_HEADER_MULTI 0x80
343 #define PCI_HEADER_MASK 0x7f
351 /* Overlay for a PCI-to-PCI bridge */
353 #define PPB_RSVDA_MAX 2
354 #define PPB_RSVDD_MAX 8
356 typedef struct _ppb_config_regs
{
365 uint8 cache_line_size
;
369 uint32 rsvd_a
[PPB_RSVDA_MAX
];
381 uint32 pf_mem_base_hi
;
382 uint32 pf_mem_lim_hi
;
385 uint16 subsys_vendor
;
394 uint32 rsvd_d
[PPB_RSVDD_MAX
];
399 /* PCI CAPABILITY DEFINES */
400 #define PCI_CAP_POWERMGMTCAP_ID 0x01
401 #define PCI_CAP_MSICAP_ID 0x05
402 #define PCI_CAP_VENDSPEC_ID 0x09
403 #define PCI_CAP_PCIECAP_ID 0x10
405 /* Data structure to define the Message Signalled Interrupt facility
406 * Valid for PCI and PCIE configurations
408 typedef struct _pciconfig_cap_msi
{
415 /* Data structure to define the Power managment facility
416 * Valid for PCI and PCIE configurations
418 typedef struct _pciconfig_cap_pwrmgmt
{
423 uint8 pme_bridge_ext
;
425 } pciconfig_cap_pwrmgmt
;
427 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
428 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
429 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
430 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
432 /* Data structure to define the PCIE capability */
433 typedef struct _pciconfig_cap_pcie
{
449 } pciconfig_cap_pcie
;
451 /* PCIE Enhanced CAPABILITY DEFINES */
452 #define PCIE_EXTCFG_OFFSET 0x100
453 #define PCIE_ADVERRREP_CAPID 0x0001
454 #define PCIE_VC_CAPID 0x0002
455 #define PCIE_DEVSNUM_CAPID 0x0003
456 #define PCIE_PWRBUDGET_CAPID 0x0004
458 /* PCIE Extended configuration */
459 #define PCIE_ADV_CORR_ERR_MASK 0x114
460 #define CORR_ERR_RE (1 << 0) /* Receiver */
461 #define CORR_ERR_BT (1 << 6) /* Bad TLP */
462 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */
463 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
464 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
465 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
466 CORR_ERR_RR | CORR_ERR_RT)
468 /* PCIE Root Control Register bits (Host mode only) */
469 #define PCIE_RC_CORR_SERR_EN 0x0001
470 #define PCIE_RC_NONFATAL_SERR_EN 0x0002
471 #define PCIE_RC_FATAL_SERR_EN 0x0004
472 #define PCIE_RC_PME_INT_EN 0x0008
473 #define PCIE_RC_CRS_EN 0x0010
475 /* PCIE Root Capability Register bits (Host mode only) */
476 #define PCIE_RC_CRS_VISIBILITY 0x0001
478 /* Header to define the PCIE specific capabilities in the extended config space */
479 typedef struct _pcie_enhanced_caphdr
{
482 uint16 next_ptr
: 12;
483 } pcie_enhanced_caphdr
;
486 /* Everything below is BRCM HND proprietary */
489 /* Brcm PCI configuration registers */
490 #define cap_list rsvd_a[0]
491 #define bar0_window dev_dep[0x80 - 0x40]
492 #define bar1_window dev_dep[0x84 - 0x40]
493 #define sprom_control dev_dep[0x88 - 0x40]
494 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
495 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
496 #ifndef LINUX_POSTMOGRIFY_REMOVAL
497 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
498 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */
499 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
500 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
501 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
502 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
503 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
504 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
505 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
506 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
507 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
508 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
509 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
511 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
512 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
513 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
514 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
515 * 8KB window, so their address is the "regular"
518 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
519 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
520 #ifndef LINUX_POSTMOGRIFY_REMOVAL
521 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
522 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
523 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
524 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
526 /* On AI chips we have a second window to map DMP regs are mapped: */
527 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
530 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
533 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
534 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
535 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
537 /* PCI_SPROM_CONTROL */
538 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
539 #define SPROM_LOCKED 0x08 /* SPROM Locked */
540 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */
541 #define SPROM_WRITEEN 0x10 /* SPROM write enable */
542 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
543 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
544 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */
546 /* Bits in PCI command and status regs */
547 #define PCI_CMD_IO 0x00000001 /* I/O enable */
548 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
549 #define PCI_CMD_MASTER 0x00000004 /* Master enable */
550 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
551 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
552 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
553 #define PCI_STAT_TA 0x08000000 /* target abort status */
554 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
555 #endif /* _h_pcicfg_ */