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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / sound / oss / au1550_i2s.c
blob529b6252cce3ac8016773d85d730965a740eeb6f
1 /*
2 * au1550_i2s.c -- Sound driver for Alchemy Au1550 MIPS
3 * Internet Edge Processor.
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 * Copyright 2005 Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Mostly copied from the au1550_psc.c driver and some from the
10 * PowerMac dbdma driver.
11 * We assume the processor can do memory coherent DMA.
12 *
13 * WM8731 mixer support, codec framework, cleanup, and 2.6 port
14 * Matt Porter <mporter@kernel.crashing.org>
15 *
16 * The SMBus (I2C) is required for the control of the
17 * appears at I2C address 0x36 (I2C binary 0011011). The Pb1550
18 * uses the Wolfson WM8731 codec, which is controlled over the I2C.
19 * It's connected to a 12MHz clock, so we can only reliably support
20 * 96KHz, 48KHz, 32KHz, and 8KHz data rates. Variable rate audio is
21 * unsupported, we currently force it to 48KHz.
22 *
23 * This program is free software; you can redistribute it and/or modify it
24 * under the terms of the GNU General Public License as published by the
25 * Free Software Foundation; either version 2 of the License, or (at your
26 * option) any later version.
27 *
28 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
31 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
34 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 * You should have received a copy of the GNU General Public License along
40 * with this program; if not, write to the Free Software Foundation, Inc.,
41 * 675 Mass Ave, Cambridge, MA 02139, USA.
42 *
43 */
44 #include <linux/module.h>
45 #include <linux/string.h>
46 #include <linux/ioport.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/fs.h>
50 #include <linux/hardirq.h>
51 #include <linux/sound.h>
52 #include <linux/slab.h>
53 #include <linux/soundcard.h>
54 #include <linux/init.h>
55 #include <linux/poll.h>
56 #include <linux/pci.h>
57 #include <linux/bitops.h>
58 #include <linux/proc_fs.h>
59 #include <linux/spinlock.h>
60 #include <linux/smp_lock.h>
61
62 #include <asm/io.h>
63 #include <asm/uaccess.h>
64 #include <asm/hardirq.h>
65
66 #include <asm/mach-au1x00/au1000.h>
67 #include <asm/mach-au1x00/au1xxx_psc.h>
68 #include <asm/mach-au1x00/au1xxx_dbdma.h>
69 #include <asm/mach-pb1x00/pb1550.h>
70
71 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
72
73 #define AU1550_MODULE_NAME "Au1550 I2S Audio"
74 #define PFX AU1550_MODULE_NAME
75
76 /* Define this if you want to try running at the 44.1 KHz rate.
77 * It's just a little off, I think it's actually 44117 or something.
78 * I did this for debugging, since many programs, including this
79 * driver, will try to upsample from 44.1 to 48 KHz.
80 * Seems to work well, we'll just leave it this way.
81 */
82 #define TRY_441KHz
83
84 #ifdef TRY_441KHz
85 #define SAMP_RATE 44100
86 #else
87 #define SAMP_RATE 48000
88 #endif
89
90 /* The number of DBDMA ring descriptors to allocate. No sense making
91 * this too large....if you can't keep up with a few you aren't likely
92 * to be able to with lots of them, either.
93 */
94 #define NUM_DBDMA_DESCRIPTORS 4
95
96 #define pr_error(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
97
98 static void
99 au1550_delay(int msec)
100 {
101 unsigned long tmo;
102 signed long tmo2;
103
104 if (in_interrupt())
105 return;
106
107 tmo = jiffies + (msec * HZ) / 1000;
108 for (;;) {
109 tmo2 = tmo - jiffies;
110 if (tmo2 <= 0)
111 break;
112 schedule_timeout(tmo2);
113 }
114 }
115
116 /*
117 * Codec framework. If somebody supports another codec, they
118 * should hopefully be able to define another struct i2s_codec
119 * definition, and #ifdef the support for it and the WM8731 so
120 * they can be selected via a CONFIG option. For now, we just
121 * hardcode WM8731_CODEC.
122 */
123 #define i2s_supported_mixer(CODEC,FOO) ((FOO >= 0) && \
124 (FOO < SOUND_MIXER_NRDEVICES) && \
125 (CODEC)->supported_mixers & (1<<FOO) )
126
127 struct i2s_codec {
128 int modcnt;
129 int supported_mixers;
130 int stereo_mixers;
131 int record_sources;
132 unsigned int mixer_state[SOUND_MIXER_NRDEVICES];
133 void *data;
134 int (*set_mixer) (struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val);
135 void (*init_codec) (struct i2s_codec *codec);
136 };
137
138 #define WM8731_CODEC
139 #ifdef WM8731_CODEC
140 /*
141 * WM8731 codec support
142 */
143 #define WM8731_SUPPORTED_MASK (WM8731_STEREO_MASK|WM8731_RECORD_MASK)
144 #define WM8731_STEREO_MASK (SOUND_MASK_VOLUME|SOUND_MASK_LINE)
145 #define WM8731_RECORD_MASK (SOUND_MASK_MIC|SOUND_MASK_LINE)
146
147 static struct codec_data {
148 u16 audio_path;
149 } wm8731_data;
150
151 static void
152 wm8731_wrcodec(u8 ctlreg, u8 val)
153 {
154 int rcnt;
155 extern int pb1550_wm_codec_write(u8 addr, u8 reg, u8 val);
156
157 /* The codec is a write only device, with a 16-bit control/data
158 * word. Although it is written as two bytes on the I2C, the
159 * format is actually 7 bits of register and 9 bits of data.
160 * The ls bit of the first byte is the ms bit of the data.
161 */
162 rcnt = 0;
163 while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
164 && (rcnt < 50)) {
165 rcnt++;
166 }
167 }
168
169 static int
170 wm8731_set_mixer(struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val)
171 {
172 unsigned int lvol, rvol;
173 struct codec_data *cdata = (struct codec_data *)codec->data;
174
175 switch (oss_mixer) {
176 case SOUND_MIXER_VOLUME:
177 /* normalize OSS range to fit codec volume control */
178 lvol = ((((val & 0x7f00) >> 8) * 0x60) / 0x64) + 0x1f;
179 rvol = (((val & 0x7f) * 0x60) / 0x64) + 0x1f;
180 lvol |= 0x80;
181 rvol |= 0x80;
182 wm8731_wrcodec(0x04, lvol);
183 au1550_delay(10);
184 wm8731_wrcodec(0x06, rvol);
185 au1550_delay(10);
186 codec->mixer_state[oss_mixer] = val;
187 break;
188 case SOUND_MIXER_LINE:
189 /* normalize OSS range to fit codec line control */
190 lvol = ((((val & 0x7f00) >> 8) * 0x1f) / 0x64);
191 rvol = (((val & 0x7f) * 0x1f) / 0x64);
192 if (!(val & 0x1f00))
193 lvol |= 0x80;
194 else
195 lvol &= ~0x80;
196 if (!(val & 0x001f))
197 rvol |= 0x80;
198 else
199 rvol &= ~0x80;
200 wm8731_wrcodec(0x00, lvol);
201 au1550_delay(10);
202 wm8731_wrcodec(0x02, rvol);
203 au1550_delay(10);
204 codec->mixer_state[oss_mixer] = val;
205 break;
206 case SOUND_MIXER_MIC:
207 if (!val)
208 cdata->audio_path |= 0x02;
209 else {
210 if (val >= 0x32)
211 cdata->audio_path |= 0x01;
212 else
213 cdata->audio_path &= ~0x01;
214 cdata->audio_path &= ~0x02;
215 }
216 wm8731_wrcodec(0x08, cdata->audio_path);
217 au1550_delay(10);
218 codec->mixer_state[oss_mixer] = val;
219 break;
220 case SOUND_MIXER_RECSRC:
221 if (val & SOUND_MASK_LINE)
222 cdata->audio_path &= ~0x04;
223 else
224 cdata->audio_path |= 0x04;
225 wm8731_wrcodec(0x08, cdata->audio_path);
226 au1550_delay(10);
227 codec->mixer_state[oss_mixer] = val;
228 break;
229 default:
230 return -EINVAL;
231 }
232
233 return 0;
234 }
235
236 void
237 wm8731_init_codec(struct i2s_codec *codec)
238 {
239 struct codec_data *cdata = (struct codec_data *)codec->data;
240
241 wm8731_wrcodec(0x1e, 0x00); /* Reset */
242 au1550_delay(200);
243 wm8731_wrcodec(0x0c, 0x00); /* Power up everything */
244 au1550_delay(10);
245 wm8731_wrcodec(0x12, 0x00); /* Deactivate codec */
246 au1550_delay(10);
247 cdata->audio_path = 0x10;
248 /* Select DAC outputs to line out */
249 wm8731_wrcodec(0x08, cdata->audio_path);
250 au1550_delay(10);
251 wm8731_wrcodec(0x0a, 0x00); /* Disable output mute */
252 au1550_delay(10);
253 wm8731_wrcodec(0x0e, 0x02); /* Set slave, 16-bit, I2S modes */
254 au1550_delay(10);
255 wm8731_wrcodec(0x10, 0x01); /* 12MHz (USB), 250fs */
256 au1550_delay(10);
257 wm8731_wrcodec(0x12, 0x01); /* Activate codec */
258 au1550_delay(10);
259
260 codec->set_mixer(codec, SOUND_MIXER_VOLUME, 0x5050);
261 codec->set_mixer(codec, SOUND_MIXER_LINE, 0x0000);
262 codec->set_mixer(codec, SOUND_MIXER_MIC, 0x00);
263 codec->mixer_state[SOUND_MIXER_RECSRC] = SOUND_MIXER_LINE;
264 }
265
266 static struct i2s_codec au1550_i2s_codec = {
267 .supported_mixers = WM8731_SUPPORTED_MASK,
268 .stereo_mixers = WM8731_STEREO_MASK,
269 .record_sources = WM8731_RECORD_MASK,
270 .init_codec = &wm8731_init_codec,
271 .set_mixer = &wm8731_set_mixer,
272 .data = &wm8731_data,
273 };
274 #endif /* WM8731_CODEC */
275
276 static struct au1550_state {
277 /* soundcore stuff */
278 int dev_audio;
279 int dev_mixer;
280
281 spinlock_t lock;
282 struct semaphore open_sem;
283 struct semaphore sem;
284 mode_t open_mode;
285 wait_queue_head_t open_wait;
286 volatile psc_i2s_t *psc_addr;
287 struct i2s_codec *codec;
288
289 struct dmabuf {
290 u32 dmanr;
291 unsigned sample_rate;
292 unsigned src_factor;
293 unsigned sample_size;
294 int num_channels;
295 int dma_bytes_per_sample;
296 int user_bytes_per_sample;
297 int cnt_factor;
298
299 void *rawbuf;
300 unsigned buforder;
301 unsigned numfrag;
302 unsigned fragshift;
303 void *nextIn;
304 void *nextOut;
305 int count;
306 unsigned total_bytes;
307 unsigned error;
308 wait_queue_head_t wait;
309
310 /* redundant, but makes calculations easier */
311 unsigned fragsize;
312 unsigned dma_fragsize;
313 unsigned dmasize;
314 unsigned dma_qcount;
315
316 /* OSS stuff */
317 unsigned mapped:1;
318 unsigned ready:1;
319 unsigned stopped:1;
320 unsigned ossfragshift;
321 int ossmaxfrags;
322 unsigned subdivision;
323
324 /* Mixer stuff */
325 int dev_mixer;
326 } dma_dac, dma_adc;
327 } au1550_state;
328
329 static unsigned
330 ld2(unsigned int x)
331 {
332 unsigned r = 0;
333
334 if (x >= 0x10000) {
335 x >>= 16;
336 r += 16;
337 }
338 if (x >= 0x100) {
339 x >>= 8;
340 r += 8;
341 }
342 if (x >= 0x10) {
343 x >>= 4;
344 r += 4;
345 }
346 if (x >= 4) {
347 x >>= 2;
348 r += 2;
349 }
350 if (x >= 2)
351 r++;
352 return r;
353 }
354
355 /* stop the ADC before calling */
356 static void
357 set_adc_rate(struct au1550_state *s, unsigned rate)
358 {
359 struct dmabuf *adc = &s->dma_adc;
360
361 /* calc SRC factor */
362 adc->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
363 adc->sample_rate = SAMP_RATE / adc->src_factor;
364 return;
365
366 adc->src_factor = 1;
367 }
368
369 /* stop the DAC before calling */
370 static void
371 set_dac_rate(struct au1550_state *s, unsigned rate)
372 {
373 struct dmabuf *dac = &s->dma_dac;
374
375 /* calc SRC factor */
376 dac->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
377 dac->sample_rate = SAMP_RATE / dac->src_factor;
378 return;
379
380 dac->src_factor = 1;
381 }
382
383 static void
384 stop_dac(struct au1550_state *s)
385 {
386 struct dmabuf *db = &s->dma_dac;
387 unsigned long flags;
388 uint stat;
389 volatile psc_i2s_t *ip;
390
391 if (db->stopped)
392 return;
393
394 ip = s->psc_addr;
395 spin_lock_irqsave(&s->lock, flags);
396
397 ip->psc_i2spcr = PSC_I2SPCR_TP;
398 au_sync();
399
400 /* Wait for Transmit Busy to show disabled.
401 */
402 do {
403 stat = ip->psc_i2sstat;
404 au_sync();
405 } while ((stat & PSC_I2SSTAT_TB) != 0);
406
407 au1xxx_dbdma_reset(db->dmanr);
408
409 db->stopped = 1;
410
411 spin_unlock_irqrestore(&s->lock, flags);
412 }
413
414 static void
415 stop_adc(struct au1550_state *s)
416 {
417 struct dmabuf *db = &s->dma_adc;
418 unsigned long flags;
419 uint stat;
420 volatile psc_i2s_t *ip;
421
422 if (db->stopped)
423 return;
424
425 ip = s->psc_addr;
426 spin_lock_irqsave(&s->lock, flags);
427
428 ip->psc_i2spcr = PSC_I2SPCR_RP;
429 au_sync();
430
431 /* Wait for Receive Busy to show disabled.
432 */
433 do {
434 stat = ip->psc_i2sstat;
435 au_sync();
436 } while ((stat & PSC_I2SSTAT_RB) != 0);
437
438 au1xxx_dbdma_reset(db->dmanr);
439
440 db->stopped = 1;
441
442 spin_unlock_irqrestore(&s->lock, flags);
443 }
444
445 static void
446 set_xmit_slots(int num_channels)
447 {
448 /* This is here just as a place holder. The WM8731 only
449 * supports two fixed channels.
450 */
451 }
452
453 static void
454 set_recv_slots(int num_channels)
455 {
456 /* This is here just as a place holder. The WM8731 only
457 * supports two fixed channels.
458 */
459 }
460
461 static void
462 start_dac(struct au1550_state *s)
463 {
464 struct dmabuf *db = &s->dma_dac;
465 unsigned long flags;
466 volatile psc_i2s_t *ip;
467
468 if (!db->stopped)
469 return;
470
471 spin_lock_irqsave(&s->lock, flags);
472
473 ip = s->psc_addr;
474 set_xmit_slots(db->num_channels);
475 ip->psc_i2spcr = PSC_I2SPCR_TC;
476 au_sync();
477 ip->psc_i2spcr = PSC_I2SPCR_TS;
478 au_sync();
479
480 au1xxx_dbdma_start(db->dmanr);
481
482 db->stopped = 0;
483
484 spin_unlock_irqrestore(&s->lock, flags);
485 }
486
487 static void
488 start_adc(struct au1550_state *s)
489 {
490 struct dmabuf *db = &s->dma_adc;
491 int i;
492 volatile psc_i2s_t *ip;
493
494 if (!db->stopped)
495 return;
496
497 /* Put two buffers on the ring to get things started.
498 */
499 for (i=0; i<2; i++) {
500 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
501
502 db->nextIn += db->dma_fragsize;
503 if (db->nextIn >= db->rawbuf + db->dmasize)
504 db->nextIn -= db->dmasize;
505 }
506
507 ip = s->psc_addr;
508 set_recv_slots(db->num_channels);
509 au1xxx_dbdma_start(db->dmanr);
510 ip->psc_i2spcr = PSC_I2SPCR_RC;
511 au_sync();
512 ip->psc_i2spcr = PSC_I2SPCR_RS;
513 au_sync();
514
515 db->stopped = 0;
516 }
517
518 static int
519 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
520 {
521 unsigned user_bytes_per_sec;
522 unsigned bufs;
523 unsigned rate = db->sample_rate;
524
525 if (!db->rawbuf) {
526 db->ready = db->mapped = 0;
527 db->buforder = 5; /* 32 * PAGE_SIZE */
528 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
529 if (!db->rawbuf)
530 return -ENOMEM;
531 }
532
533 db->cnt_factor = 1;
534 if (db->sample_size == 8)
535 db->cnt_factor *= 2;
536 if (db->num_channels == 1)
537 db->cnt_factor *= 2;
538 db->cnt_factor *= db->src_factor;
539
540 db->count = 0;
541 db->dma_qcount = 0;
542 db->nextIn = db->nextOut = db->rawbuf;
543
544 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
545 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
546 2 : db->num_channels);
547
548 user_bytes_per_sec = rate * db->user_bytes_per_sample;
549 bufs = PAGE_SIZE << db->buforder;
550 if (db->ossfragshift) {
551 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
552 db->fragshift = ld2(user_bytes_per_sec/1000);
553 else
554 db->fragshift = db->ossfragshift;
555 } else {
556 db->fragshift = ld2(user_bytes_per_sec / 100 /
557 (db->subdivision ? db->subdivision : 1));
558 if (db->fragshift < 3)
559 db->fragshift = 3;
560 }
561
562 db->fragsize = 1 << db->fragshift;
563 db->dma_fragsize = db->fragsize * db->cnt_factor;
564 db->numfrag = bufs / db->dma_fragsize;
565
566 while (db->numfrag < 4 && db->fragshift > 3) {
567 db->fragshift--;
568 db->fragsize = 1 << db->fragshift;
569 db->dma_fragsize = db->fragsize * db->cnt_factor;
570 db->numfrag = bufs / db->dma_fragsize;
571 }
572
573 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
574 db->numfrag = db->ossmaxfrags;
575
576 db->dmasize = db->dma_fragsize * db->numfrag;
577 memset(db->rawbuf, 0, bufs);
578
579 #ifdef AU1000_VERBOSE_DEBUG
580 dbg("rate=%d, samplesize=%d, channels=%d",
581 rate, db->sample_size, db->num_channels);
582 dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
583 db->fragsize, db->cnt_factor, db->dma_fragsize);
584 dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
585 #endif
586
587 db->ready = 1;
588 return 0;
589 }
590
591 static int
592 prog_dmabuf_adc(struct au1550_state *s)
593 {
594 stop_adc(s);
595 return prog_dmabuf(s, &s->dma_adc);
596
597 }
598
599 static int
600 prog_dmabuf_dac(struct au1550_state *s)
601 {
602 stop_dac(s);
603 return prog_dmabuf(s, &s->dma_dac);
604 }
605
606
607 /* hold spinlock for the following */
608 static void
609 dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
610 {
611 struct au1550_state *s = (struct au1550_state *) dev_id;
612 struct dmabuf *db = &s->dma_dac;
613 u32 i2s_stat;
614 volatile psc_i2s_t *ip;
615
616 ip = s->psc_addr;
617 i2s_stat = ip->psc_i2sstat;
618 #ifdef AU1000_VERBOSE_DEBUG
619 if (i2s_stat & (PSC_I2SSTAT_TF | PSC_I2SSTAT_TR | PSC_I2SSTAT_TF))
620 dbg("I2S status = 0x%08x", i2s_stat);
621 #endif
622 db->dma_qcount--;
623
624 if (db->count >= db->fragsize) {
625 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
626 db->fragsize) == 0) {
627 pr_error("qcount < 2 and no ring room!");
628 }
629 db->nextOut += db->fragsize;
630 if (db->nextOut >= db->rawbuf + db->dmasize)
631 db->nextOut -= db->dmasize;
632 db->count -= db->fragsize;
633 db->total_bytes += db->dma_fragsize;
634 db->dma_qcount++;
635 }
636
637 /* wake up anybody listening */
638 if (waitqueue_active(&db->wait))
639 wake_up(&db->wait);
640 }
641
642
643 static void
644 adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
645 {
646 struct au1550_state *s = (struct au1550_state *)dev_id;
647 struct dmabuf *dp = &s->dma_adc;
648 u32 obytes;
649 char *obuf;
650
651 /* Pull the buffer from the dma queue.
652 */
653 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
654
655 if ((dp->count + obytes) > dp->dmasize) {
656 /* Overrun. Stop ADC and log the error
657 */
658 stop_adc(s);
659 dp->error++;
660 pr_error("adc overrun");
661 return;
662 }
663
664 /* Put a new empty buffer on the destination DMA.
665 */
666 au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
667
668 dp->nextIn += dp->dma_fragsize;
669 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
670 dp->nextIn -= dp->dmasize;
671
672 dp->count += obytes;
673 dp->total_bytes += obytes;
674
675 /* wake up anybody listening
676 */
677 if (waitqueue_active(&dp->wait))
678 wake_up(&dp->wait);
679
680 }
681
682 static loff_t
683 au1550_llseek(struct file *file, loff_t offset, int origin)
684 {
685 return -ESPIPE;
686 }
687
688 static int
689 au1550_open_mixdev(struct inode *inode, struct file *file)
690 {
691 file->private_data = &au1550_state;
692 return 0;
693 }
694
695 static int
696 au1550_release_mixdev(struct inode *inode, struct file *file)
697 {
698 return 0;
699 }
700
701 #define I2S_CODEC "Wolfson WM8731"
702
703 static int
704 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
705 unsigned int cmd, unsigned long arg)
706 {
707 struct au1550_state *s = (struct au1550_state *)file->private_data;
708 struct i2s_codec *codec = s->codec;
709 int i, val = 0;
710
711 if (cmd == SOUND_MIXER_INFO) {
712 mixer_info info;
713 memset(&info, 0, sizeof(info));
714 strlcpy(info.id, I2S_CODEC, sizeof(info.id));
715 strlcpy(info.name, I2S_CODEC, sizeof(info.name));
716 info.modify_counter = codec->modcnt;
717 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
718 return -EFAULT;
719 return 0;
720 }
721 if (cmd == SOUND_OLD_MIXER_INFO) {
722 _old_mixer_info info;
723 memset(&info, 0, sizeof(info));
724 strlcpy(info.id, I2S_CODEC, sizeof(info.id));
725 strlcpy(info.name, I2S_CODEC, sizeof(info.name));
726 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
727 return -EFAULT;
728 return 0;
729 }
730
731 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
732 return -EINVAL;
733
734 if (cmd == OSS_GETVERSION)
735 return put_user(SOUND_VERSION, (int __user *)arg);
736
737 if (_SIOC_DIR(cmd) == _SIOC_READ) {
738 switch (_IOC_NR(cmd)) {
739 case SOUND_MIXER_RECSRC: /* give them the current record source */
740 val = codec->mixer_state[SOUND_MIXER_RECSRC];
741 break;
742
743 case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
744 val = codec->supported_mixers;
745 break;
746
747 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
748 val = codec->record_sources;
749 break;
750
751 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
752 val = codec->stereo_mixers;
753 break;
754
755 case SOUND_MIXER_CAPS:
756 val = SOUND_CAP_EXCL_INPUT;
757 break;
758
759 default: /* read a specific mixer */
760 i = _IOC_NR(cmd);
761
762 if (!i2s_supported_mixer(codec, i))
763 return -EINVAL;
764
765 val = codec->mixer_state[i];
766 break;
767 }
768 return put_user(val, (int __user *)arg);
769 }
770
771 if (_SIOC_DIR(cmd) == (_SIOC_WRITE|_SIOC_READ)) {
772 codec->modcnt++;
773 if (get_user(val, (int __user *)arg))
774 return -EFAULT;
775
776 switch (_IOC_NR(cmd)) {
777 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
778 if (!val) return 0;
779 if (!(val &= codec->record_sources)) return -EINVAL;
780
781 codec->set_mixer(codec, SOUND_MIXER_RECSRC, val);
782
783 return 0;
784 default: /* write a specific mixer */
785 i = _IOC_NR(cmd);
786
787 if (!i2s_supported_mixer(codec, i))
788 return -EINVAL;
789
790 codec->set_mixer(codec, i, val);
791
792 return 0;
793 }
794 }
795 return -EINVAL;
796 }
797
798 static struct file_operations au1550_mixer_fops = {
799 owner:THIS_MODULE,
800 llseek:au1550_llseek,
801 ioctl:au1550_ioctl_mixdev,
802 open:au1550_open_mixdev,
803 release:au1550_release_mixdev,
804 };
805
806 static int
807 drain_dac(struct au1550_state *s, int nonblock)
808 {
809 unsigned long flags;
810 int count, tmo;
811
812 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
813 return 0;
814
815 for (;;) {
816 spin_lock_irqsave(&s->lock, flags);
817 count = s->dma_dac.count;
818 spin_unlock_irqrestore(&s->lock, flags);
819 if (count <= 0)
820 break;
821 if (signal_pending(current))
822 break;
823 if (nonblock)
824 return -EBUSY;
825 tmo = 1000 * count / SAMP_RATE;
826 tmo /= s->dma_dac.dma_bytes_per_sample;
827 au1550_delay(tmo);
828 }
829 if (signal_pending(current))
830 return -ERESTARTSYS;
831 return 0;
832 }
833
834 static inline u8 S16_TO_U8(s16 ch)
835 {
836 return (u8) (ch >> 8) + 0x80;
837 }
838 static inline s16 U8_TO_S16(u8 ch)
839 {
840 return (s16) (ch - 0x80) << 8;
841 }
842
843 /*
844 * Translates user samples to dma buffer suitable for audio DAC data:
845 * If mono, copy left channel to right channel in dma buffer.
846 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
847 * If interpolating (no VRA), duplicate every audio frame src_factor times.
848 */
849 static int
850 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
851 int dmacount)
852 {
853 int sample, i;
854 int interp_bytes_per_sample;
855 int num_samples;
856 int mono = (db->num_channels == 1);
857 char usersample[12];
858 s16 ch, dmasample[6];
859
860 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
861 /* no translation necessary, just copy
862 */
863 if (copy_from_user(dmabuf, userbuf, dmacount))
864 return -EFAULT;
865 return dmacount;
866 }
867
868 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
869 num_samples = dmacount / interp_bytes_per_sample;
870
871 for (sample = 0; sample < num_samples; sample++) {
872 if (copy_from_user(usersample, userbuf,
873 db->user_bytes_per_sample)) {
874 return -EFAULT;
875 }
876
877 for (i = 0; i < db->num_channels; i++) {
878 if (db->sample_size == 8)
879 ch = U8_TO_S16(usersample[i]);
880 else
881 ch = *((s16 *) (&usersample[i * 2]));
882 dmasample[i] = ch;
883 if (mono)
884 dmasample[i + 1] = ch; /* right channel */
885 }
886
887 /* duplicate every audio frame src_factor times
888 */
889 for (i = 0; i < db->src_factor; i++)
890 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
891
892 userbuf += db->user_bytes_per_sample;
893 dmabuf += interp_bytes_per_sample;
894 }
895
896 return num_samples * interp_bytes_per_sample;
897 }
898
899 /*
900 * Translates audio ADC samples to user buffer:
901 * If mono, send only left channel to user buffer.
902 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
903 * If decimating (no VRA), skip over src_factor audio frames.
904 */
905 static int
906 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
907 int dmacount)
908 {
909 int sample, i;
910 int interp_bytes_per_sample;
911 int num_samples;
912 int mono = (db->num_channels == 1);
913 char usersample[12];
914
915 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
916 /* no translation necessary, just copy
917 */
918 if (copy_to_user(userbuf, dmabuf, dmacount))
919 return -EFAULT;
920 return dmacount;
921 }
922
923 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
924 num_samples = dmacount / interp_bytes_per_sample;
925
926 for (sample = 0; sample < num_samples; sample++) {
927 for (i = 0; i < db->num_channels; i++) {
928 if (db->sample_size == 8)
929 usersample[i] =
930 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
931 else
932 *((s16 *) (&usersample[i * 2])) =
933 *((s16 *) (&dmabuf[i * 2]));
934 }
935
936 if (copy_to_user(userbuf, usersample,
937 db->user_bytes_per_sample)) {
938 return -EFAULT;
939 }
940
941 userbuf += db->user_bytes_per_sample;
942 dmabuf += interp_bytes_per_sample;
943 }
944
945 return num_samples * interp_bytes_per_sample;
946 }
947
948 /*
949 * Copy audio data to/from user buffer from/to dma buffer, taking care
950 * that we wrap when reading/writing the dma buffer. Returns actual byte
951 * count written to or read from the dma buffer.
952 */
953 static int
954 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
955 {
956 char *bufptr = to_user ? db->nextOut : db->nextIn;
957 char *bufend = db->rawbuf + db->dmasize;
958 int cnt, ret;
959
960 if (bufptr + count > bufend) {
961 int partial = (int) (bufend - bufptr);
962 if (to_user) {
963 if ((cnt = translate_to_user(db, userbuf,
964 bufptr, partial)) < 0)
965 return cnt;
966 ret = cnt;
967 if ((cnt = translate_to_user(db, userbuf + partial,
968 db->rawbuf,
969 count - partial)) < 0)
970 return cnt;
971 ret += cnt;
972 } else {
973 if ((cnt = translate_from_user(db, bufptr, userbuf,
974 partial)) < 0)
975 return cnt;
976 ret = cnt;
977 if ((cnt = translate_from_user(db, db->rawbuf,
978 userbuf + partial,
979 count - partial)) < 0)
980 return cnt;
981 ret += cnt;
982 }
983 } else {
984 if (to_user)
985 ret = translate_to_user(db, userbuf, bufptr, count);
986 else
987 ret = translate_from_user(db, bufptr, userbuf, count);
988 }
989
990 return ret;
991 }
992
993 static ssize_t
994 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
995 {
996 struct au1550_state *s = (struct au1550_state *)file->private_data;
997 struct dmabuf *db = &s->dma_adc;
998 DECLARE_WAITQUEUE(wait, current);
999 ssize_t ret;
1000 unsigned long flags;
1001 int cnt, usercnt, avail;
1002
1003 if (db->mapped)
1004 return -ENXIO;
1005 if (!access_ok(VERIFY_WRITE, buffer, count))
1006 return -EFAULT;
1007 ret = 0;
1008
1009 count *= db->cnt_factor;
1010
1011 down(&s->sem);
1012 add_wait_queue(&db->wait, &wait);
1013
1014 while (count > 0) {
1015 /* wait for samples in ADC dma buffer
1016 */
1017 do {
1018 if (db->stopped)
1019 start_adc(s);
1020 spin_lock_irqsave(&s->lock, flags);
1021 avail = db->count;
1022 if (avail <= 0)
1023 __set_current_state(TASK_INTERRUPTIBLE);
1024 spin_unlock_irqrestore(&s->lock, flags);
1025 if (avail <= 0) {
1026 if (file->f_flags & O_NONBLOCK) {
1027 if (!ret)
1028 ret = -EAGAIN;
1029 goto out;
1030 }
1031 up(&s->sem);
1032 schedule();
1033 if (signal_pending(current)) {
1034 if (!ret)
1035 ret = -ERESTARTSYS;
1036 goto out2;
1037 }
1038 down(&s->sem);
1039 }
1040 } while (avail <= 0);
1041
1042 /* copy from nextOut to user
1043 */
1044 if ((cnt = copy_dmabuf_user(db, buffer,
1045 count > avail ?
1046 avail : count, 1)) < 0) {
1047 if (!ret)
1048 ret = -EFAULT;
1049 goto out;
1050 }
1051
1052 spin_lock_irqsave(&s->lock, flags);
1053 db->count -= cnt;
1054 db->nextOut += cnt;
1055 if (db->nextOut >= db->rawbuf + db->dmasize)
1056 db->nextOut -= db->dmasize;
1057 spin_unlock_irqrestore(&s->lock, flags);
1058
1059 count -= cnt;
1060 usercnt = cnt / db->cnt_factor;
1061 buffer += usercnt;
1062 ret += usercnt;
1063 } /* while (count > 0) */
1064
1065 out:
1066 up(&s->sem);
1067 out2:
1068 remove_wait_queue(&db->wait, &wait);
1069 set_current_state(TASK_RUNNING);
1070 return ret;
1071 }
1072
1073 static ssize_t
1074 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1075 {
1076 struct au1550_state *s = (struct au1550_state *)file->private_data;
1077 struct dmabuf *db = &s->dma_dac;
1078 DECLARE_WAITQUEUE(wait, current);
1079 ssize_t ret = 0;
1080 unsigned long flags;
1081 int cnt, usercnt, avail;
1082
1083 #ifdef AU1000_VERBOSE_DEBUG
1084 dbg("write: count=%d", count);
1085 #endif
1086
1087 if (db->mapped)
1088 return -ENXIO;
1089 if (!access_ok(VERIFY_READ, buffer, count))
1090 return -EFAULT;
1091
1092 count *= db->cnt_factor;
1093
1094 down(&s->sem);
1095 add_wait_queue(&db->wait, &wait);
1096
1097 while (count > 0) {
1098 /* wait for space in playback buffer
1099 */
1100 do {
1101 spin_lock_irqsave(&s->lock, flags);
1102 avail = (int) db->dmasize - db->count;
1103 if (avail <= 0)
1104 __set_current_state(TASK_INTERRUPTIBLE);
1105 spin_unlock_irqrestore(&s->lock, flags);
1106 if (avail <= 0) {
1107 if (file->f_flags & O_NONBLOCK) {
1108 if (!ret)
1109 ret = -EAGAIN;
1110 goto out;
1111 }
1112 up(&s->sem);
1113 schedule();
1114 if (signal_pending(current)) {
1115 if (!ret)
1116 ret = -ERESTARTSYS;
1117 goto out2;
1118 }
1119 down(&s->sem);
1120 }
1121 } while (avail <= 0);
1122
1123 /* copy from user to nextIn
1124 */
1125 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1126 count > avail ?
1127 avail : count, 0)) < 0) {
1128 if (!ret)
1129 ret = -EFAULT;
1130 goto out;
1131 }
1132
1133 spin_lock_irqsave(&s->lock, flags);
1134 db->count += cnt;
1135 db->nextIn += cnt;
1136 if (db->nextIn >= db->rawbuf + db->dmasize)
1137 db->nextIn -= db->dmasize;
1138
1139 /* If the data is available, we want to keep two buffers
1140 * on the dma queue. If the queue count reaches zero,
1141 * we know the dma has stopped.
1142 */
1143 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1144 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1145 db->fragsize) == 0) {
1146 pr_error("qcount < 2 and no ring room!");
1147 }
1148 db->nextOut += db->fragsize;
1149 if (db->nextOut >= db->rawbuf + db->dmasize)
1150 db->nextOut -= db->dmasize;
1151 db->count -= db->fragsize;
1152 db->total_bytes += db->dma_fragsize;
1153 if (db->dma_qcount == 0)
1154 start_dac(s);
1155 db->dma_qcount++;
1156 }
1157 spin_unlock_irqrestore(&s->lock, flags);
1158
1159 count -= cnt;
1160 usercnt = cnt / db->cnt_factor;
1161 buffer += usercnt;
1162 ret += usercnt;
1163 } /* while (count > 0) */
1164
1165 out:
1166 up(&s->sem);
1167 out2:
1168 remove_wait_queue(&db->wait, &wait);
1169 set_current_state(TASK_RUNNING);
1170 return ret;
1171 }
1172
1173
1174 /* No kernel lock - we have our own spinlock */
1175 static unsigned int
1176 au1550_poll(struct file *file, struct poll_table_struct *wait)
1177 {
1178 struct au1550_state *s = (struct au1550_state *)file->private_data;
1179 unsigned long flags;
1180 unsigned int mask = 0;
1181
1182 if (file->f_mode & FMODE_WRITE) {
1183 if (!s->dma_dac.ready)
1184 return 0;
1185 poll_wait(file, &s->dma_dac.wait, wait);
1186 }
1187 if (file->f_mode & FMODE_READ) {
1188 if (!s->dma_adc.ready)
1189 return 0;
1190 poll_wait(file, &s->dma_adc.wait, wait);
1191 }
1192
1193 spin_lock_irqsave(&s->lock, flags);
1194
1195 if (file->f_mode & FMODE_READ) {
1196 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1197 mask |= POLLIN | POLLRDNORM;
1198 }
1199 if (file->f_mode & FMODE_WRITE) {
1200 if (s->dma_dac.mapped) {
1201 if (s->dma_dac.count >=
1202 (signed)s->dma_dac.dma_fragsize)
1203 mask |= POLLOUT | POLLWRNORM;
1204 } else {
1205 if ((signed) s->dma_dac.dmasize >=
1206 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1207 mask |= POLLOUT | POLLWRNORM;
1208 }
1209 }
1210 spin_unlock_irqrestore(&s->lock, flags);
1211 return mask;
1212 }
1213
1214 static int
1215 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1216 {
1217 struct au1550_state *s = (struct au1550_state *)file->private_data;
1218 struct dmabuf *db;
1219 unsigned long size;
1220 int ret = 0;
1221
1222 lock_kernel();
1223 down(&s->sem);
1224 if (vma->vm_flags & VM_WRITE)
1225 db = &s->dma_dac;
1226 else if (vma->vm_flags & VM_READ)
1227 db = &s->dma_adc;
1228 else {
1229 ret = -EINVAL;
1230 goto out;
1231 }
1232 if (vma->vm_pgoff != 0) {
1233 ret = -EINVAL;
1234 goto out;
1235 }
1236 size = vma->vm_end - vma->vm_start;
1237 if (size > (PAGE_SIZE << db->buforder)) {
1238 ret = -EINVAL;
1239 goto out;
1240 }
1241 if (remap_pfn_range(vma, vma->vm_start,
1242 page_to_pfn(virt_to_page(db->rawbuf)),
1243 size, vma->vm_page_prot)) {
1244 ret = -EAGAIN;
1245 goto out;
1246 }
1247 vma->vm_flags &= ~VM_IO;
1248 db->mapped = 1;
1249 out:
1250 up(&s->sem);
1251 unlock_kernel();
1252 return ret;
1253 }
1254
1255
1256 #ifdef AU1000_VERBOSE_DEBUG
1257 static struct ioctl_str_t {
1258 unsigned int cmd;
1259 const char *str;
1260 } ioctl_str[] = {
1261 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1262 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1263 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1264 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1265 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1266 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1267 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1268 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1269 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1270 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1271 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1272 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1273 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1274 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1275 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1276 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1277 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1278 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1279 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1280 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1281 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1282 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1283 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1284 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1285 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1286 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1287 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1288 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1289 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1290 {OSS_GETVERSION, "OSS_GETVERSION"},
1291 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1292 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1293 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1294 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1295 };
1296 #endif
1297
1298 static int
1299 dma_count_done(struct dmabuf *db)
1300 {
1301 if (db->stopped)
1302 return 0;
1303
1304 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1305 }
1306
1307
1308 static int
1309 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1310 unsigned long arg)
1311 {
1312 struct au1550_state *s = (struct au1550_state *)file->private_data;
1313 unsigned long flags;
1314 audio_buf_info abinfo;
1315 count_info cinfo;
1316 int count;
1317 int val, mapped, ret, diff;
1318
1319 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1320 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1321
1322 #ifdef AU1000_VERBOSE_DEBUG
1323 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1324 if (ioctl_str[count].cmd == cmd)
1325 break;
1326 }
1327 if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1328 dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
1329 else
1330 dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
1331 #endif
1332
1333 switch (cmd) {
1334 case OSS_GETVERSION:
1335 return put_user(SOUND_VERSION, (int *) arg);
1336
1337 case SNDCTL_DSP_SYNC:
1338 if (file->f_mode & FMODE_WRITE)
1339 return drain_dac(s, file->f_flags & O_NONBLOCK);
1340 return 0;
1341
1342 case SNDCTL_DSP_SETDUPLEX:
1343 return 0;
1344
1345 case SNDCTL_DSP_GETCAPS:
1346 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1347 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1348
1349 case SNDCTL_DSP_RESET:
1350 if (file->f_mode & FMODE_WRITE) {
1351 stop_dac(s);
1352 synchronize_irq();
1353 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1354 s->dma_dac.nextIn = s->dma_dac.nextOut =
1355 s->dma_dac.rawbuf;
1356 }
1357 if (file->f_mode & FMODE_READ) {
1358 stop_adc(s);
1359 synchronize_irq();
1360 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1361 s->dma_adc.nextIn = s->dma_adc.nextOut =
1362 s->dma_adc.rawbuf;
1363 }
1364 return 0;
1365
1366 case SNDCTL_DSP_SPEED:
1367 if (get_user(val, (int *) arg))
1368 return -EFAULT;
1369 if (val >= 0) {
1370 if (file->f_mode & FMODE_READ) {
1371 stop_adc(s);
1372 set_adc_rate(s, val);
1373 }
1374 if (file->f_mode & FMODE_WRITE) {
1375 stop_dac(s);
1376 set_dac_rate(s, val);
1377 }
1378 if (s->open_mode & FMODE_READ)
1379 if ((ret = prog_dmabuf_adc(s)))
1380 return ret;
1381 if (s->open_mode & FMODE_WRITE)
1382 if ((ret = prog_dmabuf_dac(s)))
1383 return ret;
1384 }
1385 return put_user((file->f_mode & FMODE_READ) ?
1386 s->dma_adc.sample_rate :
1387 s->dma_dac.sample_rate,
1388 (int *)arg);
1389
1390 case SNDCTL_DSP_STEREO:
1391 if (get_user(val, (int *) arg))
1392 return -EFAULT;
1393 if (file->f_mode & FMODE_READ) {
1394 stop_adc(s);
1395 s->dma_adc.num_channels = val ? 2 : 1;
1396 if ((ret = prog_dmabuf_adc(s)))
1397 return ret;
1398 }
1399 if (file->f_mode & FMODE_WRITE) {
1400 stop_dac(s);
1401 s->dma_dac.num_channels = val ? 2 : 1;
1402 if ((ret = prog_dmabuf_dac(s)))
1403 return ret;
1404 }
1405 return 0;
1406
1407 case SNDCTL_DSP_CHANNELS:
1408 if (get_user(val, (int *) arg))
1409 return -EFAULT;
1410 if (val != 0) {
1411 if (file->f_mode & FMODE_READ) {
1412 if (val < 0 || val > 2)
1413 return -EINVAL;
1414 stop_adc(s);
1415 s->dma_adc.num_channels = val;
1416 if ((ret = prog_dmabuf_adc(s)))
1417 return ret;
1418 }
1419 if (file->f_mode & FMODE_WRITE) {
1420 switch (val) {
1421 case 1:
1422 case 2:
1423 break;
1424 default:
1425 return -EINVAL;
1426 }
1427
1428 stop_dac(s);
1429 s->dma_dac.num_channels = val;
1430 if ((ret = prog_dmabuf_dac(s)))
1431 return ret;
1432 }
1433 }
1434 return put_user(val, (int *) arg);
1435
1436 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1437 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1438
1439 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1440 if (get_user(val, (int *) arg))
1441 return -EFAULT;
1442 if (val != AFMT_QUERY) {
1443 if (file->f_mode & FMODE_READ) {
1444 stop_adc(s);
1445 if (val == AFMT_S16_LE)
1446 s->dma_adc.sample_size = 16;
1447 else {
1448 val = AFMT_U8;
1449 s->dma_adc.sample_size = 8;
1450 }
1451 if ((ret = prog_dmabuf_adc(s)))
1452 return ret;
1453 }
1454 if (file->f_mode & FMODE_WRITE) {
1455 stop_dac(s);
1456 if (val == AFMT_S16_LE)
1457 s->dma_dac.sample_size = 16;
1458 else {
1459 val = AFMT_U8;
1460 s->dma_dac.sample_size = 8;
1461 }
1462 if ((ret = prog_dmabuf_dac(s)))
1463 return ret;
1464 }
1465 } else {
1466 if (file->f_mode & FMODE_READ)
1467 val = (s->dma_adc.sample_size == 16) ?
1468 AFMT_S16_LE : AFMT_U8;
1469 else
1470 val = (s->dma_dac.sample_size == 16) ?
1471 AFMT_S16_LE : AFMT_U8;
1472 }
1473 return put_user(val, (int *) arg);
1474
1475 case SNDCTL_DSP_POST:
1476 return 0;
1477
1478 case SNDCTL_DSP_GETTRIGGER:
1479 val = 0;
1480 spin_lock_irqsave(&s->lock, flags);
1481 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1482 val |= PCM_ENABLE_INPUT;
1483 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1484 val |= PCM_ENABLE_OUTPUT;
1485 spin_unlock_irqrestore(&s->lock, flags);
1486 return put_user(val, (int *) arg);
1487
1488 case SNDCTL_DSP_SETTRIGGER:
1489 if (get_user(val, (int *) arg))
1490 return -EFAULT;
1491 if (file->f_mode & FMODE_READ) {
1492 if (val & PCM_ENABLE_INPUT)
1493 start_adc(s);
1494 else
1495 stop_adc(s);
1496 }
1497 if (file->f_mode & FMODE_WRITE) {
1498 if (val & PCM_ENABLE_OUTPUT)
1499 start_dac(s);
1500 else
1501 stop_dac(s);
1502 }
1503 return 0;
1504
1505 case SNDCTL_DSP_GETOSPACE:
1506 if (!(file->f_mode & FMODE_WRITE))
1507 return -EINVAL;
1508 abinfo.fragsize = s->dma_dac.fragsize;
1509 spin_lock_irqsave(&s->lock, flags);
1510 count = s->dma_dac.count;
1511 count -= dma_count_done(&s->dma_dac);
1512 spin_unlock_irqrestore(&s->lock, flags);
1513 if (count < 0)
1514 count = 0;
1515 abinfo.bytes = (s->dma_dac.dmasize - count) /
1516 s->dma_dac.cnt_factor;
1517 abinfo.fragstotal = s->dma_dac.numfrag;
1518 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1519 #ifdef AU1000_VERBOSE_DEBUG
1520 dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
1521 #endif
1522 return copy_to_user((void *) arg, &abinfo,
1523 sizeof(abinfo)) ? -EFAULT : 0;
1524
1525 case SNDCTL_DSP_GETISPACE:
1526 if (!(file->f_mode & FMODE_READ))
1527 return -EINVAL;
1528 abinfo.fragsize = s->dma_adc.fragsize;
1529 spin_lock_irqsave(&s->lock, flags);
1530 count = s->dma_adc.count;
1531 count += dma_count_done(&s->dma_adc);
1532 spin_unlock_irqrestore(&s->lock, flags);
1533 if (count < 0)
1534 count = 0;
1535 abinfo.bytes = count / s->dma_adc.cnt_factor;
1536 abinfo.fragstotal = s->dma_adc.numfrag;
1537 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1538 return copy_to_user((void *) arg, &abinfo,
1539 sizeof(abinfo)) ? -EFAULT : 0;
1540
1541 case SNDCTL_DSP_NONBLOCK:
1542 file->f_flags |= O_NONBLOCK;
1543 return 0;
1544
1545 case SNDCTL_DSP_GETODELAY:
1546 if (!(file->f_mode & FMODE_WRITE))
1547 return -EINVAL;
1548 spin_lock_irqsave(&s->lock, flags);
1549 count = s->dma_dac.count;
1550 count -= dma_count_done(&s->dma_dac);
1551 spin_unlock_irqrestore(&s->lock, flags);
1552 if (count < 0)
1553 count = 0;
1554 count /= s->dma_dac.cnt_factor;
1555 return put_user(count, (int *) arg);
1556
1557 case SNDCTL_DSP_GETIPTR:
1558 if (!(file->f_mode & FMODE_READ))
1559 return -EINVAL;
1560 spin_lock_irqsave(&s->lock, flags);
1561 cinfo.bytes = s->dma_adc.total_bytes;
1562 count = s->dma_adc.count;
1563 if (!s->dma_adc.stopped) {
1564 diff = dma_count_done(&s->dma_adc);
1565 count += diff;
1566 cinfo.bytes += diff;
1567 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1568 virt_to_phys(s->dma_adc.rawbuf);
1569 } else
1570 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1571 virt_to_phys(s->dma_adc.rawbuf);
1572 if (s->dma_adc.mapped)
1573 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1574 spin_unlock_irqrestore(&s->lock, flags);
1575 if (count < 0)
1576 count = 0;
1577 cinfo.blocks = count >> s->dma_adc.fragshift;
1578 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1579
1580 case SNDCTL_DSP_GETOPTR:
1581 if (!(file->f_mode & FMODE_READ))
1582 return -EINVAL;
1583 spin_lock_irqsave(&s->lock, flags);
1584 cinfo.bytes = s->dma_dac.total_bytes;
1585 count = s->dma_dac.count;
1586 if (!s->dma_dac.stopped) {
1587 diff = dma_count_done(&s->dma_dac);
1588 count -= diff;
1589 cinfo.bytes += diff;
1590 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1591 virt_to_phys(s->dma_dac.rawbuf);
1592 } else
1593 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1594 virt_to_phys(s->dma_dac.rawbuf);
1595 if (s->dma_dac.mapped)
1596 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1597 spin_unlock_irqrestore(&s->lock, flags);
1598 if (count < 0)
1599 count = 0;
1600 cinfo.blocks = count >> s->dma_dac.fragshift;
1601 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1602
1603 case SNDCTL_DSP_GETBLKSIZE:
1604 if (file->f_mode & FMODE_WRITE)
1605 return put_user(s->dma_dac.fragsize, (int *) arg);
1606 else
1607 return put_user(s->dma_adc.fragsize, (int *) arg);
1608
1609 case SNDCTL_DSP_SETFRAGMENT:
1610 if (get_user(val, (int *) arg))
1611 return -EFAULT;
1612 if (file->f_mode & FMODE_READ) {
1613 stop_adc(s);
1614 s->dma_adc.ossfragshift = val & 0xffff;
1615 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1616 if (s->dma_adc.ossfragshift < 4)
1617 s->dma_adc.ossfragshift = 4;
1618 if (s->dma_adc.ossfragshift > 15)
1619 s->dma_adc.ossfragshift = 15;
1620 if (s->dma_adc.ossmaxfrags < 4)
1621 s->dma_adc.ossmaxfrags = 4;
1622 if ((ret = prog_dmabuf_adc(s)))
1623 return ret;
1624 }
1625 if (file->f_mode & FMODE_WRITE) {
1626 stop_dac(s);
1627 s->dma_dac.ossfragshift = val & 0xffff;
1628 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1629 if (s->dma_dac.ossfragshift < 4)
1630 s->dma_dac.ossfragshift = 4;
1631 if (s->dma_dac.ossfragshift > 15)
1632 s->dma_dac.ossfragshift = 15;
1633 if (s->dma_dac.ossmaxfrags < 4)
1634 s->dma_dac.ossmaxfrags = 4;
1635 if ((ret = prog_dmabuf_dac(s)))
1636 return ret;
1637 }
1638 return 0;
1639
1640 case SNDCTL_DSP_SUBDIVIDE:
1641 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1642 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1643 return -EINVAL;
1644 if (get_user(val, (int *) arg))
1645 return -EFAULT;
1646 if (val != 1 && val != 2 && val != 4)
1647 return -EINVAL;
1648 if (file->f_mode & FMODE_READ) {
1649 stop_adc(s);
1650 s->dma_adc.subdivision = val;
1651 if ((ret = prog_dmabuf_adc(s)))
1652 return ret;
1653 }
1654 if (file->f_mode & FMODE_WRITE) {
1655 stop_dac(s);
1656 s->dma_dac.subdivision = val;
1657 if ((ret = prog_dmabuf_dac(s)))
1658 return ret;
1659 }
1660 return 0;
1661
1662 case SOUND_PCM_READ_RATE:
1663 return put_user((file->f_mode & FMODE_READ) ?
1664 s->dma_adc.sample_rate :
1665 s->dma_dac.sample_rate,
1666 (int *)arg);
1667
1668 case SOUND_PCM_READ_CHANNELS:
1669 if (file->f_mode & FMODE_READ)
1670 return put_user(s->dma_adc.num_channels, (int *)arg);
1671 else
1672 return put_user(s->dma_dac.num_channels, (int *)arg);
1673
1674 case SOUND_PCM_READ_BITS:
1675 if (file->f_mode & FMODE_READ)
1676 return put_user(s->dma_adc.sample_size, (int *)arg);
1677 else
1678 return put_user(s->dma_dac.sample_size, (int *)arg);
1679
1680 case SOUND_PCM_WRITE_FILTER:
1681 case SNDCTL_DSP_SETSYNCRO:
1682 case SOUND_PCM_READ_FILTER:
1683 return -EINVAL;
1684 }
1685
1686 return 0;
1687 }
1688
1689
1690 static int
1691 au1550_open(struct inode *inode, struct file *file)
1692 {
1693 int minor = MINOR(inode->i_rdev);
1694 DECLARE_WAITQUEUE(wait, current);
1695 struct au1550_state *s = &au1550_state;
1696 int ret;
1697
1698 #ifdef AU1000_VERBOSE_DEBUG
1699 if (file->f_flags & O_NONBLOCK)
1700 dbg(__FUNCTION__ ": non-blocking");
1701 else
1702 dbg(__FUNCTION__ ": blocking");
1703 #endif
1704
1705 file->private_data = s;
1706 /* wait for device to become free */
1707 down(&s->open_sem);
1708 while (s->open_mode & file->f_mode) {
1709 if (file->f_flags & O_NONBLOCK) {
1710 up(&s->open_sem);
1711 return -EBUSY;
1712 }
1713 add_wait_queue(&s->open_wait, &wait);
1714 __set_current_state(TASK_INTERRUPTIBLE);
1715 up(&s->open_sem);
1716 schedule();
1717 remove_wait_queue(&s->open_wait, &wait);
1718 set_current_state(TASK_RUNNING);
1719 if (signal_pending(current))
1720 return -ERESTARTSYS;
1721 down(&s->open_sem);
1722 }
1723
1724 stop_dac(s);
1725 stop_adc(s);
1726
1727 if (file->f_mode & FMODE_READ) {
1728 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1729 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1730 s->dma_adc.num_channels = 1;
1731 s->dma_adc.sample_size = 8;
1732 set_adc_rate(s, 8000);
1733 if ((minor & 0xf) == SND_DEV_DSP16)
1734 s->dma_adc.sample_size = 16;
1735 }
1736
1737 if (file->f_mode & FMODE_WRITE) {
1738 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1739 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1740 s->dma_dac.num_channels = 1;
1741 s->dma_dac.sample_size = 8;
1742 set_dac_rate(s, 8000);
1743 if ((minor & 0xf) == SND_DEV_DSP16)
1744 s->dma_dac.sample_size = 16;
1745 }
1746
1747 if (file->f_mode & FMODE_READ) {
1748 if ((ret = prog_dmabuf_adc(s)))
1749 return ret;
1750 }
1751 if (file->f_mode & FMODE_WRITE) {
1752 if ((ret = prog_dmabuf_dac(s)))
1753 return ret;
1754 }
1755
1756 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1757 up(&s->open_sem);
1758 init_MUTEX(&s->sem);
1759 return 0;
1760 }
1761
1762 static int
1763 au1550_release(struct inode *inode, struct file *file)
1764 {
1765 struct au1550_state *s = (struct au1550_state *)file->private_data;
1766
1767 lock_kernel();
1768
1769 if (file->f_mode & FMODE_WRITE) {
1770 unlock_kernel();
1771 drain_dac(s, file->f_flags & O_NONBLOCK);
1772 lock_kernel();
1773 }
1774
1775 down(&s->open_sem);
1776 if (file->f_mode & FMODE_WRITE) {
1777 stop_dac(s);
1778 kfree(s->dma_dac.rawbuf);
1779 s->dma_dac.rawbuf = NULL;
1780 }
1781 if (file->f_mode & FMODE_READ) {
1782 stop_adc(s);
1783 kfree(s->dma_adc.rawbuf);
1784 s->dma_adc.rawbuf = NULL;
1785 }
1786 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1787 up(&s->open_sem);
1788 wake_up(&s->open_wait);
1789 unlock_kernel();
1790 return 0;
1791 }
1792
1793 static struct file_operations au1550_audio_fops = {
1794 owner: THIS_MODULE,
1795 llseek: au1550_llseek,
1796 read: au1550_read,
1797 write: au1550_write,
1798 poll: au1550_poll,
1799 ioctl: au1550_ioctl,
1800 mmap: au1550_mmap,
1801 open: au1550_open,
1802 release: au1550_release,
1803 };
1804
1805 /* Set up an internal clock for the PSC3. This will then get
1806 * driven out of the Au1550 as the master.
1807 */
1808 static void
1809 intclk_setup(void)
1810 {
1811 uint clk, rate;
1812
1813 /* Wire up Freq4 as a clock for the PSC3.
1814 * We know SMBus uses Freq3.
1815 * By making changes to this rate, plus the word strobe
1816 * size, we can make fine adjustments to the actual data rate.
1817 */
1818 rate = get_au1x00_speed();
1819 #ifdef TRY_441KHz
1820 rate /= (11 * 1000000);
1821 #else
1822 rate /= (12 * 1000000);
1823 #endif
1824
1825 /* The FRDIV in the frequency control is (FRDIV + 1) * 2
1826 */
1827 rate /=2;
1828 rate--;
1829 clk = au_readl(SYS_FREQCTRL1);
1830 au_sync();
1831 clk &= ~(SYS_FC_FRDIV4_MASK | SYS_FC_FS4);;
1832 clk |= (rate << SYS_FC_FRDIV4_BIT);
1833 clk |= SYS_FC_FE4;
1834 au_writel(clk, SYS_FREQCTRL1);
1835 au_sync();
1836
1837 /* Set up the clock source routing to get Freq4 to PSC3_intclk.
1838 */
1839 clk = au_readl(SYS_CLKSRC);
1840 au_sync();
1841 clk &= ~0x01f00000;
1842 clk |= (6 << 22);
1843 au_writel(clk, SYS_CLKSRC);
1844 au_sync();
1845 }
1846
1847 static int __devinit
1848 au1550_probe(void)
1849 {
1850 struct au1550_state *s = &au1550_state;
1851 int val;
1852 volatile psc_i2s_t *ip;
1853 #ifdef AU1550_DEBUG
1854 char proc_str[80];
1855 #endif
1856
1857 memset(s, 0, sizeof(struct au1550_state));
1858
1859 init_waitqueue_head(&s->dma_adc.wait);
1860 init_waitqueue_head(&s->dma_dac.wait);
1861 init_waitqueue_head(&s->open_wait);
1862 init_MUTEX(&s->open_sem);
1863 spin_lock_init(&s->lock);
1864
1865 s->codec = &au1550_i2s_codec;
1866 s->psc_addr = (volatile psc_i2s_t *)I2S_PSC_BASE;
1867 ip = s->psc_addr;
1868
1869 if (!request_region(CPHYSADDR(ip),
1870 0x30, AU1550_MODULE_NAME)) {
1871 pr_error("I2S Audio ports in use");
1872 }
1873
1874 /* Allocate the DMA Channels
1875 */
1876 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1877 DBDMA_I2S_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1878 pr_error("Can't get DAC DMA");
1879 goto err_dma1;
1880 }
1881 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1882 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1883 NUM_DBDMA_DESCRIPTORS) == 0) {
1884 pr_error("Can't get DAC DMA descriptors");
1885 goto err_dma1;
1886 }
1887
1888 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_I2S_RX_CHAN,
1889 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1890 pr_error("Can't get ADC DMA");
1891 goto err_dma2;
1892 }
1893 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1894 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1895 NUM_DBDMA_DESCRIPTORS) == 0) {
1896 pr_error("Can't get ADC DMA descriptors");
1897 goto err_dma2;
1898 }
1899
1900 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_I2S_TX_CHAN, DBDMA_I2S_RX_CHAN);
1901
1902 /* register devices */
1903
1904 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1905 goto err_dev1;
1906
1907 if ((s->dev_mixer = register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1908 goto err_dev2;
1909
1910 #ifdef AU1550_DEBUG
1911 /* intialize the debug proc device */
1912 s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
1913 proc_au1550_dump, NULL);
1914 #endif /* AU1550_DEBUG */
1915
1916 intclk_setup();
1917
1918 /* The GPIO for the appropriate PSC was configured by the
1919 * board specific start up.
1920 *
1921 * configure PSC for I2S Audio
1922 */
1923 ip->psc_ctrl = PSC_CTRL_DISABLE; /* Disable PSC */
1924 au_sync();
1925 ip->psc_sel = (PSC_SEL_CLK_INTCLK | PSC_SEL_PS_I2SMODE);
1926 au_sync();
1927
1928 /* Enable PSC
1929 */
1930 ip->psc_ctrl = PSC_CTRL_ENABLE;
1931 au_sync();
1932
1933 /* Wait for PSC ready.
1934 */
1935 do {
1936 val = ip->psc_i2sstat;
1937 au_sync();
1938 } while ((val & PSC_I2SSTAT_SR) == 0);
1939
1940 /* Configure I2S controller.
1941 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
1942 * Actual I2S mode (first bit delayed by one clock).
1943 * Master mode (We provide the clock from the PSC).
1944 */
1945 val = PSC_I2SCFG_SET_LEN(16);
1946 #ifdef TRY_441KHz
1947 /* This really should be 250, but it appears that all of the
1948 * PLLs, dividers and so on in the chain shift it. That's the
1949 * problem with sourceing the clock instead of letting the very
1950 * stable codec provide it. But, the PSC doesn't appear to want
1951 * to work in slave mode, so this is what we get. It's not
1952 * studio quality timing, but it's good enough for listening
1953 * to mp3s.
1954 */
1955 val |= PSC_I2SCFG_SET_WS(252);
1956 #else
1957 val |= PSC_I2SCFG_SET_WS(250);
1958 #endif
1959 val |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \
1960 PSC_I2SCFG_BI | PSC_I2SCFG_XM;
1961
1962 ip->psc_i2scfg = val;
1963 au_sync();
1964 val |= PSC_I2SCFG_DE_ENABLE;
1965 ip->psc_i2scfg = val;
1966 au_sync();
1967
1968 /* Wait for Device ready.
1969 */
1970 do {
1971 val = ip->psc_i2sstat;
1972 au_sync();
1973 } while ((val & PSC_I2SSTAT_DR) == 0);
1974
1975 val = ip->psc_i2scfg;
1976 au_sync();
1977
1978 s->codec->init_codec(s->codec);
1979
1980 return 0;
1981
1982 err_dev2:
1983 unregister_sound_dsp(s->dev_audio);
1984 err_dev1:
1985 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
1986 err_dma2:
1987 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
1988 err_dma1:
1989 release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
1990
1991 return -1;
1992 }
1993
1994 static void __devinit
1995 au1550_remove(void)
1996 {
1997 struct au1550_state *s = &au1550_state;
1998
1999 if (!s)
2000 return;
2001 #ifdef AU1550_DEBUG
2002 if (s->ps)
2003 remove_proc_entry(AU1000_MODULE_NAME, NULL);
2004 #endif /* AU1000_DEBUG */
2005 synchronize_irq();
2006 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2007 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2008 release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
2009 unregister_sound_dsp(s->dev_audio);
2010 unregister_sound_mixer(s->dev_mixer);
2011 }
2012
2013 static int __init
2014 init_au1550(void)
2015 {
2016 return au1550_probe();
2017 }
2018
2019 static void __exit
2020 cleanup_au1550(void)
2021 {
2022 au1550_remove();
2023 }
2024
2025 module_init(init_au1550);
2026 module_exit(cleanup_au1550);
2027
2028 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
2029 MODULE_DESCRIPTION("Au1550 I2S Audio Driver");
Tomato firmware and modifications.