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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / asm-frv / system.h
blob6931af525da3201873274337a993d342d2c9b14b
1 /* system.h: FR-V CPU control definitions
2 *
3 * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef _ASM_SYSTEM_H
13 #define _ASM_SYSTEM_H
14
15 #include <linux/types.h>
16 #include <linux/linkage.h>
17
18 struct thread_struct;
19
20 /*
21 * switch_to(prev, next) should switch from task `prev' to `next'
22 * `prev' will never be the same as `next'.
23 * The `mb' is to tell GCC not to cache `current' across this call.
24 */
25 extern asmlinkage
26 struct task_struct *__switch_to(struct thread_struct *prev_thread,
27 struct thread_struct *next_thread,
28 struct task_struct *prev);
29
30 #define switch_to(prev, next, last) \
31 do { \
32 (prev)->thread.sched_lr = \
33 (unsigned long) __builtin_return_address(0); \
34 (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
35 mb(); \
36 } while(0)
37
38 /*
39 * interrupt flag manipulation
40 * - use virtual interrupt management since touching the PSR is slow
41 * - ICC2.Z: T if interrupts virtually disabled
42 * - ICC2.C: F if interrupts really disabled
43 * - if Z==1 upon interrupt:
44 * - C is set to 0
45 * - interrupts are really disabled
46 * - entry.S returns immediately
47 * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
48 * - if taken, the trap:
49 * - sets ICC2.C
50 * - enables interrupts
51 */
52 #define local_irq_disable() \
53 do { \
54 /* set Z flag, but don't change the C flag */ \
55 asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
56 : \
57 : \
58 : "memory", "icc2" \
59 ); \
60 } while(0)
61
62 #define local_irq_enable() \
63 do { \
64 /* clear Z flag and then test the C flag */ \
65 asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
66 " tihi icc2,gr0,#2 \n" \
67 : \
68 : \
69 : "memory", "icc2" \
70 ); \
71 } while(0)
72
73 #define local_save_flags(flags) \
74 do { \
75 typecheck(unsigned long, flags); \
76 asm volatile("movsg ccr,%0" \
77 : "=r"(flags) \
78 : \
79 : "memory"); \
80 \
81 /* shift ICC2.Z to bit 0 */ \
82 flags >>= 26; \
83 \
84 /* make flags 1 if interrupts disabled, 0 otherwise */ \
85 flags &= 1UL; \
86 } while(0)
87
88 #define irqs_disabled() \
89 ({unsigned long flags; local_save_flags(flags); flags; })
90
91 #define local_irq_save(flags) \
92 do { \
93 typecheck(unsigned long, flags); \
94 local_save_flags(flags); \
95 local_irq_disable(); \
96 } while(0)
97
98 #define local_irq_restore(flags) \
99 do { \
100 typecheck(unsigned long, flags); \
101 \
102 /* load the Z flag by turning 1 if disabled into 0 if disabled \
103 * and thus setting the Z flag but not the C flag */ \
104 asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
105 /* then test Z=0 and C=0 */ \
106 " tihi icc2,gr0,#2 \n" \
107 : \
108 : "r"(flags) \
109 : "memory", "icc2" \
110 ); \
111 \
112 } while(0)
113
114 /*
115 * real interrupt flag manipulation
116 */
117 #define __local_irq_disable() \
118 do { \
119 unsigned long psr; \
120 asm volatile(" movsg psr,%0 \n" \
121 " andi %0,%2,%0 \n" \
122 " ori %0,%1,%0 \n" \
123 " movgs %0,psr \n" \
124 : "=r"(psr) \
125 : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
126 : "memory"); \
127 } while(0)
128
129 #define __local_irq_enable() \
130 do { \
131 unsigned long psr; \
132 asm volatile(" movsg psr,%0 \n" \
133 " andi %0,%1,%0 \n" \
134 " movgs %0,psr \n" \
135 : "=r"(psr) \
136 : "i" (~PSR_PIL) \
137 : "memory"); \
138 } while(0)
139
140 #define __local_save_flags(flags) \
141 do { \
142 typecheck(unsigned long, flags); \
143 asm("movsg psr,%0" \
144 : "=r"(flags) \
145 : \
146 : "memory"); \
147 } while(0)
148
149 #define __local_irq_save(flags) \
150 do { \
151 unsigned long npsr; \
152 typecheck(unsigned long, flags); \
153 asm volatile(" movsg psr,%0 \n" \
154 " andi %0,%3,%1 \n" \
155 " ori %1,%2,%1 \n" \
156 " movgs %1,psr \n" \
157 : "=r"(flags), "=r"(npsr) \
158 : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
159 : "memory"); \
160 } while(0)
161
162 #define __local_irq_restore(flags) \
163 do { \
164 typecheck(unsigned long, flags); \
165 asm volatile(" movgs %0,psr \n" \
166 : \
167 : "r" (flags) \
168 : "memory"); \
169 } while(0)
170
171 #define __irqs_disabled() \
172 ((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
173
174 /*
175 * Force strict CPU ordering.
176 */
177 #define nop() asm volatile ("nop"::)
178 #define mb() asm volatile ("membar" : : :"memory")
179 #define rmb() asm volatile ("membar" : : :"memory")
180 #define wmb() asm volatile ("membar" : : :"memory")
181 #define set_mb(var, value) do { var = value; mb(); } while (0)
182
183 #define smp_mb() mb()
184 #define smp_rmb() rmb()
185 #define smp_wmb() wmb()
186
187 #define read_barrier_depends() do {} while(0)
188 #define smp_read_barrier_depends() read_barrier_depends()
189
190 #define HARD_RESET_NOW() \
191 do { \
192 cli(); \
193 } while(1)
194
195 extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
196 extern void free_initmem(void);
197
198 #define arch_align_stack(x) (x)
199
200 /*****************************************************************************/
201 /*
202 * compare and conditionally exchange value with memory
203 * - if (*ptr == test) then orig = *ptr; *ptr = test;
204 * - if (*ptr != test) then orig = *ptr;
205 */
206 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
207
208 #define cmpxchg(ptr, test, new) \
209 ({ \
210 __typeof__(ptr) __xg_ptr = (ptr); \
211 __typeof__(*(ptr)) __xg_orig, __xg_tmp; \
212 __typeof__(*(ptr)) __xg_test = (test); \
213 __typeof__(*(ptr)) __xg_new = (new); \
214 \
215 switch (sizeof(__xg_orig)) { \
216 case 4: \
217 asm volatile( \
218 "0: \n" \
219 " orcc gr0,gr0,gr0,icc3 \n" \
220 " ckeq icc3,cc7 \n" \
221 " ld.p %M0,%1 \n" \
222 " orcr cc7,cc7,cc3 \n" \
223 " sub%I4cc %1,%4,%2,icc0 \n" \
224 " bne icc0,#0,1f \n" \
225 " cst.p %3,%M0 ,cc3,#1 \n" \
226 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
227 " beq icc3,#0,0b \n" \
228 "1: \n" \
229 : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
230 : "r"(__xg_new), "NPr"(__xg_test) \
231 : "memory", "cc7", "cc3", "icc3", "icc0" \
232 ); \
233 break; \
234 \
235 default: \
236 __xg_orig = 0; \
237 asm volatile("break"); \
238 break; \
239 } \
240 \
241 __xg_orig; \
242 })
243
244 #else
245
246 extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
247
248 #define cmpxchg(ptr, test, new) \
249 ({ \
250 __typeof__(ptr) __xg_ptr = (ptr); \
251 __typeof__(*(ptr)) __xg_orig; \
252 __typeof__(*(ptr)) __xg_test = (test); \
253 __typeof__(*(ptr)) __xg_new = (new); \
254 \
255 switch (sizeof(__xg_orig)) { \
256 case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
257 default: \
258 __xg_orig = 0; \
259 asm volatile("break"); \
260 break; \
261 } \
262 \
263 __xg_orig; \
264 })
265
266 #endif
267
268
269 #endif /* _ASM_SYSTEM_H */
Tomato firmware and modifications.