release/src-rt-6.x/linux/linux-2.6/include/asm-arm/hardware/iomd.h

   1 /*
   2  *  linux/include/asm-arm/hardware/iomd.h
   3  *
   4  *  Copyright (C) 1999 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This file contains information out the IOMD ASIC used in the
  11  *  Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
  12  */
  13 #ifndef __ASMARM_HARDWARE_IOMD_H
  14 #define __ASMARM_HARDWARE_IOMD_H
  15
  16
  17 #ifndef __ASSEMBLY__
  18
  19 /*
  20  * We use __raw_base variants here so that we give the compiler the
  21  * chance to keep IOC_BASE in a register.
  22  */
  23 #define iomd_readb(off)         __raw_readb(IOMD_BASE + (off))
  24 #define iomd_readl(off)         __raw_readl(IOMD_BASE + (off))
  25 #define iomd_writeb(val,off)    __raw_writeb(val, IOMD_BASE + (off))
  26 #define iomd_writel(val,off)    __raw_writel(val, IOMD_BASE + (off))
  27
  28 #endif
  29
  30 #define IOMD_CONTROL    (0x000)
  31 #define IOMD_KARTTX     (0x004)
  32 #define IOMD_KARTRX     (0x004)
  33 #define IOMD_KCTRL      (0x008)
  34
  35 #ifdef CONFIG_ARCH_CLPS7500
  36 #define IOMD_IOLINES    (0x00C)
  37 #endif
  38
  39 #define IOMD_IRQSTATA   (0x010)
  40 #define IOMD_IRQREQA    (0x014)
  41 #define IOMD_IRQCLRA    (0x014)
  42 #define IOMD_IRQMASKA   (0x018)
  43
  44 #ifdef CONFIG_ARCH_CLPS7500
  45 #define IOMD_SUSMODE    (0x01C)
  46 #endif
  47
  48 #define IOMD_IRQSTATB   (0x020)
  49 #define IOMD_IRQREQB    (0x024)
  50 #define IOMD_IRQMASKB   (0x028)
  51
  52 #define IOMD_FIQSTAT    (0x030)
  53 #define IOMD_FIQREQ     (0x034)
  54 #define IOMD_FIQMASK    (0x038)
  55
  56 #ifdef CONFIG_ARCH_CLPS7500
  57 #define IOMD_CLKCTL     (0x03C)
  58 #endif
  59
  60 #define IOMD_T0CNTL     (0x040)
  61 #define IOMD_T0LTCHL    (0x040)
  62 #define IOMD_T0CNTH     (0x044)
  63 #define IOMD_T0LTCHH    (0x044)
  64 #define IOMD_T0GO       (0x048)
  65 #define IOMD_T0LATCH    (0x04c)
  66
  67 #define IOMD_T1CNTL     (0x050)
  68 #define IOMD_T1LTCHL    (0x050)
  69 #define IOMD_T1CNTH     (0x054)
  70 #define IOMD_T1LTCHH    (0x054)
  71 #define IOMD_T1GO       (0x058)
  72 #define IOMD_T1LATCH    (0x05c)
  73
  74 #ifdef CONFIG_ARCH_CLPS7500
  75 #define IOMD_IRQSTATC   (0x060)
  76 #define IOMD_IRQREQC    (0x064)
  77 #define IOMD_IRQMASKC   (0x068)
  78
  79 #define IOMD_VIDMUX     (0x06c)
  80
  81 #define IOMD_IRQSTATD   (0x070)
  82 #define IOMD_IRQREQD    (0x074)
  83 #define IOMD_IRQMASKD   (0x078)
  84 #endif
  85
  86 #define IOMD_ROMCR0     (0x080)
  87 #define IOMD_ROMCR1     (0x084)
  88 #ifdef CONFIG_ARCH_RPC
  89 #define IOMD_DRAMCR     (0x088)
  90 #endif
  91 #define IOMD_REFCR      (0x08C)
  92
  93 #define IOMD_FSIZE      (0x090)
  94 #define IOMD_ID0        (0x094)
  95 #define IOMD_ID1        (0x098)
  96 #define IOMD_VERSION    (0x09C)
  97
  98 #ifdef CONFIG_ARCH_RPC
  99 #define IOMD_MOUSEX     (0x0A0)
 100 #define IOMD_MOUSEY     (0x0A4)
 101 #endif
 102
 103 #ifdef CONFIG_ARCH_CLPS7500
 104 #define IOMD_MSEDAT     (0x0A8)
 105 #define IOMD_MSECTL     (0x0Ac)
 106 #endif
 107
 108 #ifdef CONFIG_ARCH_RPC
 109 #define IOMD_DMATCR     (0x0C0)
 110 #endif
 111 #define IOMD_IOTCR      (0x0C4)
 112 #define IOMD_ECTCR      (0x0C8)
 113 #ifdef CONFIG_ARCH_RPC
 114 #define IOMD_DMAEXT     (0x0CC)
 115 #endif
 116 #ifdef CONFIG_ARCH_CLPS7500
 117 #define IOMD_ASTCR      (0x0CC)
 118 #define IOMD_DRAMCR     (0x0D0)
 119 #define IOMD_SELFREF    (0x0D4)
 120 #define IOMD_ATODICR    (0x0E0)
 121 #define IOMD_ATODSR     (0x0E4)
 122 #define IOMD_ATODCC     (0x0E8)
 123 #define IOMD_ATODCNT1   (0x0EC)
 124 #define IOMD_ATODCNT2   (0x0F0)
 125 #define IOMD_ATODCNT3   (0x0F4)
 126 #define IOMD_ATODCNT4   (0x0F8)
 127 #endif
 128
 129 #ifdef CONFIG_ARCH_RPC
 130 #define DMA_EXT_IO0     1
 131 #define DMA_EXT_IO1     2
 132 #define DMA_EXT_IO2     4
 133 #define DMA_EXT_IO3     8
 134
 135 #define IOMD_IO0CURA    (0x100)
 136 #define IOMD_IO0ENDA    (0x104)
 137 #define IOMD_IO0CURB    (0x108)
 138 #define IOMD_IO0ENDB    (0x10C)
 139 #define IOMD_IO0CR      (0x110)
 140 #define IOMD_IO0ST      (0x114)
 141
 142 #define IOMD_IO1CURA    (0x120)
 143 #define IOMD_IO1ENDA    (0x124)
 144 #define IOMD_IO1CURB    (0x128)
 145 #define IOMD_IO1ENDB    (0x12C)
 146 #define IOMD_IO1CR      (0x130)
 147 #define IOMD_IO1ST      (0x134)
 148
 149 #define IOMD_IO2CURA    (0x140)
 150 #define IOMD_IO2ENDA    (0x144)
 151 #define IOMD_IO2CURB    (0x148)
 152 #define IOMD_IO2ENDB    (0x14C)
 153 #define IOMD_IO2CR      (0x150)
 154 #define IOMD_IO2ST      (0x154)
 155
 156 #define IOMD_IO3CURA    (0x160)
 157 #define IOMD_IO3ENDA    (0x164)
 158 #define IOMD_IO3CURB    (0x168)
 159 #define IOMD_IO3ENDB    (0x16C)
 160 #define IOMD_IO3CR      (0x170)
 161 #define IOMD_IO3ST      (0x174)
 162 #endif
 163
 164 #define IOMD_SD0CURA    (0x180)
 165 #define IOMD_SD0ENDA    (0x184)
 166 #define IOMD_SD0CURB    (0x188)
 167 #define IOMD_SD0ENDB    (0x18C)
 168 #define IOMD_SD0CR      (0x190)
 169 #define IOMD_SD0ST      (0x194)
 170
 171 #ifdef CONFIG_ARCH_RPC
 172 #define IOMD_SD1CURA    (0x1A0)
 173 #define IOMD_SD1ENDA    (0x1A4)
 174 #define IOMD_SD1CURB    (0x1A8)
 175 #define IOMD_SD1ENDB    (0x1AC)
 176 #define IOMD_SD1CR      (0x1B0)
 177 #define IOMD_SD1ST      (0x1B4)
 178 #endif
 179
 180 #define IOMD_CURSCUR    (0x1C0)
 181 #define IOMD_CURSINIT   (0x1C4)
 182
 183 #define IOMD_VIDCUR     (0x1D0)
 184 #define IOMD_VIDEND     (0x1D4)
 185 #define IOMD_VIDSTART   (0x1D8)
 186 #define IOMD_VIDINIT    (0x1DC)
 187 #define IOMD_VIDCR      (0x1E0)
 188
 189 #define IOMD_DMASTAT    (0x1F0)
 190 #define IOMD_DMAREQ     (0x1F4)
 191 #define IOMD_DMAMASK    (0x1F8)
 192
 193 #define DMA_END_S       (1 << 31)
 194 #define DMA_END_L       (1 << 30)
 195
 196 #define DMA_CR_C        0x80
 197 #define DMA_CR_D        0x40
 198 #define DMA_CR_E        0x20
 199
 200 #define DMA_ST_OFL      4
 201 #define DMA_ST_INT      2
 202 #define DMA_ST_AB       1
 203
 204 /*
 205  * DMA (MEMC) compatibility
 206  */
 207 #define HALF_SAM        vram_half_sam
 208 #define VDMA_ALIGNMENT  (HALF_SAM * 2)
 209 #define VDMA_XFERSIZE   (HALF_SAM)
 210 #define VDMA_INIT       IOMD_VIDINIT
 211 #define VDMA_START      IOMD_VIDSTART
 212 #define VDMA_END        IOMD_VIDEND
 213
 214 #ifndef __ASSEMBLY__
 215 extern unsigned int vram_half_sam;
 216 #define video_set_dma(start,end,offset)                         \
 217 do {                                                            \
 218         outl (SCREEN_START + start, VDMA_START);                \
 219         outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END);    \
 220         if (offset >= end - VDMA_XFERSIZE)                      \
 221                 offset |= 0x40000000;                           \
 222         outl (SCREEN_START + offset, VDMA_INIT);                \
 223 } while (0)
 224 #endif
 225
 226 #endif