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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / serial / sh-sci.c
blob1f89496d530e405db3f11d6d0f52eaaaed34ae5f
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42
43 #ifdef CONFIG_CPU_FREQ
44 #include <linux/notifier.h>
45 #include <linux/cpufreq.h>
46 #endif
47
48 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
49 #include <linux/ctype.h>
50 #include <asm/clock.h>
51 #include <asm/sh_bios.h>
52 #include <asm/kgdb.h>
53 #endif
54
55 #include <asm/sci.h>
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
82 /* Port clock */
83 struct clk *clk;
84 #endif
85 };
86
87 #ifdef CONFIG_SH_KGDB
88 static struct sci_port *kgdb_sci_port;
89 #endif
90
91 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
92 static struct sci_port *serial_console_port;
93 #endif
94
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port *port);
97
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
99
100 static struct sci_port sci_ports[SCI_NPORTS];
101 static struct uart_driver sci_uart_driver;
102
103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
104 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
105 static inline void handle_error(struct uart_port *port)
106 {
107 /* Clear error flags */
108 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
109 }
110
111 static int get_char(struct uart_port *port)
112 {
113 unsigned long flags;
114 unsigned short status;
115 int c;
116
117 spin_lock_irqsave(&port->lock, flags);
118 do {
119 status = sci_in(port, SCxSR);
120 if (status & SCxSR_ERRORS(port)) {
121 handle_error(port);
122 continue;
123 }
124 } while (!(status & SCxSR_RDxF(port)));
125 c = sci_in(port, SCxRDR);
126 sci_in(port, SCxSR); /* Dummy read */
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128 spin_unlock_irqrestore(&port->lock, flags);
129
130 return c;
131 }
132 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
133
134 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
135 static void put_char(struct uart_port *port, char c)
136 {
137 unsigned long flags;
138 unsigned short status;
139
140 spin_lock_irqsave(&port->lock, flags);
141
142 do {
143 status = sci_in(port, SCxSR);
144 } while (!(status & SCxSR_TDxE(port)));
145
146 sci_out(port, SCxTDR, c);
147 sci_in(port, SCxSR); /* Dummy read */
148 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
149
150 spin_unlock_irqrestore(&port->lock, flags);
151 }
152 #endif
153
154 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
155 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
156 {
157 struct uart_port *port = &sci_port->port;
158 const unsigned char *p = buffer;
159 int i;
160
161 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
162 int checksum;
163 int usegdb=0;
164
165 #ifdef CONFIG_SH_STANDARD_BIOS
166 /* This call only does a trap the first time it is
167 * called, and so is safe to do here unconditionally
168 */
169 usegdb |= sh_bios_in_gdb_mode();
170 #endif
171 #ifdef CONFIG_SH_KGDB
172 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
173 #endif
174
175 if (usegdb) {
176 /* $<packet info>#<checksum>. */
177 do {
178 unsigned char c;
179 put_char(port, '$');
180 put_char(port, 'O'); /* 'O'utput to console */
181 checksum = 'O';
182
183 for (i=0; i<count; i++) { /* Don't use run length encoding */
184 int h, l;
185
186 c = *p++;
187 h = highhex(c);
188 l = lowhex(c);
189 put_char(port, h);
190 put_char(port, l);
191 checksum += h + l;
192 }
193 put_char(port, '#');
194 put_char(port, highhex(checksum));
195 put_char(port, lowhex(checksum));
196 } while (get_char(port) != '+');
197 } else
198 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
199 for (i=0; i<count; i++) {
200 if (*p == 10)
201 put_char(port, '\r');
202 put_char(port, *p++);
203 }
204 }
205 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
206
207 #ifdef CONFIG_SH_KGDB
208 static int kgdb_sci_getchar(void)
209 {
210 int c;
211
212 /* Keep trying to read a character, this could be neater */
213 while ((c = get_char(&kgdb_sci_port->port)) < 0)
214 cpu_relax();
215
216 return c;
217 }
218
219 static inline void kgdb_sci_putchar(int c)
220 {
221 put_char(&kgdb_sci_port->port, c);
222 }
223 #endif /* CONFIG_SH_KGDB */
224
225 #if defined(__H8300S__)
226 enum { sci_disable, sci_enable };
227
228 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
229 {
230 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
231 int ch = (port->mapbase - SMR0) >> 3;
232 unsigned char mask = 1 << (ch+1);
233
234 if (ctrl == sci_disable) {
235 *mstpcrl |= mask;
236 } else {
237 *mstpcrl &= ~mask;
238 }
239 }
240
241 static inline void h8300_sci_enable(struct uart_port *port)
242 {
243 h8300_sci_config(port, sci_enable);
244 }
245
246 static inline void h8300_sci_disable(struct uart_port *port)
247 {
248 h8300_sci_config(port, sci_disable);
249 }
250 #endif
251
252 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
253 defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
255 {
256 int ch = (port->mapbase - SMR0) >> 3;
257
258 /* set DDR regs */
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].rx,
261 H8300_GPIO_INPUT);
262 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
263 h8300_sci_pins[ch].tx,
264 H8300_GPIO_OUTPUT);
265
266 /* tx mark output*/
267 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
268 }
269 #else
270 #define sci_init_pins_sci NULL
271 #endif
272
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
275 {
276 unsigned int fcr_val = 0;
277
278 if (cflag & CRTSCTS)
279 fcr_val |= SCFCR_MCE;
280
281 sci_out(port, SCFCR, fcr_val);
282 }
283 #else
284 #define sci_init_pins_irda NULL
285 #endif
286
287 #ifdef SCI_ONLY
288 #define sci_init_pins_scif NULL
289 #endif
290
291 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
293 /* SH7300 doesn't use RTS/CTS */
294 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
295 {
296 sci_out(port, SCFCR, 0);
297 }
298 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
299 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
300 {
301 unsigned int fcr_val = 0;
302
303 set_sh771x_scif_pfc(port);
304 if (cflag & CRTSCTS) {
305 fcr_val |= SCFCR_MCE;
306 }
307 sci_out(port, SCFCR, fcr_val);
308 }
309 #elif defined(CONFIG_CPU_SH3)
310 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
311 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
312 {
313 unsigned int fcr_val = 0;
314 unsigned short data;
315
316 /* We need to set SCPCR to enable RTS/CTS */
317 data = ctrl_inw(SCPCR);
318 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
319 ctrl_outw(data & 0x0fcf, SCPCR);
320
321 if (cflag & CRTSCTS)
322 fcr_val |= SCFCR_MCE;
323 else {
324 /* We need to set SCPCR to enable RTS/CTS */
325 data = ctrl_inw(SCPCR);
326 /* Clear out SCP7MD1,0, SCP4MD1,0,
327 Set SCP6MD1,0 = {01} (output) */
328 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
329
330 data = ctrl_inb(SCPDR);
331 /* Set /RTS2 (bit6) = 0 */
332 ctrl_outb(data & 0xbf, SCPDR);
333 }
334
335 sci_out(port, SCFCR, fcr_val);
336 }
337 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339 {
340 unsigned int fcr_val = 0;
341
342 if (cflag & CRTSCTS) {
343 fcr_val |= SCFCR_MCE;
344
345 ctrl_outw(0x0000, PORT_PSCR);
346 } else {
347 unsigned short data;
348
349 data = ctrl_inw(PORT_PSCR);
350 data &= 0x033f;
351 data |= 0x0400;
352 ctrl_outw(data, PORT_PSCR);
353
354 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
355 }
356
357 sci_out(port, SCFCR, fcr_val);
358 }
359 #else
360 /* For SH7750 */
361 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
362 {
363 unsigned int fcr_val = 0;
364
365 if (cflag & CRTSCTS) {
366 fcr_val |= SCFCR_MCE;
367 } else {
368 #ifdef CONFIG_CPU_SUBTYPE_SH7343
369 /* Nothing */
370 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
371 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
372 #else
373 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
374 #endif
375 }
376 sci_out(port, SCFCR, fcr_val);
377 }
378 #endif
379
380 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
381 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
382 defined(CONFIG_CPU_SUBTYPE_SH7785)
383 static inline int scif_txroom(struct uart_port *port)
384 {
385 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
386 }
387
388 static inline int scif_rxroom(struct uart_port *port)
389 {
390 return sci_in(port, SCRFDR) & 0x7f;
391 }
392 #else
393 static inline int scif_txroom(struct uart_port *port)
394 {
395 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
396 }
397
398 static inline int scif_rxroom(struct uart_port *port)
399 {
400 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
401 }
402 #endif
403 #endif /* SCIF_ONLY || SCI_AND_SCIF */
404
405 static inline int sci_txroom(struct uart_port *port)
406 {
407 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
408 }
409
410 static inline int sci_rxroom(struct uart_port *port)
411 {
412 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
413 }
414
415 /* ********************************************************************** *
416 * the interrupt related routines *
417 * ********************************************************************** */
418
419 static void sci_transmit_chars(struct uart_port *port)
420 {
421 struct circ_buf *xmit = &port->info->xmit;
422 unsigned int stopped = uart_tx_stopped(port);
423 unsigned short status;
424 unsigned short ctrl;
425 int count;
426
427 status = sci_in(port, SCxSR);
428 if (!(status & SCxSR_TDxE(port))) {
429 ctrl = sci_in(port, SCSCR);
430 if (uart_circ_empty(xmit)) {
431 ctrl &= ~SCI_CTRL_FLAGS_TIE;
432 } else {
433 ctrl |= SCI_CTRL_FLAGS_TIE;
434 }
435 sci_out(port, SCSCR, ctrl);
436 return;
437 }
438
439 #ifndef SCI_ONLY
440 if (port->type == PORT_SCIF)
441 count = scif_txroom(port);
442 else
443 #endif
444 count = sci_txroom(port);
445
446 do {
447 unsigned char c;
448
449 if (port->x_char) {
450 c = port->x_char;
451 port->x_char = 0;
452 } else if (!uart_circ_empty(xmit) && !stopped) {
453 c = xmit->buf[xmit->tail];
454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
455 } else {
456 break;
457 }
458
459 sci_out(port, SCxTDR, c);
460
461 port->icount.tx++;
462 } while (--count > 0);
463
464 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
465
466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
467 uart_write_wakeup(port);
468 if (uart_circ_empty(xmit)) {
469 sci_stop_tx(port);
470 } else {
471 ctrl = sci_in(port, SCSCR);
472
473 #if !defined(SCI_ONLY)
474 if (port->type == PORT_SCIF) {
475 sci_in(port, SCxSR); /* Dummy read */
476 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
477 }
478 #endif
479
480 ctrl |= SCI_CTRL_FLAGS_TIE;
481 sci_out(port, SCSCR, ctrl);
482 }
483 }
484
485 /* On SH3, SCIF may read end-of-break as a space->mark char */
486 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
487
488 static inline void sci_receive_chars(struct uart_port *port)
489 {
490 struct sci_port *sci_port = (struct sci_port *)port;
491 struct tty_struct *tty = port->info->tty;
492 int i, count, copied = 0;
493 unsigned short status;
494 unsigned char flag;
495
496 status = sci_in(port, SCxSR);
497 if (!(status & SCxSR_RDxF(port)))
498 return;
499
500 while (1) {
501 #if !defined(SCI_ONLY)
502 if (port->type == PORT_SCIF)
503 count = scif_rxroom(port);
504 else
505 #endif
506 count = sci_rxroom(port);
507
508 /* Don't copy more bytes than there is room for in the buffer */
509 count = tty_buffer_request_room(tty, count);
510
511 /* If for any reason we can't copy more data, we're done! */
512 if (count == 0)
513 break;
514
515 if (port->type == PORT_SCI) {
516 char c = sci_in(port, SCxRDR);
517 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
518 count = 0;
519 else {
520 tty_insert_flip_char(tty, c, TTY_NORMAL);
521 }
522 } else {
523 for (i=0; i<count; i++) {
524 char c = sci_in(port, SCxRDR);
525 status = sci_in(port, SCxSR);
526 #if defined(CONFIG_CPU_SH3)
527 /* Skip "chars" during break */
528 if (sci_port->break_flag) {
529 if ((c == 0) &&
530 (status & SCxSR_FER(port))) {
531 count--; i--;
532 continue;
533 }
534
535 /* Nonzero => end-of-break */
536 pr_debug("scif: debounce<%02x>\n", c);
537 sci_port->break_flag = 0;
538
539 if (STEPFN(c)) {
540 count--; i--;
541 continue;
542 }
543 }
544 #endif /* CONFIG_CPU_SH3 */
545 if (uart_handle_sysrq_char(port, c)) {
546 count--; i--;
547 continue;
548 }
549
550 /* Store data and status */
551 if (status&SCxSR_FER(port)) {
552 flag = TTY_FRAME;
553 pr_debug("sci: frame error\n");
554 } else if (status&SCxSR_PER(port)) {
555 flag = TTY_PARITY;
556 pr_debug("sci: parity error\n");
557 } else
558 flag = TTY_NORMAL;
559 tty_insert_flip_char(tty, c, flag);
560 }
561 }
562
563 sci_in(port, SCxSR); /* dummy read */
564 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
565
566 copied += count;
567 port->icount.rx += count;
568 }
569
570 if (copied) {
571 /* Tell the rest of the system the news. New characters! */
572 tty_flip_buffer_push(tty);
573 } else {
574 sci_in(port, SCxSR); /* dummy read */
575 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
576 }
577 }
578
579 #define SCI_BREAK_JIFFIES (HZ/20)
580 /* The sci generates interrupts during the break,
581 * 1 per millisecond or so during the break period, for 9600 baud.
582 * So dont bother disabling interrupts.
583 * But dont want more than 1 break event.
584 * Use a kernel timer to periodically poll the rx line until
585 * the break is finished.
586 */
587 static void sci_schedule_break_timer(struct sci_port *port)
588 {
589 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
590 add_timer(&port->break_timer);
591 }
592 /* Ensure that two consecutive samples find the break over. */
593 static void sci_break_timer(unsigned long data)
594 {
595 struct sci_port *port = (struct sci_port *)data;
596
597 if (sci_rxd_in(&port->port) == 0) {
598 port->break_flag = 1;
599 sci_schedule_break_timer(port);
600 } else if (port->break_flag == 1) {
601 /* break is over. */
602 port->break_flag = 2;
603 sci_schedule_break_timer(port);
604 } else
605 port->break_flag = 0;
606 }
607
608 static inline int sci_handle_errors(struct uart_port *port)
609 {
610 int copied = 0;
611 unsigned short status = sci_in(port, SCxSR);
612 struct tty_struct *tty = port->info->tty;
613
614 if (status & SCxSR_ORER(port)) {
615 /* overrun error */
616 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
617 copied++;
618 pr_debug("sci: overrun error\n");
619 }
620
621 if (status & SCxSR_FER(port)) {
622 if (sci_rxd_in(port) == 0) {
623 /* Notify of BREAK */
624 struct sci_port *sci_port = (struct sci_port *)port;
625
626 if (!sci_port->break_flag) {
627 sci_port->break_flag = 1;
628 sci_schedule_break_timer(sci_port);
629
630 /* Do sysrq handling. */
631 if (uart_handle_break(port))
632 return 0;
633 pr_debug("sci: BREAK detected\n");
634 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
635 copied++;
636 }
637 } else {
638 /* frame error */
639 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
640 copied++;
641 pr_debug("sci: frame error\n");
642 }
643 }
644
645 if (status & SCxSR_PER(port)) {
646 /* parity error */
647 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
648 copied++;
649 pr_debug("sci: parity error\n");
650 }
651
652 if (copied)
653 tty_flip_buffer_push(tty);
654
655 return copied;
656 }
657
658 static inline int sci_handle_breaks(struct uart_port *port)
659 {
660 int copied = 0;
661 unsigned short status = sci_in(port, SCxSR);
662 struct tty_struct *tty = port->info->tty;
663 struct sci_port *s = &sci_ports[port->line];
664
665 if (uart_handle_break(port))
666 return 0;
667
668 if (!s->break_flag && status & SCxSR_BRK(port)) {
669 #if defined(CONFIG_CPU_SH3)
670 /* Debounce break */
671 s->break_flag = 1;
672 #endif
673 /* Notify of BREAK */
674 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
675 copied++;
676 pr_debug("sci: BREAK detected\n");
677 }
678
679 #if defined(SCIF_ORER)
680 /* XXX: Handle SCIF overrun error */
681 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
682 sci_out(port, SCLSR, 0);
683 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
684 copied++;
685 pr_debug("sci: overrun error\n");
686 }
687 }
688 #endif
689
690 if (copied)
691 tty_flip_buffer_push(tty);
692
693 return copied;
694 }
695
696 static irqreturn_t sci_rx_interrupt(int irq, void *port)
697 {
698 /* I think sci_receive_chars has to be called irrespective
699 * of whether the I_IXOFF is set, otherwise, how is the interrupt
700 * to be disabled?
701 */
702 sci_receive_chars(port);
703
704 return IRQ_HANDLED;
705 }
706
707 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
708 {
709 struct uart_port *port = ptr;
710
711 spin_lock_irq(&port->lock);
712 sci_transmit_chars(port);
713 spin_unlock_irq(&port->lock);
714
715 return IRQ_HANDLED;
716 }
717
718 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
719 {
720 struct uart_port *port = ptr;
721
722 /* Handle errors */
723 if (port->type == PORT_SCI) {
724 if (sci_handle_errors(port)) {
725 /* discard character in rx buffer */
726 sci_in(port, SCxSR);
727 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
728 }
729 } else {
730 #if defined(SCIF_ORER)
731 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
732 struct tty_struct *tty = port->info->tty;
733
734 sci_out(port, SCLSR, 0);
735 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
736 tty_flip_buffer_push(tty);
737 pr_debug("scif: overrun error\n");
738 }
739 #endif
740 sci_rx_interrupt(irq, ptr);
741 }
742
743 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
744
745 /* Kick the transmission */
746 sci_tx_interrupt(irq, ptr);
747
748 return IRQ_HANDLED;
749 }
750
751 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
752 {
753 struct uart_port *port = ptr;
754
755 /* Handle BREAKs */
756 sci_handle_breaks(port);
757 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
758
759 return IRQ_HANDLED;
760 }
761
762 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
763 {
764 unsigned short ssr_status, scr_status;
765 struct uart_port *port = ptr;
766
767 ssr_status = sci_in(port,SCxSR);
768 scr_status = sci_in(port,SCSCR);
769
770 /* Tx Interrupt */
771 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
772 sci_tx_interrupt(irq, ptr);
773 /* Rx Interrupt */
774 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
775 sci_rx_interrupt(irq, ptr);
776 /* Error Interrupt */
777 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
778 sci_er_interrupt(irq, ptr);
779 /* Break Interrupt */
780 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
781 sci_br_interrupt(irq, ptr);
782
783 return IRQ_HANDLED;
784 }
785
786 #ifdef CONFIG_CPU_FREQ
787 /*
788 * Here we define a transistion notifier so that we can update all of our
789 * ports' baud rate when the peripheral clock changes.
790 */
791 static int sci_notifier(struct notifier_block *self,
792 unsigned long phase, void *p)
793 {
794 struct cpufreq_freqs *freqs = p;
795 int i;
796
797 if ((phase == CPUFREQ_POSTCHANGE) ||
798 (phase == CPUFREQ_RESUMECHANGE)){
799 for (i = 0; i < SCI_NPORTS; i++) {
800 struct uart_port *port = &sci_ports[i].port;
801 struct clk *clk;
802
803 /*
804 * Update the uartclk per-port if frequency has
805 * changed, since it will no longer necessarily be
806 * consistent with the old frequency.
807 *
808 * Really we want to be able to do something like
809 * uart_change_speed() or something along those lines
810 * here to implicitly reset the per-port baud rate..
811 *
812 * Clean this up later..
813 */
814 clk = clk_get(NULL, "module_clk");
815 port->uartclk = clk_get_rate(clk) * 16;
816 clk_put(clk);
817 }
818
819 printk(KERN_INFO "%s: got a postchange notification "
820 "for cpu %d (old %d, new %d)\n",
821 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
822 }
823
824 return NOTIFY_OK;
825 }
826
827 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
828 #endif /* CONFIG_CPU_FREQ */
829
830 static int sci_request_irq(struct sci_port *port)
831 {
832 int i;
833 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
834 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
835 sci_br_interrupt,
836 };
837 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
838 "SCI Transmit Data Empty", "SCI Break" };
839
840 if (port->irqs[0] == port->irqs[1]) {
841 if (!port->irqs[0]) {
842 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
843 return -ENODEV;
844 }
845
846 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
847 IRQF_DISABLED, "sci", port)) {
848 printk(KERN_ERR "sci: Cannot allocate irq.\n");
849 return -ENODEV;
850 }
851 } else {
852 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
853 if (!port->irqs[i])
854 continue;
855 if (request_irq(port->irqs[i], handlers[i],
856 IRQF_DISABLED, desc[i], port)) {
857 printk(KERN_ERR "sci: Cannot allocate irq.\n");
858 return -ENODEV;
859 }
860 }
861 }
862
863 return 0;
864 }
865
866 static void sci_free_irq(struct sci_port *port)
867 {
868 int i;
869
870 if (port->irqs[0] == port->irqs[1]) {
871 if (!port->irqs[0])
872 printk("sci: sci_free_irq error\n");
873 else
874 free_irq(port->irqs[0], port);
875 } else {
876 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
877 if (!port->irqs[i])
878 continue;
879
880 free_irq(port->irqs[i], port);
881 }
882 }
883 }
884
885 static unsigned int sci_tx_empty(struct uart_port *port)
886 {
887 /* Can't detect */
888 return TIOCSER_TEMT;
889 }
890
891 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
892 {
893 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
894 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
895 /* If you have signals for DTR and DCD, please implement here. */
896 }
897
898 static unsigned int sci_get_mctrl(struct uart_port *port)
899 {
900 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
901 and CTS/RTS */
902
903 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
904 }
905
906 static void sci_start_tx(struct uart_port *port)
907 {
908 unsigned short ctrl;
909
910 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
911 ctrl = sci_in(port, SCSCR);
912 ctrl |= SCI_CTRL_FLAGS_TIE;
913 sci_out(port, SCSCR, ctrl);
914 }
915
916 static void sci_stop_tx(struct uart_port *port)
917 {
918 unsigned short ctrl;
919
920 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
921 ctrl = sci_in(port, SCSCR);
922 ctrl &= ~SCI_CTRL_FLAGS_TIE;
923 sci_out(port, SCSCR, ctrl);
924 }
925
926 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
927 {
928 unsigned short ctrl;
929
930 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
931 ctrl = sci_in(port, SCSCR);
932 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
933 sci_out(port, SCSCR, ctrl);
934 }
935
936 static void sci_stop_rx(struct uart_port *port)
937 {
938 unsigned short ctrl;
939
940 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
941 ctrl = sci_in(port, SCSCR);
942 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
943 sci_out(port, SCSCR, ctrl);
944 }
945
946 static void sci_enable_ms(struct uart_port *port)
947 {
948 /* Nothing here yet .. */
949 }
950
951 static void sci_break_ctl(struct uart_port *port, int break_state)
952 {
953 /* Nothing here yet .. */
954 }
955
956 static int sci_startup(struct uart_port *port)
957 {
958 struct sci_port *s = &sci_ports[port->line];
959
960 if (s->enable)
961 s->enable(port);
962
963 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
964 s->clk = clk_get(NULL, "module_clk");
965 #endif
966
967 sci_request_irq(s);
968 sci_start_tx(port);
969 sci_start_rx(port, 1);
970
971 return 0;
972 }
973
974 static void sci_shutdown(struct uart_port *port)
975 {
976 struct sci_port *s = &sci_ports[port->line];
977
978 sci_stop_rx(port);
979 sci_stop_tx(port);
980 sci_free_irq(s);
981
982 if (s->disable)
983 s->disable(port);
984
985 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
986 clk_put(s->clk);
987 s->clk = NULL;
988 #endif
989 }
990
991 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
992 struct ktermios *old)
993 {
994 struct sci_port *s = &sci_ports[port->line];
995 unsigned int status, baud, smr_val;
996 int t;
997
998 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
999
1000 switch (baud) {
1001 case 0:
1002 t = -1;
1003 break;
1004 default:
1005 {
1006 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1007 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1008 #else
1009 t = SCBRR_VALUE(baud);
1010 #endif
1011 break;
1012 }
1013 }
1014
1015 do {
1016 status = sci_in(port, SCxSR);
1017 } while (!(status & SCxSR_TEND(port)));
1018
1019 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1020
1021 #if !defined(SCI_ONLY)
1022 if (port->type == PORT_SCIF)
1023 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1024 #endif
1025
1026 smr_val = sci_in(port, SCSMR) & 3;
1027 if ((termios->c_cflag & CSIZE) == CS7)
1028 smr_val |= 0x40;
1029 if (termios->c_cflag & PARENB)
1030 smr_val |= 0x20;
1031 if (termios->c_cflag & PARODD)
1032 smr_val |= 0x30;
1033 if (termios->c_cflag & CSTOPB)
1034 smr_val |= 0x08;
1035
1036 uart_update_timeout(port, termios->c_cflag, baud);
1037
1038 sci_out(port, SCSMR, smr_val);
1039
1040 if (t > 0) {
1041 if(t >= 256) {
1042 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1043 t >>= 2;
1044 } else {
1045 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1046 }
1047 sci_out(port, SCBRR, t);
1048 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1049 }
1050
1051 if (likely(s->init_pins))
1052 s->init_pins(port, termios->c_cflag);
1053
1054 sci_out(port, SCSCR, SCSCR_INIT(port));
1055
1056 if ((termios->c_cflag & CREAD) != 0)
1057 sci_start_rx(port,0);
1058 }
1059
1060 static const char *sci_type(struct uart_port *port)
1061 {
1062 switch (port->type) {
1063 case PORT_SCI: return "sci";
1064 case PORT_SCIF: return "scif";
1065 case PORT_IRDA: return "irda";
1066 }
1067
1068 return 0;
1069 }
1070
1071 static void sci_release_port(struct uart_port *port)
1072 {
1073 /* Nothing here yet .. */
1074 }
1075
1076 static int sci_request_port(struct uart_port *port)
1077 {
1078 /* Nothing here yet .. */
1079 return 0;
1080 }
1081
1082 static void sci_config_port(struct uart_port *port, int flags)
1083 {
1084 struct sci_port *s = &sci_ports[port->line];
1085
1086 port->type = s->type;
1087
1088 switch (port->type) {
1089 case PORT_SCI:
1090 s->init_pins = sci_init_pins_sci;
1091 break;
1092 case PORT_SCIF:
1093 s->init_pins = sci_init_pins_scif;
1094 break;
1095 case PORT_IRDA:
1096 s->init_pins = sci_init_pins_irda;
1097 break;
1098 }
1099
1100 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1101 if (port->mapbase == 0)
1102 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1103
1104 port->membase = (void __iomem *)port->mapbase;
1105 #endif
1106 }
1107
1108 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1109 {
1110 struct sci_port *s = &sci_ports[port->line];
1111
1112 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1113 return -EINVAL;
1114 if (ser->baud_base < 2400)
1115 /* No paper tape reader for Mitch.. */
1116 return -EINVAL;
1117
1118 return 0;
1119 }
1120
1121 static struct uart_ops sci_uart_ops = {
1122 .tx_empty = sci_tx_empty,
1123 .set_mctrl = sci_set_mctrl,
1124 .get_mctrl = sci_get_mctrl,
1125 .start_tx = sci_start_tx,
1126 .stop_tx = sci_stop_tx,
1127 .stop_rx = sci_stop_rx,
1128 .enable_ms = sci_enable_ms,
1129 .break_ctl = sci_break_ctl,
1130 .startup = sci_startup,
1131 .shutdown = sci_shutdown,
1132 .set_termios = sci_set_termios,
1133 .type = sci_type,
1134 .release_port = sci_release_port,
1135 .request_port = sci_request_port,
1136 .config_port = sci_config_port,
1137 .verify_port = sci_verify_port,
1138 };
1139
1140 static void __init sci_init_ports(void)
1141 {
1142 static int first = 1;
1143 int i;
1144
1145 if (!first)
1146 return;
1147
1148 first = 0;
1149
1150 for (i = 0; i < SCI_NPORTS; i++) {
1151 sci_ports[i].port.ops = &sci_uart_ops;
1152 sci_ports[i].port.iotype = UPIO_MEM;
1153 sci_ports[i].port.line = i;
1154 sci_ports[i].port.fifosize = 1;
1155
1156 #if defined(__H8300H__) || defined(__H8300S__)
1157 #ifdef __H8300S__
1158 sci_ports[i].enable = h8300_sci_enable;
1159 sci_ports[i].disable = h8300_sci_disable;
1160 #endif
1161 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1162 #elif defined(CONFIG_SUPERH64)
1163 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1164 #else
1165 /*
1166 * XXX: We should use a proper SCI/SCIF clock
1167 */
1168 {
1169 struct clk *clk = clk_get(NULL, "module_clk");
1170 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1171 clk_put(clk);
1172 }
1173 #endif
1174
1175 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1176 sci_ports[i].break_timer.function = sci_break_timer;
1177
1178 init_timer(&sci_ports[i].break_timer);
1179 }
1180 }
1181
1182 int __init early_sci_setup(struct uart_port *port)
1183 {
1184 if (unlikely(port->line > SCI_NPORTS))
1185 return -ENODEV;
1186
1187 sci_init_ports();
1188
1189 sci_ports[port->line].port.membase = port->membase;
1190 sci_ports[port->line].port.mapbase = port->mapbase;
1191 sci_ports[port->line].port.type = port->type;
1192
1193 return 0;
1194 }
1195
1196 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1197 /*
1198 * Print a string to the serial port trying not to disturb
1199 * any possible real use of the port...
1200 */
1201 static void serial_console_write(struct console *co, const char *s,
1202 unsigned count)
1203 {
1204 put_string(serial_console_port, s, count);
1205 }
1206
1207 static int __init serial_console_setup(struct console *co, char *options)
1208 {
1209 struct uart_port *port;
1210 int baud = 115200;
1211 int bits = 8;
1212 int parity = 'n';
1213 int flow = 'n';
1214 int ret;
1215
1216 /*
1217 * Check whether an invalid uart number has been specified, and
1218 * if so, search for the first available port that does have
1219 * console support.
1220 */
1221 if (co->index >= SCI_NPORTS)
1222 co->index = 0;
1223
1224 serial_console_port = &sci_ports[co->index];
1225 port = &serial_console_port->port;
1226
1227 /*
1228 * Also need to check port->type, we don't actually have any
1229 * UPIO_PORT ports, but uart_report_port() handily misreports
1230 * it anyways if we don't have a port available by the time this is
1231 * called.
1232 */
1233 if (!port->type)
1234 return -ENODEV;
1235 if (!port->membase || !port->mapbase)
1236 return -ENODEV;
1237
1238 port->type = serial_console_port->type;
1239
1240 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1241 if (!serial_console_port->clk)
1242 serial_console_port->clk = clk_get(NULL, "module_clk");
1243 #endif
1244
1245 if (port->flags & UPF_IOREMAP)
1246 sci_config_port(port, 0);
1247
1248 if (serial_console_port->enable)
1249 serial_console_port->enable(port);
1250
1251 if (options)
1252 uart_parse_options(options, &baud, &parity, &bits, &flow);
1253
1254 ret = uart_set_options(port, co, baud, parity, bits, flow);
1255 #if defined(__H8300H__) || defined(__H8300S__)
1256 /* disable rx interrupt */
1257 if (ret == 0)
1258 sci_stop_rx(port);
1259 #endif
1260 return ret;
1261 }
1262
1263 static struct console serial_console = {
1264 .name = "ttySC",
1265 .device = uart_console_device,
1266 .write = serial_console_write,
1267 .setup = serial_console_setup,
1268 .flags = CON_PRINTBUFFER,
1269 .index = -1,
1270 .data = &sci_uart_driver,
1271 };
1272
1273 static int __init sci_console_init(void)
1274 {
1275 sci_init_ports();
1276 register_console(&serial_console);
1277 return 0;
1278 }
1279 console_initcall(sci_console_init);
1280 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1281
1282 #ifdef CONFIG_SH_KGDB
1283 /*
1284 * FIXME: Most of this can go away.. at the moment, we rely on
1285 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1286 * most of that can easily be done here instead.
1287 *
1288 * For the time being, just accept the values that were parsed earlier..
1289 */
1290 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1291 int *parity, int *bits)
1292 {
1293 *baud = kgdb_baud;
1294 *parity = tolower(kgdb_parity);
1295 *bits = kgdb_bits - '0';
1296 }
1297
1298 /*
1299 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1300 * care of the early-on initialization for kgdb, regardless of whether we
1301 * actually use kgdb as a console or not.
1302 *
1303 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1304 */
1305 int __init kgdb_console_setup(struct console *co, char *options)
1306 {
1307 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1308 int baud = 38400;
1309 int bits = 8;
1310 int parity = 'n';
1311 int flow = 'n';
1312
1313 if (co->index != kgdb_portnum)
1314 co->index = kgdb_portnum;
1315
1316 kgdb_sci_port = &sci_ports[co->index];
1317 port = &kgdb_sci_port->port;
1318
1319 /*
1320 * Also need to check port->type, we don't actually have any
1321 * UPIO_PORT ports, but uart_report_port() handily misreports
1322 * it anyways if we don't have a port available by the time this is
1323 * called.
1324 */
1325 if (!port->type)
1326 return -ENODEV;
1327 if (!port->membase || !port->mapbase)
1328 return -ENODEV;
1329
1330 if (options)
1331 uart_parse_options(options, &baud, &parity, &bits, &flow);
1332 else
1333 kgdb_console_get_options(port, &baud, &parity, &bits);
1334
1335 kgdb_getchar = kgdb_sci_getchar;
1336 kgdb_putchar = kgdb_sci_putchar;
1337
1338 return uart_set_options(port, co, baud, parity, bits, flow);
1339 }
1340 #endif /* CONFIG_SH_KGDB */
1341
1342 #ifdef CONFIG_SH_KGDB_CONSOLE
1343 static struct console kgdb_console = {
1344 .name = "ttySC",
1345 .device = uart_console_device,
1346 .write = kgdb_console_write,
1347 .setup = kgdb_console_setup,
1348 .flags = CON_PRINTBUFFER,
1349 .index = -1,
1350 .data = &sci_uart_driver,
1351 };
1352
1353 /* Register the KGDB console so we get messages (d'oh!) */
1354 static int __init kgdb_console_init(void)
1355 {
1356 sci_init_ports();
1357 register_console(&kgdb_console);
1358 return 0;
1359 }
1360 console_initcall(kgdb_console_init);
1361 #endif /* CONFIG_SH_KGDB_CONSOLE */
1362
1363 #if defined(CONFIG_SH_KGDB_CONSOLE)
1364 #define SCI_CONSOLE &kgdb_console
1365 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1366 #define SCI_CONSOLE &serial_console
1367 #else
1368 #define SCI_CONSOLE 0
1369 #endif
1370
1371 static char banner[] __initdata =
1372 KERN_INFO "SuperH SCI(F) driver initialized\n";
1373
1374 static struct uart_driver sci_uart_driver = {
1375 .owner = THIS_MODULE,
1376 .driver_name = "sci",
1377 .dev_name = "ttySC",
1378 .major = SCI_MAJOR,
1379 .minor = SCI_MINOR_START,
1380 .nr = SCI_NPORTS,
1381 .cons = SCI_CONSOLE,
1382 };
1383
1384 /*
1385 * Register a set of serial devices attached to a platform device. The
1386 * list is terminated with a zero flags entry, which means we expect
1387 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1388 * remapping (such as sh64) should also set UPF_IOREMAP.
1389 */
1390 static int __devinit sci_probe(struct platform_device *dev)
1391 {
1392 struct plat_sci_port *p = dev->dev.platform_data;
1393 int i;
1394
1395 for (i = 0; p && p->flags != 0; p++, i++) {
1396 struct sci_port *sciport = &sci_ports[i];
1397
1398 /* Sanity check */
1399 if (unlikely(i == SCI_NPORTS)) {
1400 dev_notice(&dev->dev, "Attempting to register port "
1401 "%d when only %d are available.\n",
1402 i+1, SCI_NPORTS);
1403 dev_notice(&dev->dev, "Consider bumping "
1404 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1405 break;
1406 }
1407
1408 sciport->port.mapbase = p->mapbase;
1409
1410 /*
1411 * For the simple (and majority of) cases where we don't need
1412 * to do any remapping, just cast the cookie directly.
1413 */
1414 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1415 p->membase = (void __iomem *)p->mapbase;
1416
1417 sciport->port.membase = p->membase;
1418
1419 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1420 sciport->port.flags = p->flags;
1421 sciport->port.dev = &dev->dev;
1422
1423 sciport->type = sciport->port.type = p->type;
1424
1425 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1426
1427 uart_add_one_port(&sci_uart_driver, &sciport->port);
1428 }
1429
1430 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1431 kgdb_sci_port = &sci_ports[kgdb_portnum];
1432 kgdb_getchar = kgdb_sci_getchar;
1433 kgdb_putchar = kgdb_sci_putchar;
1434 #endif
1435
1436 #ifdef CONFIG_CPU_FREQ
1437 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1438 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1439 #endif
1440
1441 #ifdef CONFIG_SH_STANDARD_BIOS
1442 sh_bios_gdb_detach();
1443 #endif
1444
1445 return 0;
1446 }
1447
1448 static int __devexit sci_remove(struct platform_device *dev)
1449 {
1450 int i;
1451
1452 for (i = 0; i < SCI_NPORTS; i++)
1453 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1454
1455 return 0;
1456 }
1457
1458 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1459 {
1460 int i;
1461
1462 for (i = 0; i < SCI_NPORTS; i++) {
1463 struct sci_port *p = &sci_ports[i];
1464
1465 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1466 uart_suspend_port(&sci_uart_driver, &p->port);
1467 }
1468
1469 return 0;
1470 }
1471
1472 static int sci_resume(struct platform_device *dev)
1473 {
1474 int i;
1475
1476 for (i = 0; i < SCI_NPORTS; i++) {
1477 struct sci_port *p = &sci_ports[i];
1478
1479 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1480 uart_resume_port(&sci_uart_driver, &p->port);
1481 }
1482
1483 return 0;
1484 }
1485
1486 static struct platform_driver sci_driver = {
1487 .probe = sci_probe,
1488 .remove = __devexit_p(sci_remove),
1489 .suspend = sci_suspend,
1490 .resume = sci_resume,
1491 .driver = {
1492 .name = "sh-sci",
1493 .owner = THIS_MODULE,
1494 },
1495 };
1496
1497 static int __init sci_init(void)
1498 {
1499 int ret;
1500
1501 printk(banner);
1502
1503 sci_init_ports();
1504
1505 ret = uart_register_driver(&sci_uart_driver);
1506 if (likely(ret == 0)) {
1507 ret = platform_driver_register(&sci_driver);
1508 if (unlikely(ret))
1509 uart_unregister_driver(&sci_uart_driver);
1510 }
1511
1512 return ret;
1513 }
1514
1515 static void __exit sci_exit(void)
1516 {
1517 platform_driver_unregister(&sci_driver);
1518 uart_unregister_driver(&sci_uart_driver);
1519 }
1520
1521 module_init(sci_init);
1522 module_exit(sci_exit);
1523
1524 MODULE_LICENSE("GPL");
Tomato firmware and modifications.