release/src-rt-6.x/linux/linux-2.6/drivers/media/dvb/frontends/mt312.c

   1 /*
   2     Driver for Zarlink VP310/MT312 Satellite Channel Decoder
   3
   4     Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21     References:
  22     http://products.zarlink.com/product_profiles/MT312.htm
  23     http://products.zarlink.com/product_profiles/SL1935.htm
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/string.h>
  33 #include <linux/slab.h>
  34
  35 #include "dvb_frontend.h"
  36 #include "mt312_priv.h"
  37 #include "mt312.h"
  38
  39
  40 struct mt312_state {
  41         struct i2c_adapter* i2c;
  42         /* configuration settings */
  43         const struct mt312_config* config;
  44         struct dvb_frontend frontend;
  45
  46         u8 id;
  47         u8 frequency;
  48 };
  49
  50 static int debug;
  51 #define dprintk(args...) \
  52         do { \
  53                 if (debug) printk(KERN_DEBUG "mt312: " args); \
  54         } while (0)
  55
  56 #define MT312_SYS_CLK           90000000UL      /* 90 MHz */
  57 #define MT312_LPOWER_SYS_CLK    60000000UL      /* 60 MHz */
  58 #define MT312_PLL_CLK           10000000UL      /* 10 MHz */
  59
  60 static int mt312_read(struct mt312_state* state, const enum mt312_reg_addr reg,
  61                       void *buf, const size_t count)
  62 {
  63         int ret;
  64         struct i2c_msg msg[2];
  65         u8 regbuf[1] = { reg };
  66
  67         msg[0].addr = state->config->demod_address;
  68         msg[0].flags = 0;
  69         msg[0].buf = regbuf;
  70         msg[0].len = 1;
  71         msg[1].addr = state->config->demod_address;
  72         msg[1].flags = I2C_M_RD;
  73         msg[1].buf = buf;
  74         msg[1].len = count;
  75
  76         ret = i2c_transfer(state->i2c, msg, 2);
  77
  78         if (ret != 2) {
  79                 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
  80                 return -EREMOTEIO;
  81         }
  82
  83         if(debug) {
  84                 int i;
  85                 dprintk("R(%d):", reg & 0x7f);
  86                 for (i = 0; i < count; i++)
  87                         printk(" %02x", ((const u8 *) buf)[i]);
  88                 printk("\n");
  89         }
  90
  91         return 0;
  92 }
  93
  94 static int mt312_write(struct mt312_state* state, const enum mt312_reg_addr reg,
  95                        const void *src, const size_t count)
  96 {
  97         int ret;
  98         u8 buf[count + 1];
  99         struct i2c_msg msg;
 100
 101         if(debug) {
 102                 int i;
 103                 dprintk("W(%d):", reg & 0x7f);
 104                 for (i = 0; i < count; i++)
 105                         printk(" %02x", ((const u8 *) src)[i]);
 106                 printk("\n");
 107         }
 108
 109         buf[0] = reg;
 110         memcpy(&buf[1], src, count);
 111
 112         msg.addr = state->config->demod_address;
 113         msg.flags = 0;
 114         msg.buf = buf;
 115         msg.len = count + 1;
 116
 117         ret = i2c_transfer(state->i2c, &msg, 1);
 118
 119         if (ret != 1) {
 120                 dprintk("%s: ret == %d\n", __FUNCTION__, ret);
 121                 return -EREMOTEIO;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static inline int mt312_readreg(struct mt312_state* state,
 128                                 const enum mt312_reg_addr reg, u8 *val)
 129 {
 130         return mt312_read(state, reg, val, 1);
 131 }
 132
 133 static inline int mt312_writereg(struct mt312_state* state,
 134                                  const enum mt312_reg_addr reg, const u8 val)
 135 {
 136         return mt312_write(state, reg, &val, 1);
 137 }
 138
 139 static inline u32 mt312_div(u32 a, u32 b)
 140 {
 141         return (a + (b / 2)) / b;
 142 }
 143
 144 static int mt312_reset(struct mt312_state* state, const u8 full)
 145 {
 146         return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
 147 }
 148
 149 static int mt312_get_inversion(struct mt312_state* state,
 150                                fe_spectral_inversion_t *i)
 151 {
 152         int ret;
 153         u8 vit_mode;
 154
 155         if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0)
 156                 return ret;
 157
 158         if (vit_mode & 0x80)    /* auto inversion was used */
 159                 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
 160
 161         return 0;
 162 }
 163
 164 static int mt312_get_symbol_rate(struct mt312_state* state, u32 *sr)
 165 {
 166         int ret;
 167         u8 sym_rate_h;
 168         u8 dec_ratio;
 169         u16 sym_rat_op;
 170         u16 monitor;
 171         u8 buf[2];
 172
 173         if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0)
 174                 return ret;
 175
 176         if (sym_rate_h & 0x80) {        /* symbol rate search was used */
 177                 if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0)
 178                         return ret;
 179
 180                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 181                         return ret;
 182
 183                 monitor = (buf[0] << 8) | buf[1];
 184
 185                 dprintk(KERN_DEBUG "sr(auto) = %u\n",
 186                        mt312_div(monitor * 15625, 4));
 187         } else {
 188                 if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0)
 189                         return ret;
 190
 191                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 192                         return ret;
 193
 194                 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
 195
 196                 if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
 197                         return ret;
 198
 199                 sym_rat_op = (buf[0] << 8) | buf[1];
 200
 201                 dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
 202                        sym_rat_op, dec_ratio);
 203                 dprintk(KERN_DEBUG "*sr(manual) = %lu\n",
 204                        (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
 205                         2) - dec_ratio);
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int mt312_get_code_rate(struct mt312_state* state, fe_code_rate_t *cr)
 212 {
 213         const fe_code_rate_t fec_tab[8] =
 214             { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
 215                 FEC_AUTO, FEC_AUTO };
 216
 217         int ret;
 218         u8 fec_status;
 219
 220         if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0)
 221                 return ret;
 222
 223         *cr = fec_tab[(fec_status >> 4) & 0x07];
 224
 225         return 0;
 226 }
 227
 228 static int mt312_initfe(struct dvb_frontend* fe)
 229 {
 230         struct mt312_state *state = fe->demodulator_priv;
 231         int ret;
 232         u8 buf[2];
 233
 234         /* wake up */
 235         if ((ret = mt312_writereg(state, CONFIG, (state->frequency == 60 ? 0x88 : 0x8c))) < 0)
 236                 return ret;
 237
 238         /* wait at least 150 usec */
 239         udelay(150);
 240
 241         /* full reset */
 242         if ((ret = mt312_reset(state, 1)) < 0)
 243                 return ret;
 244
 245 // Per datasheet, write correct values. 09/28/03 ACCJr.
 246 // If we don't do this, we won't get FE_HAS_VITERBI in the VP310.
 247         {
 248                 u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};
 249
 250                 if ((ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)
 251                         return ret;
 252         }
 253
 254         /* SYS_CLK */
 255         buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);
 256
 257         /* DISEQC_RATIO */
 258         buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
 259
 260         if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0)
 261                 return ret;
 262
 263         if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0)
 264                 return ret;
 265
 266         if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0)
 267                 return ret;
 268
 269         /* TS_SW_LIM */
 270         buf[0] = 0x8c;
 271         buf[1] = 0x98;
 272
 273         if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
 274                 return ret;
 275
 276         if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0)
 277                 return ret;
 278
 279         return 0;
 280 }
 281
 282 static int mt312_send_master_cmd(struct dvb_frontend* fe,
 283                                  struct dvb_diseqc_master_cmd *c)
 284 {
 285         struct mt312_state *state = fe->demodulator_priv;
 286         int ret;
 287         u8 diseqc_mode;
 288
 289         if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
 290                 return -EINVAL;
 291
 292         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 293                 return ret;
 294
 295         if ((ret =
 296              mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
 297                 return ret;
 298
 299         if ((ret =
 300              mt312_writereg(state, DISEQC_MODE,
 301                             (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
 302                             | 0x04)) < 0)
 303                 return ret;
 304
 305         /* set DISEQC_MODE[2:0] to zero if a return message is expected */
 306         if (c->msg[0] & 0x02)
 307                 if ((ret =
 308                      mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
 309                         return ret;
 310
 311         return 0;
 312 }
 313
 314 static int mt312_send_burst(struct dvb_frontend* fe, const fe_sec_mini_cmd_t c)
 315 {
 316         struct mt312_state *state = fe->demodulator_priv;
 317         const u8 mini_tab[2] = { 0x02, 0x03 };
 318
 319         int ret;
 320         u8 diseqc_mode;
 321
 322         if (c > SEC_MINI_B)
 323                 return -EINVAL;
 324
 325         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 326                 return ret;
 327
 328         if ((ret =
 329              mt312_writereg(state, DISEQC_MODE,
 330                             (diseqc_mode & 0x40) | mini_tab[c])) < 0)
 331                 return ret;
 332
 333         return 0;
 334 }
 335
 336 static int mt312_set_tone(struct dvb_frontend* fe, const fe_sec_tone_mode_t t)
 337 {
 338         struct mt312_state *state = fe->demodulator_priv;
 339         const u8 tone_tab[2] = { 0x01, 0x00 };
 340
 341         int ret;
 342         u8 diseqc_mode;
 343
 344         if (t > SEC_TONE_OFF)
 345                 return -EINVAL;
 346
 347         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 348                 return ret;
 349
 350         if ((ret =
 351              mt312_writereg(state, DISEQC_MODE,
 352                             (diseqc_mode & 0x40) | tone_tab[t])) < 0)
 353                 return ret;
 354
 355         return 0;
 356 }
 357
 358 static int mt312_set_voltage(struct dvb_frontend* fe, const fe_sec_voltage_t v)
 359 {
 360         struct mt312_state *state = fe->demodulator_priv;
 361         const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
 362
 363         if (v > SEC_VOLTAGE_OFF)
 364                 return -EINVAL;
 365
 366         return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
 367 }
 368
 369 static int mt312_read_status(struct dvb_frontend* fe, fe_status_t *s)
 370 {
 371         struct mt312_state *state = fe->demodulator_priv;
 372         int ret;
 373         u8 status[3];
 374
 375         *s = 0;
 376
 377         if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0)
 378                 return ret;
 379
 380         dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
 381
 382         if (status[0] & 0xc0)
 383                 *s |= FE_HAS_SIGNAL;    /* signal noise ratio */
 384         if (status[0] & 0x04)
 385                 *s |= FE_HAS_CARRIER;   /* qpsk carrier lock */
 386         if (status[2] & 0x02)
 387                 *s |= FE_HAS_VITERBI;   /* viterbi lock */
 388         if (status[2] & 0x04)
 389                 *s |= FE_HAS_SYNC;      /* byte align lock */
 390         if (status[0] & 0x01)
 391                 *s |= FE_HAS_LOCK;      /* qpsk lock */
 392
 393         return 0;
 394 }
 395
 396 static int mt312_read_ber(struct dvb_frontend* fe, u32 *ber)
 397 {
 398         struct mt312_state *state = fe->demodulator_priv;
 399         int ret;
 400         u8 buf[3];
 401
 402         if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0)
 403                 return ret;
 404
 405         *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
 406
 407         return 0;
 408 }
 409
 410 static int mt312_read_signal_strength(struct dvb_frontend* fe, u16 *signal_strength)
 411 {
 412         struct mt312_state *state = fe->demodulator_priv;
 413         int ret;
 414         u8 buf[3];
 415         u16 agc;
 416         s16 err_db;
 417
 418         if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0)
 419                 return ret;
 420
 421         agc = (buf[0] << 6) | (buf[1] >> 2);
 422         err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
 423
 424         *signal_strength = agc;
 425
 426         dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
 427
 428         return 0;
 429 }
 430
 431 static int mt312_read_snr(struct dvb_frontend* fe, u16 *snr)
 432 {
 433         struct mt312_state *state = fe->demodulator_priv;
 434         int ret;
 435         u8 buf[2];
 436
 437         if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0)
 438                 return ret;
 439
 440         *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
 441
 442         return 0;
 443 }
 444
 445 static int mt312_read_ucblocks(struct dvb_frontend* fe, u32 *ubc)
 446 {
 447         struct mt312_state *state = fe->demodulator_priv;
 448         int ret;
 449         u8 buf[2];
 450
 451         if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0)
 452                 return ret;
 453
 454         *ubc = (buf[0] << 8) | buf[1];
 455
 456         return 0;
 457 }
 458
 459 static int mt312_set_frontend(struct dvb_frontend* fe,
 460                               struct dvb_frontend_parameters *p)
 461 {
 462         struct mt312_state *state = fe->demodulator_priv;
 463         int ret;
 464         u8 buf[5], config_val;
 465         u16 sr;
 466
 467         const u8 fec_tab[10] =
 468             { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
 469         const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
 470
 471         dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
 472
 473         if ((p->frequency < fe->ops.info.frequency_min)
 474             || (p->frequency > fe->ops.info.frequency_max))
 475                 return -EINVAL;
 476
 477         if ((p->inversion < INVERSION_OFF)
 478             || (p->inversion > INVERSION_ON))
 479                 return -EINVAL;
 480
 481         if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
 482             || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
 483                 return -EINVAL;
 484
 485         if ((p->u.qpsk.fec_inner < FEC_NONE)
 486             || (p->u.qpsk.fec_inner > FEC_AUTO))
 487                 return -EINVAL;
 488
 489         if ((p->u.qpsk.fec_inner == FEC_4_5)
 490             || (p->u.qpsk.fec_inner == FEC_8_9))
 491                 return -EINVAL;
 492
 493         switch (state->id) {
 494         case ID_VP310:
 495         // For now we will do this only for the VP310.
 496         // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03
 497                 ret = mt312_readreg(state, CONFIG, &config_val);
 498                 if (ret < 0)
 499                         return ret;
 500                 if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz
 501                 {
 502                         if ((config_val & 0x0c) == 0x08) { //We are running 60MHz
 503                                 state->frequency = 90;
 504                                 if ((ret = mt312_initfe(fe)) < 0)
 505                                         return ret;
 506                         }
 507                 }
 508                 else
 509                 {
 510                         if ((config_val & 0x0c) == 0x0C) { //We are running 90MHz
 511                                 state->frequency = 60;
 512                                 if ((ret = mt312_initfe(fe)) < 0)
 513                                         return ret;
 514                         }
 515                 }
 516                 break;
 517
 518         case ID_MT312:
 519                 break;
 520
 521         default:
 522                 return -EINVAL;
 523         }
 524
 525         if (fe->ops.tuner_ops.set_params) {
 526                 fe->ops.tuner_ops.set_params(fe, p);
 527                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 528         }
 529
 530         /* sr = (u16)(sr * 256.0 / 1000000.0) */
 531         sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
 532
 533         /* SYM_RATE */
 534         buf[0] = (sr >> 8) & 0x3f;
 535         buf[1] = (sr >> 0) & 0xff;
 536
 537         /* VIT_MODE */
 538         buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
 539
 540         /* QPSK_CTRL */
 541         buf[3] = 0x40;          /* swap I and Q before QPSK demodulation */
 542
 543         if (p->u.qpsk.symbol_rate < 10000000)
 544                 buf[3] |= 0x04; /* use afc mode */
 545
 546         /* GO */
 547         buf[4] = 0x01;
 548
 549         if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0)
 550                 return ret;
 551
 552         mt312_reset(state, 0);
 553
 554         return 0;
 555 }
 556
 557 static int mt312_get_frontend(struct dvb_frontend* fe,
 558                               struct dvb_frontend_parameters *p)
 559 {
 560         struct mt312_state *state = fe->demodulator_priv;
 561         int ret;
 562
 563         if ((ret = mt312_get_inversion(state, &p->inversion)) < 0)
 564                 return ret;
 565
 566         if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0)
 567                 return ret;
 568
 569         if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0)
 570                 return ret;
 571
 572         return 0;
 573 }
 574
 575 static int mt312_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
 576 {
 577         struct mt312_state* state = fe->demodulator_priv;
 578
 579         if (enable) {
 580                 return mt312_writereg(state, GPP_CTRL, 0x40);
 581         } else {
 582                 return mt312_writereg(state, GPP_CTRL, 0x00);
 583         }
 584 }
 585
 586 static int mt312_sleep(struct dvb_frontend* fe)
 587 {
 588         struct mt312_state *state = fe->demodulator_priv;
 589         int ret;
 590         u8 config;
 591
 592         /* reset all registers to defaults */
 593         if ((ret = mt312_reset(state, 1)) < 0)
 594                 return ret;
 595
 596         if ((ret = mt312_readreg(state, CONFIG, &config)) < 0)
 597                 return ret;
 598
 599         /* enter standby */
 600         if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0)
 601                 return ret;
 602
 603         return 0;
 604 }
 605
 606 static int mt312_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 607 {
 608         fesettings->min_delay_ms = 50;
 609         fesettings->step_size = 0;
 610         fesettings->max_drift = 0;
 611         return 0;
 612 }
 613
 614 static void mt312_release(struct dvb_frontend* fe)
 615 {
 616         struct mt312_state* state = fe->demodulator_priv;
 617         kfree(state);
 618 }
 619
 620 static struct dvb_frontend_ops vp310_mt312_ops = {
 621
 622         .info = {
 623                 .name = "Zarlink ???? DVB-S",
 624                 .type = FE_QPSK,
 625                 .frequency_min = 950000,
 626                 .frequency_max = 2150000,
 627                 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
 628                 .symbol_rate_min = MT312_SYS_CLK / 128,
 629                 .symbol_rate_max = MT312_SYS_CLK / 2,
 630                 .caps =
 631                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 632                     FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 633                     FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
 634                     FE_CAN_RECOVER
 635         },
 636
 637         .release = mt312_release,
 638
 639         .init = mt312_initfe,
 640         .sleep = mt312_sleep,
 641         .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
 642
 643         .set_frontend = mt312_set_frontend,
 644         .get_frontend = mt312_get_frontend,
 645         .get_tune_settings = mt312_get_tune_settings,
 646
 647         .read_status = mt312_read_status,
 648         .read_ber = mt312_read_ber,
 649         .read_signal_strength = mt312_read_signal_strength,
 650         .read_snr = mt312_read_snr,
 651         .read_ucblocks = mt312_read_ucblocks,
 652
 653         .diseqc_send_master_cmd = mt312_send_master_cmd,
 654         .diseqc_send_burst = mt312_send_burst,
 655         .set_tone = mt312_set_tone,
 656         .set_voltage = mt312_set_voltage,
 657 };
 658
 659 struct dvb_frontend* vp310_mt312_attach(const struct mt312_config* config,
 660                                         struct i2c_adapter* i2c)
 661 {
 662         struct mt312_state* state = NULL;
 663
 664         /* allocate memory for the internal state */
 665         state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
 666         if (state == NULL)
 667                 goto error;
 668
 669         /* setup the state */
 670         state->config = config;
 671         state->i2c = i2c;
 672
 673         /* check if the demod is there */
 674         if (mt312_readreg(state, ID, &state->id) < 0)
 675                 goto error;
 676
 677         /* create dvb_frontend */
 678         memcpy(&state->frontend.ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
 679         state->frontend.demodulator_priv = state;
 680
 681         switch (state->id) {
 682         case ID_VP310:
 683                 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
 684                 state->frequency = 90;
 685                 break;
 686         case ID_MT312:
 687                 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
 688                 state->frequency = 60;
 689                 break;
 690         default:
 691                 printk (KERN_WARNING "Only Zarlink VP310/MT312 are supported chips.\n");
 692                 goto error;
 693         }
 694
 695         return &state->frontend;
 696
 697 error:
 698         kfree(state);
 699         return NULL;
 700 }
 701
 702 module_param(debug, int, 0644);
 703 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 704
 705 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
 706 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
 707 MODULE_LICENSE("GPL");
 708
 709 EXPORT_SYMBOL(vp310_mt312_attach);