release/src-rt-6.x/linux/linux-2.6/drivers/media/dvb/frontends/cx24110.c

   1         /*
   2     cx24110 - Single Chip Satellite Channel Receiver driver module
   3
   4     Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
   5     work
   6     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30
  31 #include "dvb_frontend.h"
  32 #include "cx24110.h"
  33
  34
  35 struct cx24110_state {
  36
  37         struct i2c_adapter* i2c;
  38
  39         const struct cx24110_config* config;
  40
  41         struct dvb_frontend frontend;
  42
  43         u32 lastber;
  44         u32 lastbler;
  45         u32 lastesn0;
  46 };
  47
  48 static int debug;
  49 #define dprintk(args...) \
  50         do { \
  51                 if (debug) printk(KERN_DEBUG "cx24110: " args); \
  52         } while (0)
  53
  54 static struct {u8 reg; u8 data;} cx24110_regdata[]=
  55                       /* Comments beginning with @ denote this value should
  56                          be the default */
  57         {{0x09,0x01}, /* SoftResetAll */
  58          {0x09,0x00}, /* release reset */
  59          {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
  60          {0x02,0x17}, /* middle byte " */
  61          {0x03,0x29}, /* LSB         " */
  62          {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
  63          {0x06,0xa5}, /* @ PLL 60MHz */
  64          {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
  65          {0x0a,0x00}, /* @ partial chip disables, do not set */
  66          {0x0b,0x01}, /* set output clock in gapped mode, start signal low
  67                          active for first byte */
  68          {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
  69          {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
  70          {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
  71                          to avoid starting the BER counter. Reset the
  72                          CRC test bit. Finite counting selected */
  73          {0x15,0xff}, /* @ size of the limited time window for RS BER
  74                          estimation. It is <value>*256 RS blocks, this
  75                          gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
  76          {0x16,0x00}, /* @ enable all RS output ports */
  77          {0x17,0x04}, /* @ time window allowed for the RS to sync */
  78          {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
  79                          for automatically */
  80                       /* leave the current code rate and normalization
  81                          registers as they are after reset... */
  82          {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
  83                          only once */
  84          {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
  85                          estimation. It is <value>*65536 channel bits, i.e.
  86                          approx. 38ms at 27.5MS/s, rate 3/4 */
  87          {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
  88                       /* leave front-end AGC parameters at default values */
  89                       /* leave decimation AGC parameters at default values */
  90          {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
  91          {0x36,0xff}, /* clear all interrupt pending flags */
  92          {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
  93          {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
  94                       /* leave the equalizer parameters on their default values */
  95                       /* leave the final AGC parameters on their default values */
  96          {0x41,0x00}, /* @ MSB of front-end derotator frequency */
  97          {0x42,0x00}, /* @ middle bytes " */
  98          {0x43,0x00}, /* @ LSB          " */
  99                       /* leave the carrier tracking loop parameters on default */
 100                       /* leave the bit timing loop parameters at gefault */
 101          {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
 102                       /* the cx24108 data sheet for symbol rates above 15MS/s */
 103          {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
 104          {0x61,0x95}, /* GPIO pins 1-4 have special function */
 105          {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
 106          {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
 107          {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
 108          {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
 109          {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
 110          {0x73,0x00}, /* @ disable several demod bypasses */
 111          {0x74,0x00}, /* @  " */
 112          {0x75,0x00}  /* @  " */
 113                       /* the remaining registers are for SEC */
 114         };
 115
 116
 117 static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
 118 {
 119         u8 buf [] = { reg, data };
 120         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 121         int err;
 122
 123         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 124                 dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
 125                          " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
 126                 return -EREMOTEIO;
 127         }
 128
 129         return 0;
 130 }
 131
 132 static int cx24110_readreg (struct cx24110_state* state, u8 reg)
 133 {
 134         int ret;
 135         u8 b0 [] = { reg };
 136         u8 b1 [] = { 0 };
 137         struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 138                            { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 139
 140         ret = i2c_transfer(state->i2c, msg, 2);
 141
 142         if (ret != 2) return ret;
 143
 144         return b1[0];
 145 }
 146
 147 static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
 148 {
 149 /* fixme (low): error handling */
 150
 151         switch (inversion) {
 152         case INVERSION_OFF:
 153                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 154                 /* AcqSpectrInvDis on. No idea why someone should want this */
 155                 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
 156                 /* Initial value 0 at start of acq */
 157                 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
 158                 /* current value 0 */
 159                 /* The cx24110 manual tells us this reg is read-only.
 160                    But what the heck... set it ayways */
 161                 break;
 162         case INVERSION_ON:
 163                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 164                 /* AcqSpectrInvDis on. No idea why someone should want this */
 165                 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
 166                 /* Initial value 1 at start of acq */
 167                 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
 168                 /* current value 1 */
 169                 break;
 170         case INVERSION_AUTO:
 171                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
 172                 /* AcqSpectrInvDis off. Leave initial & current states as is */
 173                 break;
 174         default:
 175                 return -EINVAL;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
 182 {
 183 /* fixme (low): error handling */
 184
 185         static const int rate[]={-1,1,2,3,5,7,-1};
 186         static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
 187         static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
 188
 189         /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
 190            searches all enabled viterbi rates, and can handle non-standard
 191            rates as well. */
 192
 193         if (fec>FEC_AUTO)
 194                 fec=FEC_AUTO;
 195
 196         if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
 197                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
 198                 /* clear AcqVitDis bit */
 199                 cx24110_writereg(state,0x18,0xae);
 200                 /* allow all DVB standard code rates */
 201                 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3);
 202                 /* set nominal Viterbi rate 3/4 */
 203                 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3);
 204                 /* set current Viterbi rate 3/4 */
 205                 cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
 206                 /* set the puncture registers for code rate 3/4 */
 207                 return 0;
 208         } else {
 209                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
 210                 /* set AcqVitDis bit */
 211                 if(rate[fec]>0) {
 212                         cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]);
 213                         /* set nominal Viterbi rate */
 214                         cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]);
 215                         /* set current Viterbi rate */
 216                         cx24110_writereg(state,0x1a,g1[fec]);
 217                         cx24110_writereg(state,0x1b,g2[fec]);
 218                         /* not sure if this is the right way: I always used AutoAcq mode */
 219            } else
 220                    return -EOPNOTSUPP;
 221 /* fixme (low): which is the correct return code? */
 222         };
 223         return 0;
 224 }
 225
 226 static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
 227 {
 228         int i;
 229
 230         i=cx24110_readreg(state,0x22)&0x0f;
 231         if(!(i&0x08)) {
 232                 return FEC_1_2 + i - 1;
 233         } else {
 234 /* fixme (low): a special code rate has been selected. In theory, we need to
 235    return a denominator value, a numerator value, and a pair of puncture
 236    maps to correctly describe this mode. But this should never happen in
 237    practice, because it cannot be set by cx24110_get_fec. */
 238            return FEC_NONE;
 239         }
 240 }
 241
 242 static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
 243 {
 244 /* fixme (low): add error handling */
 245         u32 ratio;
 246         u32 tmp, fclk, BDRI;
 247
 248         static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
 249         int i;
 250
 251         dprintk("cx24110 debug: entering %s(%d)\n",__FUNCTION__,srate);
 252         if (srate>90999000UL/2)
 253                 srate=90999000UL/2;
 254         if (srate<500000)
 255                 srate=500000;
 256
 257         for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
 258                 ;
 259         /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
 260            and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
 261            R06[3:0] PLLphaseDetGain */
 262         tmp=cx24110_readreg(state,0x07)&0xfc;
 263         if(srate<90999000UL/4) { /* sample rate 45MHz*/
 264                 cx24110_writereg(state,0x07,tmp);
 265                 cx24110_writereg(state,0x06,0x78);
 266                 fclk=90999000UL/2;
 267         } else if(srate<60666000UL/2) { /* sample rate 60MHz */
 268                 cx24110_writereg(state,0x07,tmp|0x1);
 269                 cx24110_writereg(state,0x06,0xa5);
 270                 fclk=60666000UL;
 271         } else if(srate<80888000UL/2) { /* sample rate 80MHz */
 272                 cx24110_writereg(state,0x07,tmp|0x2);
 273                 cx24110_writereg(state,0x06,0x87);
 274                 fclk=80888000UL;
 275         } else { /* sample rate 90MHz */
 276                 cx24110_writereg(state,0x07,tmp|0x3);
 277                 cx24110_writereg(state,0x06,0x78);
 278                 fclk=90999000UL;
 279         };
 280         dprintk("cx24110 debug: fclk %d Hz\n",fclk);
 281         /* we need to divide two integers with approx. 27 bits in 32 bit
 282            arithmetic giving a 25 bit result */
 283         /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
 284            also the most complex divisor. Hence, the dividend has,
 285            assuming 32bit unsigned arithmetic, 6 clear bits on top, the
 286            divisor 2 unused bits at the bottom. Also, the quotient is
 287            always less than 1/2. Borrowed from VES1893.c, of course */
 288
 289         tmp=srate<<6;
 290         BDRI=fclk>>2;
 291         ratio=(tmp/BDRI);
 292
 293         tmp=(tmp%BDRI)<<8;
 294         ratio=(ratio<<8)+(tmp/BDRI);
 295
 296         tmp=(tmp%BDRI)<<8;
 297         ratio=(ratio<<8)+(tmp/BDRI);
 298
 299         tmp=(tmp%BDRI)<<1;
 300         ratio=(ratio<<1)+(tmp/BDRI);
 301
 302         dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
 303         dprintk("fclk = %d\n", fclk);
 304         dprintk("ratio= %08x\n", ratio);
 305
 306         cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
 307         cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
 308         cx24110_writereg(state, 0x3, (ratio)&0xff);
 309
 310         return 0;
 311
 312 }
 313
 314 static int _cx24110_pll_write (struct dvb_frontend* fe, u8 *buf, int len)
 315 {
 316         struct cx24110_state *state = fe->demodulator_priv;
 317
 318         if (len != 3)
 319                 return -EINVAL;
 320
 321 /* tuner data is 21 bits long, must be left-aligned in data */
 322 /* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
 323 /* FIXME (low): add error handling, avoid infinite loops if HW fails... */
 324
 325         cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
 326         cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
 327
 328         /* if the auto tuner writer is still busy, clear it out */
 329         while (cx24110_readreg(state,0x6d)&0x80)
 330                 cx24110_writereg(state,0x72,0);
 331
 332         /* write the topmost 8 bits */
 333         cx24110_writereg(state,0x72,buf[0]);
 334
 335         /* wait for the send to be completed */
 336         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 337                 ;
 338
 339         /* send another 8 bytes */
 340         cx24110_writereg(state,0x72,buf[1]);
 341         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 342                 ;
 343
 344         /* and the topmost 5 bits of this byte */
 345         cx24110_writereg(state,0x72,buf[2]);
 346         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 347                 ;
 348
 349         /* now strobe the enable line once */
 350         cx24110_writereg(state,0x6d,0x32);
 351         cx24110_writereg(state,0x6d,0x30);
 352
 353         return 0;
 354 }
 355
 356 static int cx24110_initfe(struct dvb_frontend* fe)
 357 {
 358         struct cx24110_state *state = fe->demodulator_priv;
 359 /* fixme (low): error handling */
 360         int i;
 361
 362         dprintk("%s: init chip\n", __FUNCTION__);
 363
 364         for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
 365                 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
 366         };
 367
 368         return 0;
 369 }
 370
 371 static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 372 {
 373         struct cx24110_state *state = fe->demodulator_priv;
 374
 375         switch (voltage) {
 376         case SEC_VOLTAGE_13:
 377                 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
 378         case SEC_VOLTAGE_18:
 379                 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
 380         default:
 381                 return -EINVAL;
 382         };
 383 }
 384
 385 static int cx24110_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
 386 {
 387         int rv, bit;
 388         struct cx24110_state *state = fe->demodulator_priv;
 389         unsigned long timeout;
 390
 391         if (burst == SEC_MINI_A)
 392                 bit = 0x00;
 393         else if (burst == SEC_MINI_B)
 394                 bit = 0x08;
 395         else
 396                 return -EINVAL;
 397
 398         rv = cx24110_readreg(state, 0x77);
 399         if (!(rv & 0x04))
 400                 cx24110_writereg(state, 0x77, rv | 0x04);
 401
 402         rv = cx24110_readreg(state, 0x76);
 403         cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
 404         timeout = jiffies + msecs_to_jiffies(100);
 405         while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 406                 ; /* wait for LNB ready */
 407
 408         return 0;
 409 }
 410
 411 static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
 412                                    struct dvb_diseqc_master_cmd *cmd)
 413 {
 414         int i, rv;
 415         struct cx24110_state *state = fe->demodulator_priv;
 416         unsigned long timeout;
 417
 418         if (cmd->msg_len < 3 || cmd->msg_len > 6)
 419                 return -EINVAL;  /* not implemented */
 420
 421         for (i = 0; i < cmd->msg_len; i++)
 422                 cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
 423
 424         rv = cx24110_readreg(state, 0x77);
 425         if (rv & 0x04) {
 426                 cx24110_writereg(state, 0x77, rv & ~0x04);
 427                 msleep(30); /* reportedly fixes switching problems */
 428         }
 429
 430         rv = cx24110_readreg(state, 0x76);
 431
 432         cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
 433         timeout = jiffies + msecs_to_jiffies(100);
 434         while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 435                 ; /* wait for LNB ready */
 436
 437         return 0;
 438 }
 439
 440 static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
 441 {
 442         struct cx24110_state *state = fe->demodulator_priv;
 443
 444         int sync = cx24110_readreg (state, 0x55);
 445
 446         *status = 0;
 447
 448         if (sync & 0x10)
 449                 *status |= FE_HAS_SIGNAL;
 450
 451         if (sync & 0x08)
 452                 *status |= FE_HAS_CARRIER;
 453
 454         sync = cx24110_readreg (state, 0x08);
 455
 456         if (sync & 0x40)
 457                 *status |= FE_HAS_VITERBI;
 458
 459         if (sync & 0x20)
 460                 *status |= FE_HAS_SYNC;
 461
 462         if ((sync & 0x60) == 0x60)
 463                 *status |= FE_HAS_LOCK;
 464
 465         return 0;
 466 }
 467
 468 static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
 469 {
 470         struct cx24110_state *state = fe->demodulator_priv;
 471
 472         /* fixme (maybe): value range is 16 bit. Scale? */
 473         if(cx24110_readreg(state,0x24)&0x10) {
 474                 /* the Viterbi error counter has finished one counting window */
 475                 cx24110_writereg(state,0x24,0x04); /* select the ber reg */
 476                 state->lastber=cx24110_readreg(state,0x25)|
 477                         (cx24110_readreg(state,0x26)<<8);
 478                 cx24110_writereg(state,0x24,0x04); /* start new count window */
 479                 cx24110_writereg(state,0x24,0x14);
 480         }
 481         *ber = state->lastber;
 482
 483         return 0;
 484 }
 485
 486 static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 487 {
 488         struct cx24110_state *state = fe->demodulator_priv;
 489
 490 /* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
 491         u8 signal = cx24110_readreg (state, 0x27)+128;
 492         *signal_strength = (signal << 8) | signal;
 493
 494         return 0;
 495 }
 496
 497 static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
 498 {
 499         struct cx24110_state *state = fe->demodulator_priv;
 500
 501         /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
 502         if(cx24110_readreg(state,0x6a)&0x80) {
 503                 /* the Es/N0 error counter has finished one counting window */
 504                 state->lastesn0=cx24110_readreg(state,0x69)|
 505                         (cx24110_readreg(state,0x68)<<8);
 506                 cx24110_writereg(state,0x6a,0x84); /* start new count window */
 507         }
 508         *snr = state->lastesn0;
 509
 510         return 0;
 511 }
 512
 513 static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 514 {
 515         struct cx24110_state *state = fe->demodulator_priv;
 516         u32 lastbyer;
 517
 518         if(cx24110_readreg(state,0x10)&0x40) {
 519                 /* the RS error counter has finished one counting window */
 520                 cx24110_writereg(state,0x10,0x60); /* select the byer reg */
 521                 lastbyer=cx24110_readreg(state,0x12)|
 522                         (cx24110_readreg(state,0x13)<<8)|
 523                         (cx24110_readreg(state,0x14)<<16);
 524                 cx24110_writereg(state,0x10,0x70); /* select the bler reg */
 525                 state->lastbler=cx24110_readreg(state,0x12)|
 526                         (cx24110_readreg(state,0x13)<<8)|
 527                         (cx24110_readreg(state,0x14)<<16);
 528                 cx24110_writereg(state,0x10,0x20); /* start new count window */
 529         }
 530         *ucblocks = state->lastbler;
 531
 532         return 0;
 533 }
 534
 535 static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 536 {
 537         struct cx24110_state *state = fe->demodulator_priv;
 538
 539
 540         if (fe->ops.tuner_ops.set_params) {
 541                 fe->ops.tuner_ops.set_params(fe, p);
 542                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 543         }
 544
 545         cx24110_set_inversion (state, p->inversion);
 546         cx24110_set_fec (state, p->u.qpsk.fec_inner);
 547         cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate);
 548         cx24110_writereg(state,0x04,0x05); /* start aquisition */
 549
 550         return 0;
 551 }
 552
 553 static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 554 {
 555         struct cx24110_state *state = fe->demodulator_priv;
 556         s32 afc; unsigned sclk;
 557
 558 /* cannot read back tuner settings (freq). Need to have some private storage */
 559
 560         sclk = cx24110_readreg (state, 0x07) & 0x03;
 561 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
 562  * Need 64 bit arithmetic. Is thiss possible in the kernel? */
 563         if (sclk==0) sclk=90999000L/2L;
 564         else if (sclk==1) sclk=60666000L;
 565         else if (sclk==2) sclk=80888000L;
 566         else sclk=90999000L;
 567         sclk>>=8;
 568         afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
 569               ((sclk*cx24110_readreg (state, 0x45))>>8)+
 570               ((sclk*cx24110_readreg (state, 0x46))>>16);
 571
 572         p->frequency += afc;
 573         p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
 574                                 INVERSION_ON : INVERSION_OFF;
 575         p->u.qpsk.fec_inner = cx24110_get_fec (state);
 576
 577         return 0;
 578 }
 579
 580 static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 581 {
 582         struct cx24110_state *state = fe->demodulator_priv;
 583
 584         return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
 585 }
 586
 587 static void cx24110_release(struct dvb_frontend* fe)
 588 {
 589         struct cx24110_state* state = fe->demodulator_priv;
 590         kfree(state);
 591 }
 592
 593 static struct dvb_frontend_ops cx24110_ops;
 594
 595 struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
 596                                     struct i2c_adapter* i2c)
 597 {
 598         struct cx24110_state* state = NULL;
 599         int ret;
 600
 601         /* allocate memory for the internal state */
 602         state = kmalloc(sizeof(struct cx24110_state), GFP_KERNEL);
 603         if (state == NULL) goto error;
 604
 605         /* setup the state */
 606         state->config = config;
 607         state->i2c = i2c;
 608         state->lastber = 0;
 609         state->lastbler = 0;
 610         state->lastesn0 = 0;
 611
 612         /* check if the demod is there */
 613         ret = cx24110_readreg(state, 0x00);
 614         if ((ret != 0x5a) && (ret != 0x69)) goto error;
 615
 616         /* create dvb_frontend */
 617         memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
 618         state->frontend.demodulator_priv = state;
 619         return &state->frontend;
 620
 621 error:
 622         kfree(state);
 623         return NULL;
 624 }
 625
 626 static struct dvb_frontend_ops cx24110_ops = {
 627
 628         .info = {
 629                 .name = "Conexant CX24110 DVB-S",
 630                 .type = FE_QPSK,
 631                 .frequency_min = 950000,
 632                 .frequency_max = 2150000,
 633                 .frequency_stepsize = 1011,  /* kHz for QPSK frontends */
 634                 .frequency_tolerance = 29500,
 635                 .symbol_rate_min = 1000000,
 636                 .symbol_rate_max = 45000000,
 637                 .caps = FE_CAN_INVERSION_AUTO |
 638                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 639                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 640                         FE_CAN_QPSK | FE_CAN_RECOVER
 641         },
 642
 643         .release = cx24110_release,
 644
 645         .init = cx24110_initfe,
 646         .write = _cx24110_pll_write,
 647         .set_frontend = cx24110_set_frontend,
 648         .get_frontend = cx24110_get_frontend,
 649         .read_status = cx24110_read_status,
 650         .read_ber = cx24110_read_ber,
 651         .read_signal_strength = cx24110_read_signal_strength,
 652         .read_snr = cx24110_read_snr,
 653         .read_ucblocks = cx24110_read_ucblocks,
 654
 655         .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
 656         .set_tone = cx24110_set_tone,
 657         .set_voltage = cx24110_set_voltage,
 658         .diseqc_send_burst = cx24110_diseqc_send_burst,
 659 };
 660
 661 module_param(debug, int, 0644);
 662 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 663
 664 MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
 665 MODULE_AUTHOR("Peter Hettkamp");
 666 MODULE_LICENSE("GPL");
 667
 668 EXPORT_SYMBOL(cx24110_attach);