release/src-rt-6.x/linux/linux-2.6/drivers/ide/pci/siimage.c

   1 /*
   2  * linux/drivers/ide/pci/siimage.c              Version 1.12    Mar 10 2007
   3  *
   4  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   6  * Copyright (C) 2007           MontaVista Software, Inc.
   7  *
   8  *  May be copied or modified under the terms of the GNU General Public License
   9  *
  10  *  Documentation for CMD680:
  11  *  http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  12  *
  13  *  Documentation for SiI 3112:
  14  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  15  *
  16  *  Errata and other documentation only available under NDA.
  17  *
  18  *
  19  *  FAQ Items:
  20  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  21  *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
  22  *
  23  *      If you are using WD drives with SATA bridges you must set the
  24  *      drive to "Single". "Master" will hang
  25  *
  26  *      If you have strange problems with nVidia chipset systems please
  27  *      see the SI support documentation and update your system BIOS
  28  *      if neccessary
  29  *
  30  *  The Dell DRAC4 has some interesting features including effectively hot
  31  *  unplugging/replugging the virtual CD interface when the DRAC is reset.
  32  *  This often causes drivers/ide/siimage to panic but is ok with the rather
  33  *  smarter code in libata.
  34  */
  35
  36 #include <linux/types.h>
  37 #include <linux/module.h>
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/ide.h>
  42 #include <linux/init.h>
  43
  44 #include <asm/io.h>
  45
  46 /**
  47  *      pdev_is_sata            -       check if device is SATA
  48  *      @pdev:  PCI device to check
  49  *
  50  *      Returns true if this is a SATA controller
  51  */
  52
  53 static int pdev_is_sata(struct pci_dev *pdev)
  54 {
  55         switch(pdev->device)
  56         {
  57                 case PCI_DEVICE_ID_SII_3112:
  58                 case PCI_DEVICE_ID_SII_1210SA:
  59                         return 1;
  60                 case PCI_DEVICE_ID_SII_680:
  61                         return 0;
  62         }
  63         BUG();
  64         return 0;
  65 }
  66
  67 /**
  68  *      is_sata                 -       check if hwif is SATA
  69  *      @hwif:  interface to check
  70  *
  71  *      Returns true if this is a SATA controller
  72  */
  73
  74 static inline int is_sata(ide_hwif_t *hwif)
  75 {
  76         return pdev_is_sata(hwif->pci_dev);
  77 }
  78
  79 /**
  80  *      siimage_selreg          -       return register base
  81  *      @hwif: interface
  82  *      @r: config offset
  83  *
  84  *      Turn a config register offset into the right address in either
  85  *      PCI space or MMIO space to access the control register in question
  86  *      Thankfully this is a configuration operation so isnt performance
  87  *      criticial.
  88  */
  89
  90 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  91 {
  92         unsigned long base = (unsigned long)hwif->hwif_data;
  93         base += 0xA0 + r;
  94         if(hwif->mmio)
  95                 base += (hwif->channel << 6);
  96         else
  97                 base += (hwif->channel << 4);
  98         return base;
  99 }
 100
 101 /**
 102  *      siimage_seldev          -       return register base
 103  *      @hwif: interface
 104  *      @r: config offset
 105  *
 106  *      Turn a config register offset into the right address in either
 107  *      PCI space or MMIO space to access the control register in question
 108  *      including accounting for the unit shift.
 109  */
 110
 111 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 112 {
 113         ide_hwif_t *hwif        = HWIF(drive);
 114         unsigned long base = (unsigned long)hwif->hwif_data;
 115         base += 0xA0 + r;
 116         if(hwif->mmio)
 117                 base += (hwif->channel << 6);
 118         else
 119                 base += (hwif->channel << 4);
 120         base |= drive->select.b.unit << drive->select.b.unit;
 121         return base;
 122 }
 123
 124 /**
 125  *      sil_udma_filter         -       compute UDMA mask
 126  *      @drive: IDE device
 127  *
 128  *      Compute the available UDMA speeds for the device on the interface.
 129  *
 130  *      For the CMD680 this depends on the clocking mode (scsc), for the
 131  *      SI3112 SATA controller life is a bit simpler.
 132  */
 133
 134 static u8 sil_udma_filter(ide_drive_t *drive)
 135 {
 136         ide_hwif_t *hwif = drive->hwif;
 137         unsigned long base = (unsigned long) hwif->hwif_data;
 138         u8 mask = 0, scsc = 0;
 139
 140         if (hwif->mmio)
 141                 scsc = hwif->INB(base + 0x4A);
 142         else
 143                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 144
 145         if (is_sata(hwif)) {
 146                 mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f;
 147                 goto out;
 148         }
 149
 150         if ((scsc & 0x30) == 0x10)      /* 133 */
 151                 mask = 0x7f;
 152         else if ((scsc & 0x30) == 0x20) /* 2xPCI */
 153                 mask = 0x7f;
 154         else if ((scsc & 0x30) == 0x00) /* 100 */
 155                 mask = 0x3f;
 156         else    /* Disabled ? */
 157                 BUG();
 158 out:
 159         return mask;
 160 }
 161
 162 /**
 163  *      siimage_taskfile_timing -       turn timing data to a mode
 164  *      @hwif: interface to query
 165  *
 166  *      Read the timing data for the interface and return the
 167  *      mode that is being used.
 168  */
 169
 170 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
 171 {
 172         u16 timing      = 0x328a;
 173         unsigned long addr = siimage_selreg(hwif, 2);
 174
 175         if (hwif->mmio)
 176                 timing = hwif->INW(addr);
 177         else
 178                 pci_read_config_word(hwif->pci_dev, addr, &timing);
 179
 180         switch (timing) {
 181                 case 0x10c1:    return 4;
 182                 case 0x10c3:    return 3;
 183                 case 0x1104:
 184                 case 0x1281:    return 2;
 185                 case 0x2283:    return 1;
 186                 case 0x328a:
 187                 default:        return 0;
 188         }
 189 }
 190
 191 /**
 192  *      simmage_tuneproc        -       tune a drive
 193  *      @drive: drive to tune
 194  *      @mode_wanted: the target operating mode
 195  *
 196  *      Load the timing settings for this device mode into the
 197  *      controller. If we are in PIO mode 3 or 4 turn on IORDY
 198  *      monitoring (bit 9). The TF timing is bits 31:16
 199  */
 200
 201 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
 202 {
 203         ide_hwif_t *hwif        = HWIF(drive);
 204         u32 speedt              = 0;
 205         u16 speedp              = 0;
 206         unsigned long addr      = siimage_seldev(drive, 0x04);
 207         unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
 208
 209         /* cheat for now and use the docs */
 210         switch (mode_wanted) {
 211         case 4:
 212                 speedp = 0x10c1;
 213                 speedt = 0x10c1;
 214                 break;
 215         case 3:
 216                 speedp = 0x10c3;
 217                 speedt = 0x10c3;
 218                 break;
 219         case 2:
 220                 speedp = 0x1104;
 221                 speedt = 0x1281;
 222                 break;
 223         case 1:
 224                 speedp = 0x2283;
 225                 speedt = 0x2283;
 226                 break;
 227         case 0:
 228         default:
 229                 speedp = 0x328a;
 230                 speedt = 0x328a;
 231                 break;
 232         }
 233
 234         if (hwif->mmio) {
 235                 hwif->OUTW(speedp, addr);
 236                 hwif->OUTW(speedt, tfaddr);
 237                 /* Now set up IORDY */
 238                 if(mode_wanted == 3 || mode_wanted == 4)
 239                         hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
 240                 else
 241                         hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
 242         } else {
 243                 pci_write_config_word(hwif->pci_dev, addr, speedp);
 244                 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
 245                 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
 246                 speedp &= ~0x200;
 247                 /* Set IORDY for mode 3 or 4 */
 248                 if(mode_wanted == 3 || mode_wanted == 4)
 249                         speedp |= 0x200;
 250                 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
 251         }
 252 }
 253
 254 /**
 255  *      config_siimage_chipset_for_pio  -       set drive timings
 256  *      @drive: drive to tune
 257  *      @speed we want
 258  *
 259  *      Compute the best pio mode we can for a given device. Also honour
 260  *      the timings for the driver when dealing with mixed devices. Some
 261  *      of this is ugly but its all wrapped up here
 262  *
 263  *      The SI680 can also do VDMA - we need to start using that
 264  *
 265  *      FIXME: we use the BIOS channel timings to avoid driving the task
 266  *      files too fast at the disk. We need to compute the master/slave
 267  *      drive PIO mode properly so that we can up the speed on a hotplug
 268  *      system.
 269  */
 270
 271 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 272 {
 273         u8 channel_timings      = siimage_taskfile_timing(HWIF(drive));
 274         u8 speed = 0, set_pio   = ide_get_best_pio_mode(drive, 4, 5, NULL);
 275
 276         /* WARNING PIO timing mess is going to happen b/w devices, argh */
 277         if ((channel_timings != set_pio) && (set_pio > channel_timings))
 278                 set_pio = channel_timings;
 279
 280         siimage_tuneproc(drive, set_pio);
 281         speed = XFER_PIO_0 + set_pio;
 282         if (set_speed)
 283                 (void) ide_config_drive_speed(drive, speed);
 284 }
 285
 286 /**
 287  *      siimage_tune_chipset    -       set controller timings
 288  *      @drive: Drive to set up
 289  *      @xferspeed: speed we want to achieve
 290  *
 291  *      Tune the SII chipset for the desired mode. If we can't achieve
 292  *      the desired mode then tune for a lower one, but ultimately
 293  *      make the thing work.
 294  */
 295
 296 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
 297 {
 298         u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 299         u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 300         u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
 301
 302         ide_hwif_t *hwif        = HWIF(drive);
 303         u16 ultra = 0, multi    = 0;
 304         u8 mode = 0, unit       = drive->select.b.unit;
 305         u8 speed                = ide_rate_filter(drive, xferspeed);
 306         unsigned long base      = (unsigned long)hwif->hwif_data;
 307         u8 scsc = 0, addr_mask  = ((hwif->channel) ?
 308                                     ((hwif->mmio) ? 0xF4 : 0x84) :
 309                                     ((hwif->mmio) ? 0xB4 : 0x80));
 310
 311         unsigned long ma        = siimage_seldev(drive, 0x08);
 312         unsigned long ua        = siimage_seldev(drive, 0x0C);
 313
 314         if (hwif->mmio) {
 315                 scsc = hwif->INB(base + 0x4A);
 316                 mode = hwif->INB(base + addr_mask);
 317                 multi = hwif->INW(ma);
 318                 ultra = hwif->INW(ua);
 319         } else {
 320                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 321                 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
 322                 pci_read_config_word(hwif->pci_dev, ma, &multi);
 323                 pci_read_config_word(hwif->pci_dev, ua, &ultra);
 324         }
 325
 326         mode &= ~((unit) ? 0x30 : 0x03);
 327         ultra &= ~0x3F;
 328         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 329
 330         scsc = is_sata(hwif) ? 1 : scsc;
 331
 332         switch(speed) {
 333                 case XFER_PIO_4:
 334                 case XFER_PIO_3:
 335                 case XFER_PIO_2:
 336                 case XFER_PIO_1:
 337                 case XFER_PIO_0:
 338                         siimage_tuneproc(drive, (speed - XFER_PIO_0));
 339                         mode |= ((unit) ? 0x10 : 0x01);
 340                         break;
 341                 case XFER_MW_DMA_2:
 342                 case XFER_MW_DMA_1:
 343                 case XFER_MW_DMA_0:
 344                         multi = dma[speed - XFER_MW_DMA_0];
 345                         mode |= ((unit) ? 0x20 : 0x02);
 346                         config_siimage_chipset_for_pio(drive, 0);
 347                         break;
 348                 case XFER_UDMA_6:
 349                 case XFER_UDMA_5:
 350                 case XFER_UDMA_4:
 351                 case XFER_UDMA_3:
 352                 case XFER_UDMA_2:
 353                 case XFER_UDMA_1:
 354                 case XFER_UDMA_0:
 355                         multi = dma[2];
 356                         ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
 357                                            (ultra5[speed - XFER_UDMA_0]));
 358                         mode |= ((unit) ? 0x30 : 0x03);
 359                         config_siimage_chipset_for_pio(drive, 0);
 360                         break;
 361                 default:
 362                         return 1;
 363         }
 364
 365         if (hwif->mmio) {
 366                 hwif->OUTB(mode, base + addr_mask);
 367                 hwif->OUTW(multi, ma);
 368                 hwif->OUTW(ultra, ua);
 369         } else {
 370                 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
 371                 pci_write_config_word(hwif->pci_dev, ma, multi);
 372                 pci_write_config_word(hwif->pci_dev, ua, ultra);
 373         }
 374         return (ide_config_drive_speed(drive, speed));
 375 }
 376
 377 /**
 378  *      siimage_configure_drive_for_dma -       set up for DMA transfers
 379  *      @drive: drive we are going to set up
 380  *
 381  *      Set up the drive for DMA, tune the controller and drive as
 382  *      required. If the drive isn't suitable for DMA or we hit
 383  *      other problems then we will drop down to PIO and set up
 384  *      PIO appropriately
 385  */
 386
 387 static int siimage_config_drive_for_dma (ide_drive_t *drive)
 388 {
 389         if (ide_tune_dma(drive))
 390                 return 0;
 391
 392         if (ide_use_fast_pio(drive))
 393                 config_siimage_chipset_for_pio(drive, 1);
 394
 395         return -1;
 396 }
 397
 398 /* returns 1 if dma irq issued, 0 otherwise */
 399 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
 400 {
 401         ide_hwif_t *hwif        = HWIF(drive);
 402         u8 dma_altstat          = 0;
 403         unsigned long addr      = siimage_selreg(hwif, 1);
 404
 405         /* return 1 if INTR asserted */
 406         if ((hwif->INB(hwif->dma_status) & 4) == 4)
 407                 return 1;
 408
 409         /* return 1 if Device INTR asserted */
 410         pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
 411         if (dma_altstat & 8)
 412                 return 0;       //return 1;
 413         return 0;
 414 }
 415
 416 /**
 417  *      siimage_mmio_ide_dma_test_irq   -       check we caused an IRQ
 418  *      @drive: drive we are testing
 419  *
 420  *      Check if we caused an IDE DMA interrupt. We may also have caused
 421  *      SATA status interrupts, if so we clean them up and continue.
 422  */
 423
 424 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
 425 {
 426         ide_hwif_t *hwif        = HWIF(drive);
 427         unsigned long base      = (unsigned long)hwif->hwif_data;
 428         unsigned long addr      = siimage_selreg(hwif, 0x1);
 429
 430         if (SATA_ERROR_REG) {
 431                 u32 ext_stat = readl((void __iomem *)(base + 0x10));
 432                 u8 watchdog = 0;
 433                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 434                         u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
 435                         writel(sata_error, (void __iomem *)SATA_ERROR_REG);
 436                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
 437                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 438                                 "watchdog = %d, %s\n",
 439                                 drive->name, sata_error, watchdog,
 440                                 __FUNCTION__);
 441
 442                 } else {
 443                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
 444                 }
 445                 ext_stat >>= 16;
 446
 447                 if (!(ext_stat & 0x0404) && !watchdog)
 448                         return 0;
 449         }
 450
 451         /* return 1 if INTR asserted */
 452         if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
 453                 return 1;
 454
 455         /* return 1 if Device INTR asserted */
 456         if ((readb((void __iomem *)addr) & 8) == 8)
 457                 return 0;       //return 1;
 458
 459         return 0;
 460 }
 461
 462 /**
 463  *      siimage_busproc         -       bus isolation ioctl
 464  *      @drive: drive to isolate/restore
 465  *      @state: bus state to set
 466  *
 467  *      Used by the SII3112 to handle bus isolation. As this is a
 468  *      SATA controller the work required is quite limited, we
 469  *      just have to clean up the statistics
 470  */
 471
 472 static int siimage_busproc (ide_drive_t * drive, int state)
 473 {
 474         ide_hwif_t *hwif        = HWIF(drive);
 475         u32 stat_config         = 0;
 476         unsigned long addr      = siimage_selreg(hwif, 0);
 477
 478         if (hwif->mmio)
 479                 stat_config = readl((void __iomem *)addr);
 480         else
 481                 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
 482
 483         switch (state) {
 484                 case BUSSTATE_ON:
 485                         hwif->drives[0].failures = 0;
 486                         hwif->drives[1].failures = 0;
 487                         break;
 488                 case BUSSTATE_OFF:
 489                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 490                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 491                         break;
 492                 case BUSSTATE_TRISTATE:
 493                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 494                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 495                         break;
 496                 default:
 497                         return -EINVAL;
 498         }
 499         hwif->bus_state = state;
 500         return 0;
 501 }
 502
 503 /**
 504  *      siimage_reset_poll      -       wait for sata reset
 505  *      @drive: drive we are resetting
 506  *
 507  *      Poll the SATA phy and see whether it has come back from the dead
 508  *      yet.
 509  */
 510
 511 static int siimage_reset_poll (ide_drive_t *drive)
 512 {
 513         if (SATA_STATUS_REG) {
 514                 ide_hwif_t *hwif        = HWIF(drive);
 515
 516                 /* SATA_STATUS_REG is valid only when in MMIO mode */
 517                 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
 518                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 519                                 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
 520                         HWGROUP(drive)->polling = 0;
 521                         return ide_started;
 522                 }
 523                 return 0;
 524         } else {
 525                 return 0;
 526         }
 527 }
 528
 529 /**
 530  *      siimage_pre_reset       -       reset hook
 531  *      @drive: IDE device being reset
 532  *
 533  *      For the SATA devices we need to handle recalibration/geometry
 534  *      differently
 535  */
 536
 537 static void siimage_pre_reset (ide_drive_t *drive)
 538 {
 539         if (drive->media != ide_disk)
 540                 return;
 541
 542         if (is_sata(HWIF(drive)))
 543         {
 544                 drive->special.b.set_geometry = 0;
 545                 drive->special.b.recalibrate = 0;
 546         }
 547 }
 548
 549 /**
 550  *      siimage_reset   -       reset a device on an siimage controller
 551  *      @drive: drive to reset
 552  *
 553  *      Perform a controller level reset fo the device. For
 554  *      SATA we must also check the PHY.
 555  */
 556
 557 static void siimage_reset (ide_drive_t *drive)
 558 {
 559         ide_hwif_t *hwif        = HWIF(drive);
 560         u8 reset                = 0;
 561         unsigned long addr      = siimage_selreg(hwif, 0);
 562
 563         if (hwif->mmio) {
 564                 reset = hwif->INB(addr);
 565                 hwif->OUTB((reset|0x03), addr);
 566                 /* FIXME:posting */
 567                 udelay(25);
 568                 hwif->OUTB(reset, addr);
 569                 (void) hwif->INB(addr);
 570         } else {
 571                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 572                 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
 573                 udelay(25);
 574                 pci_write_config_byte(hwif->pci_dev, addr, reset);
 575                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 576         }
 577
 578         if (SATA_STATUS_REG) {
 579                 /* SATA_STATUS_REG is valid only when in MMIO mode */
 580                 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
 581                 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
 582                         hwif->name, sata_stat, __FUNCTION__);
 583                 if (!(sata_stat)) {
 584                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 585                                 hwif->name, sata_stat);
 586                         drive->failures++;
 587                 }
 588         }
 589
 590 }
 591
 592 /**
 593  *      proc_reports_siimage            -       add siimage controller to proc
 594  *      @dev: PCI device
 595  *      @clocking: SCSC value
 596  *      @name: controller name
 597  *
 598  *      Report the clocking mode of the controller and add it to
 599  *      the /proc interface layer
 600  */
 601
 602 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
 603 {
 604         if (!pdev_is_sata(dev)) {
 605                 printk(KERN_INFO "%s: BASE CLOCK ", name);
 606                 clocking &= 0x03;
 607                 switch (clocking) {
 608                         case 0x03: printk("DISABLED!\n"); break;
 609                         case 0x02: printk("== 2X PCI\n"); break;
 610                         case 0x01: printk("== 133\n"); break;
 611                         case 0x00: printk("== 100\n"); break;
 612                 }
 613         }
 614 }
 615
 616 /**
 617  *      setup_mmio_siimage      -       switch an SI controller into MMIO
 618  *      @dev: PCI device we are configuring
 619  *      @name: device name
 620  *
 621  *      Attempt to put the device into mmio mode. There are some slight
 622  *      complications here with certain systems where the mmio bar isnt
 623  *      mapped so we have to be sure we can fall back to I/O.
 624  */
 625
 626 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
 627 {
 628         unsigned long bar5      = pci_resource_start(dev, 5);
 629         unsigned long barsize   = pci_resource_len(dev, 5);
 630         u8 tmpbyte      = 0;
 631         void __iomem *ioaddr;
 632         u32 tmp, irq_mask;
 633
 634         /*
 635          *      Drop back to PIO if we can't map the mmio. Some
 636          *      systems seem to get terminally confused in the PCI
 637          *      spaces.
 638          */
 639
 640         if(!request_mem_region(bar5, barsize, name))
 641         {
 642                 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 643                 return 0;
 644         }
 645
 646         ioaddr = ioremap(bar5, barsize);
 647
 648         if (ioaddr == NULL)
 649         {
 650                 release_mem_region(bar5, barsize);
 651                 return 0;
 652         }
 653
 654         pci_set_master(dev);
 655         pci_set_drvdata(dev, (void *) ioaddr);
 656
 657         if (pdev_is_sata(dev)) {
 658                 /* make sure IDE0/1 interrupts are not masked */
 659                 irq_mask = (1 << 22) | (1 << 23);
 660                 tmp = readl(ioaddr + 0x48);
 661                 if (tmp & irq_mask) {
 662                         tmp &= ~irq_mask;
 663                         writel(tmp, ioaddr + 0x48);
 664                         readl(ioaddr + 0x48); /* flush */
 665                 }
 666                 writel(0, ioaddr + 0x148);
 667                 writel(0, ioaddr + 0x1C8);
 668         }
 669
 670         writeb(0, ioaddr + 0xB4);
 671         writeb(0, ioaddr + 0xF4);
 672         tmpbyte = readb(ioaddr + 0x4A);
 673
 674         switch(tmpbyte & 0x30) {
 675                 case 0x00:
 676                         /* In 100 MHz clocking, try and switch to 133 */
 677                         writeb(tmpbyte|0x10, ioaddr + 0x4A);
 678                         break;
 679                 case 0x10:
 680                         /* On 133Mhz clocking */
 681                         break;
 682                 case 0x20:
 683                         /* On PCIx2 clocking */
 684                         break;
 685                 case 0x30:
 686                         /* Clocking is disabled */
 687                         /* 133 clock attempt to force it on */
 688                         writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
 689                         break;
 690         }
 691
 692         writeb(      0x72, ioaddr + 0xA1);
 693         writew(    0x328A, ioaddr + 0xA2);
 694         writel(0x62DD62DD, ioaddr + 0xA4);
 695         writel(0x43924392, ioaddr + 0xA8);
 696         writel(0x40094009, ioaddr + 0xAC);
 697         writeb(      0x72, ioaddr + 0xE1);
 698         writew(    0x328A, ioaddr + 0xE2);
 699         writel(0x62DD62DD, ioaddr + 0xE4);
 700         writel(0x43924392, ioaddr + 0xE8);
 701         writel(0x40094009, ioaddr + 0xEC);
 702
 703         if (pdev_is_sata(dev)) {
 704                 writel(0xFFFF0000, ioaddr + 0x108);
 705                 writel(0xFFFF0000, ioaddr + 0x188);
 706                 writel(0x00680000, ioaddr + 0x148);
 707                 writel(0x00680000, ioaddr + 0x1C8);
 708         }
 709
 710         tmpbyte = readb(ioaddr + 0x4A);
 711
 712         proc_reports_siimage(dev, (tmpbyte>>4), name);
 713         return 1;
 714 }
 715
 716 /**
 717  *      init_chipset_siimage    -       set up an SI device
 718  *      @dev: PCI device
 719  *      @name: device name
 720  *
 721  *      Perform the initial PCI set up for this device. Attempt to switch
 722  *      to 133MHz clocking if the system isn't already set up to do it.
 723  */
 724
 725 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 726 {
 727         u32 class_rev   = 0;
 728         u8 tmpbyte      = 0;
 729         u8 BA5_EN       = 0;
 730
 731         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 732         class_rev &= 0xff;
 733         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
 734
 735         pci_read_config_byte(dev, 0x8A, &BA5_EN);
 736         if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
 737                 if (setup_mmio_siimage(dev, name)) {
 738                         return 0;
 739                 }
 740         }
 741
 742         pci_write_config_byte(dev, 0x80, 0x00);
 743         pci_write_config_byte(dev, 0x84, 0x00);
 744         pci_read_config_byte(dev, 0x8A, &tmpbyte);
 745         switch(tmpbyte & 0x30) {
 746                 case 0x00:
 747                         /* 133 clock attempt to force it on */
 748                         pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
 749                 case 0x30:
 750                         /* if clocking is disabled */
 751                         /* 133 clock attempt to force it on */
 752                         pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
 753                 case 0x10:
 754                         /* 133 already */
 755                         break;
 756                 case 0x20:
 757                         /* BIOS set PCI x2 clocking */
 758                         break;
 759         }
 760
 761         pci_read_config_byte(dev,   0x8A, &tmpbyte);
 762
 763         pci_write_config_byte(dev,  0xA1, 0x72);
 764         pci_write_config_word(dev,  0xA2, 0x328A);
 765         pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
 766         pci_write_config_dword(dev, 0xA8, 0x43924392);
 767         pci_write_config_dword(dev, 0xAC, 0x40094009);
 768         pci_write_config_byte(dev,  0xB1, 0x72);
 769         pci_write_config_word(dev,  0xB2, 0x328A);
 770         pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
 771         pci_write_config_dword(dev, 0xB8, 0x43924392);
 772         pci_write_config_dword(dev, 0xBC, 0x40094009);
 773
 774         proc_reports_siimage(dev, (tmpbyte>>4), name);
 775         return 0;
 776 }
 777
 778 /**
 779  *      init_mmio_iops_siimage  -       set up the iops for MMIO
 780  *      @hwif: interface to set up
 781  *
 782  *      The basic setup here is fairly simple, we can use standard MMIO
 783  *      operations. However we do have to set the taskfile register offsets
 784  *      by hand as there isnt a standard defined layout for them this
 785  *      time.
 786  *
 787  *      The hardware supports buffered taskfiles and also some rather nice
 788  *      extended PRD tables. For better SI3112 support use the libata driver
 789  */
 790
 791 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 792 {
 793         struct pci_dev *dev     = hwif->pci_dev;
 794         void *addr              = pci_get_drvdata(dev);
 795         u8 ch                   = hwif->channel;
 796         hw_regs_t               hw;
 797         unsigned long           base;
 798
 799         /*
 800          *      Fill in the basic HWIF bits
 801          */
 802
 803         default_hwif_mmiops(hwif);
 804         hwif->hwif_data                 = addr;
 805
 806         /*
 807          *      Now set up the hw. We have to do this ourselves as
 808          *      the MMIO layout isnt the same as the standard port
 809          *      based I/O
 810          */
 811
 812         memset(&hw, 0, sizeof(hw_regs_t));
 813
 814         base = (unsigned long)addr;
 815         if (ch)
 816                 base += 0xC0;
 817         else
 818                 base += 0x80;
 819
 820         /*
 821          *      The buffered task file doesn't have status/control
 822          *      so we can't currently use it sanely since we want to
 823          *      use LBA48 mode.
 824          */
 825         hw.io_ports[IDE_DATA_OFFSET]    = base;
 826         hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
 827         hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
 828         hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
 829         hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
 830         hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
 831         hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
 832         hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
 833         hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
 834
 835         hw.io_ports[IDE_IRQ_OFFSET]     = 0;
 836
 837         if (pdev_is_sata(dev)) {
 838                 base = (unsigned long)addr;
 839                 if (ch)
 840                         base += 0x80;
 841                 hwif->sata_scr[SATA_STATUS_OFFSET]      = base + 0x104;
 842                 hwif->sata_scr[SATA_ERROR_OFFSET]       = base + 0x108;
 843                 hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
 844                 hwif->sata_misc[SATA_MISC_OFFSET]       = base + 0x140;
 845                 hwif->sata_misc[SATA_PHY_OFFSET]        = base + 0x144;
 846                 hwif->sata_misc[SATA_IEN_OFFSET]        = base + 0x148;
 847         }
 848
 849         hw.irq                          = hwif->pci_dev->irq;
 850
 851         memcpy(&hwif->hw, &hw, sizeof(hw));
 852         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
 853
 854         hwif->irq                       = hw.irq;
 855
 856         base = (unsigned long) addr;
 857
 858         hwif->dma_base                  = base + (ch ? 0x08 : 0x00);
 859
 860         hwif->mmio = 1;
 861 }
 862
 863 static int is_dev_seagate_sata(ide_drive_t *drive)
 864 {
 865         const char *s = &drive->id->model[0];
 866         unsigned len;
 867
 868         if (!drive->present)
 869                 return 0;
 870
 871         len = strnlen(s, sizeof(drive->id->model));
 872
 873         if ((len > 4) && (!memcmp(s, "ST", 2))) {
 874                 if ((!memcmp(s + len - 2, "AS", 2)) ||
 875                     (!memcmp(s + len - 3, "ASL", 3))) {
 876                         printk(KERN_INFO "%s: applying pessimistic Seagate "
 877                                          "errata fix\n", drive->name);
 878                         return 1;
 879                 }
 880         }
 881         return 0;
 882 }
 883
 884 /**
 885  *      siimage_fixup           -       post probe fixups
 886  *      @hwif: interface to fix up
 887  *
 888  *      Called after drive probe we use this to decide whether the
 889  *      Seagate fixup must be applied. This used to be in init_iops but
 890  *      that can occur before we know what drives are present.
 891  */
 892
 893 static void __devinit siimage_fixup(ide_hwif_t *hwif)
 894 {
 895         /* Try and raise the rqsize */
 896         if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
 897                 hwif->rqsize = 128;
 898 }
 899
 900 /**
 901  *      init_iops_siimage       -       set up iops
 902  *      @hwif: interface to set up
 903  *
 904  *      Do the basic setup for the SIIMAGE hardware interface
 905  *      and then do the MMIO setup if we can. This is the first
 906  *      look in we get for setting up the hwif so that we
 907  *      can get the iops right before using them.
 908  */
 909
 910 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
 911 {
 912         struct pci_dev *dev     = hwif->pci_dev;
 913         u32 class_rev           = 0;
 914
 915         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 916         class_rev &= 0xff;
 917
 918         hwif->hwif_data = NULL;
 919
 920         /* Pessimal until we finish probing */
 921         hwif->rqsize = 15;
 922
 923         if (pci_get_drvdata(dev) == NULL)
 924                 return;
 925         init_mmio_iops_siimage(hwif);
 926 }
 927
 928 /**
 929  *      ata66_siimage   -       check for 80 pin cable
 930  *      @hwif: interface to check
 931  *
 932  *      Check for the presence of an ATA66 capable cable on the
 933  *      interface.
 934  */
 935
 936 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
 937 {
 938         unsigned long addr = siimage_selreg(hwif, 0);
 939         if (pci_get_drvdata(hwif->pci_dev) == NULL) {
 940                 u8 ata66 = 0;
 941                 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
 942                 return (ata66 & 0x01) ? 1 : 0;
 943         }
 944
 945         return (hwif->INB(addr) & 0x01) ? 1 : 0;
 946 }
 947
 948 /**
 949  *      init_hwif_siimage       -       set up hwif structs
 950  *      @hwif: interface to set up
 951  *
 952  *      We do the basic set up of the interface structure. The SIIMAGE
 953  *      requires several custom handlers so we override the default
 954  *      ide DMA handlers appropriately
 955  */
 956
 957 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
 958 {
 959         hwif->autodma = 0;
 960
 961         hwif->resetproc = &siimage_reset;
 962         hwif->speedproc = &siimage_tune_chipset;
 963         hwif->tuneproc  = &siimage_tuneproc;
 964         hwif->reset_poll = &siimage_reset_poll;
 965         hwif->pre_reset = &siimage_pre_reset;
 966         hwif->udma_filter = &sil_udma_filter;
 967
 968         if(is_sata(hwif)) {
 969                 static int first = 1;
 970
 971                 hwif->busproc   = &siimage_busproc;
 972
 973                 if (first) {
 974                         printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
 975                         first = 0;
 976                 }
 977         }
 978         if (!hwif->dma_base) {
 979                 hwif->drives[0].autotune = 1;
 980                 hwif->drives[1].autotune = 1;
 981                 return;
 982         }
 983
 984         hwif->ultra_mask = 0x7f;
 985         hwif->mwdma_mask = 0x07;
 986
 987         if (!is_sata(hwif))
 988                 hwif->atapi_dma = 1;
 989
 990         hwif->ide_dma_check = &siimage_config_drive_for_dma;
 991         if (!(hwif->udma_four))
 992                 hwif->udma_four = ata66_siimage(hwif);
 993
 994         if (hwif->mmio) {
 995                 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
 996         } else {
 997                 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
 998         }
 999
1000         /*
1001          *      The BIOS often doesn't set up DMA on this controller
1002          *      so we always do it.
1003          */
1004
1005         hwif->autodma = 1;
1006         hwif->drives[0].autodma = hwif->autodma;
1007         hwif->drives[1].autodma = hwif->autodma;
1008 }
1009
1010 #define DECLARE_SII_DEV(name_str)                       \
1011         {                                               \
1012                 .name           = name_str,             \
1013                 .init_chipset   = init_chipset_siimage, \
1014                 .init_iops      = init_iops_siimage,    \
1015                 .init_hwif      = init_hwif_siimage,    \
1016                 .fixup          = siimage_fixup,        \
1017                 .channels       = 2,                    \
1018                 .autodma        = AUTODMA,              \
1019                 .bootable       = ON_BOARD,             \
1020         }
1021
1022 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1023         /* 0 */ DECLARE_SII_DEV("SiI680"),
1024         /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1025         /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1026 };
1027
1028 /**
1029  *      siimage_init_one        -       pci layer discovery entry
1030  *      @dev: PCI device
1031  *      @id: ident table entry
1032  *
1033  *      Called by the PCI code when it finds an SI680 or SI3112 controller.
1034  *      We then use the IDE PCI generic helper to do most of the work.
1035  */
1036
1037 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1038 {
1039         return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1040 }
1041
1042 static struct pci_device_id siimage_pci_tbl[] = {
1043         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1044 #ifdef CONFIG_BLK_DEV_IDE_SATA
1045         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1046         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1047 #endif
1048         { 0, },
1049 };
1050 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1051
1052 static struct pci_driver driver = {
1053         .name           = "SiI_IDE",
1054         .id_table       = siimage_pci_tbl,
1055         .probe          = siimage_init_one,
1056 };
1057
1058 static int __init siimage_ide_init(void)
1059 {
1060         return ide_pci_register_driver(&driver);
1061 }
1062
1063 module_init(siimage_ide_init);
1064
1065 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1066 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1067 MODULE_LICENSE("GPL");