2 * linux/drivers/ide/pci/serverworks.c Version 0.11 Jun 2 2007
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
11 * RCC/ServerWorks IDE driver for Linux
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
29 * Available under NDA only. Errata info very hard to get.
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100
[] = {
58 static u8 svwks_revision
= 0;
59 static struct pci_dev
*isa_dev
;
61 static int check_in_drive_lists (ide_drive_t
*drive
, const char **list
)
64 if (!strcmp(*list
++, drive
->id
->model
))
69 static u8
svwks_udma_filter(ide_drive_t
*drive
)
71 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
75 pci_read_config_byte(dev
, PCI_REVISION_ID
, &svwks_revision
);
77 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
)
79 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
82 pci_read_config_dword(isa_dev
, 0x64, ®
);
85 * Don't enable UDMA on disk devices for the moment
87 if(drive
->media
== ide_disk
)
89 /* Check the OSB4 DMA33 enable bit */
90 return ((reg
& 0x00004000) == 0x00004000) ? 0x07 : 0;
91 } else if (svwks_revision
< SVWKS_CSB5_REVISION_NEW
) {
93 } else if (svwks_revision
>= SVWKS_CSB5_REVISION_NEW
) {
95 pci_read_config_byte(dev
, 0x5A, &btr
);
98 /* If someone decides to do UDMA133 on CSB5 the same
99 issue will bite so be inclusive */
100 if (mode
> 2 && check_in_drive_lists(drive
, svwks_bad_ata100
))
104 case 3: mask
= 0x3f; break;
105 case 2: mask
= 0x1f; break;
106 case 1: mask
= 0x07; break;
107 default: mask
= 0x00; break;
110 if (((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
111 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) &&
112 (!(PCI_FUNC(dev
->devfn
) & 1)))
118 static u8
svwks_csb_check (struct pci_dev
*dev
)
120 switch (dev
->device
) {
121 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
:
122 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
:
123 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
:
124 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
:
131 static int svwks_tune_chipset (ide_drive_t
*drive
, u8 xferspeed
)
133 static const u8 udma_modes
[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
134 static const u8 dma_modes
[] = { 0x77, 0x21, 0x20 };
135 static const u8 pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
136 static const u8 drive_pci
[] = { 0x41, 0x40, 0x43, 0x42 };
137 static const u8 drive_pci2
[] = { 0x45, 0x44, 0x47, 0x46 };
139 ide_hwif_t
*hwif
= HWIF(drive
);
140 struct pci_dev
*dev
= hwif
->pci_dev
;
141 u8 speed
= ide_rate_filter(drive
, xferspeed
);
142 u8 pio
= ide_get_best_pio_mode(drive
, 255, 4, NULL
);
143 u8 unit
= (drive
->select
.b
.unit
& 0x01);
144 u8 csb5
= svwks_csb_check(dev
);
145 u8 ultra_enable
= 0, ultra_timing
= 0;
146 u8 dma_timing
= 0, pio_timing
= 0;
149 /* If we are about to put a disk into UDMA mode we screwed up.
150 Our code assumes we never _ever_ do this on an OSB4 */
152 if(dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4
&&
153 drive
->media
== ide_disk
&& speed
>= XFER_UDMA_0
)
156 pci_read_config_byte(dev
, drive_pci
[drive
->dn
], &pio_timing
);
157 pci_read_config_byte(dev
, drive_pci2
[drive
->dn
], &dma_timing
);
158 pci_read_config_byte(dev
, (0x56|hwif
->channel
), &ultra_timing
);
159 pci_read_config_word(dev
, 0x4A, &csb5_pio
);
160 pci_read_config_byte(dev
, 0x54, &ultra_enable
);
162 /* If we are in RAID mode (eg AMI MegaIDE) then we can't it
163 turns out trust the firmware configuration */
165 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
166 goto oem_setup_failed
;
168 /* Per Specified Design by OEM, and ASIC Architect */
169 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
170 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) {
171 if (!drive
->init_speed
) {
172 u8 dma_stat
= inb(hwif
->dma_status
);
174 if (((ultra_enable
<< (7-drive
->dn
) & 0x80) == 0x80) &&
175 ((dma_stat
& (1<<(5+unit
))) == (1<<(5+unit
)))) {
176 drive
->current_speed
= drive
->init_speed
= XFER_UDMA_0
+ udma_modes
[(ultra_timing
>> (4*unit
)) & ~(0xF0)];
178 } else if ((dma_timing
) &&
179 ((dma_stat
&(1<<(5+unit
)))==(1<<(5+unit
)))) {
182 switch (dma_timing
& 0x77) {
184 dmaspeed
= XFER_MW_DMA_2
;
187 dmaspeed
= XFER_MW_DMA_1
;
190 dmaspeed
= XFER_MW_DMA_0
;
196 drive
->current_speed
= drive
->init_speed
= dmaspeed
;
203 switch (pio_timing
& 0x7f) {
205 piospeed
= XFER_PIO_4
;
208 piospeed
= XFER_PIO_3
;
211 piospeed
= XFER_PIO_2
;
214 piospeed
= XFER_PIO_1
;
217 piospeed
= XFER_PIO_0
;
220 goto oem_setup_failed
;
223 drive
->current_speed
= drive
->init_speed
= piospeed
;
233 ultra_timing
&= ~(0x0F << (4*unit
));
234 ultra_enable
&= ~(0x01 << drive
->dn
);
235 csb5_pio
&= ~(0x0F << (4*drive
->dn
));
243 pio_timing
|= pio_modes
[speed
- XFER_PIO_0
];
244 csb5_pio
|= ((speed
- XFER_PIO_0
) << (4*drive
->dn
));
251 * TODO: always setup PIO mode so this won't be needed
253 pio_timing
|= pio_modes
[pio
];
254 csb5_pio
|= (pio
<< (4*drive
->dn
));
255 dma_timing
|= dma_modes
[speed
- XFER_MW_DMA_0
];
265 * TODO: always setup PIO mode so this won't be needed
267 pio_timing
|= pio_modes
[pio
];
268 csb5_pio
|= (pio
<< (4*drive
->dn
));
269 dma_timing
|= dma_modes
[2];
270 ultra_timing
|= ((udma_modes
[speed
- XFER_UDMA_0
]) << (4*unit
));
271 ultra_enable
|= (0x01 << drive
->dn
);
276 pci_write_config_byte(dev
, drive_pci
[drive
->dn
], pio_timing
);
278 pci_write_config_word(dev
, 0x4A, csb5_pio
);
280 pci_write_config_byte(dev
, drive_pci2
[drive
->dn
], dma_timing
);
281 pci_write_config_byte(dev
, (0x56|hwif
->channel
), ultra_timing
);
282 pci_write_config_byte(dev
, 0x54, ultra_enable
);
284 return (ide_config_drive_speed(drive
, speed
));
287 static void svwks_tune_drive (ide_drive_t
*drive
, u8 pio
)
289 pio
= ide_get_best_pio_mode(drive
, pio
, 4, NULL
);
290 (void)svwks_tune_chipset(drive
, XFER_PIO_0
+ pio
);
293 static int svwks_config_drive_xfer_rate (ide_drive_t
*drive
)
295 drive
->init_speed
= 0;
297 if (ide_tune_dma(drive
))
300 if (ide_use_fast_pio(drive
))
301 svwks_tune_drive(drive
, 255);
306 static unsigned int __devinit
init_chipset_svwks (struct pci_dev
*dev
, const char *name
)
311 /* save revision id to determine DMA capability */
312 pci_read_config_byte(dev
, PCI_REVISION_ID
, &svwks_revision
);
314 /* force Master Latency Timer value to 64 PCICLKs */
315 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x40);
317 /* OSB4 : South Bridge and IDE */
318 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
319 isa_dev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
320 PCI_DEVICE_ID_SERVERWORKS_OSB4
, NULL
);
322 pci_read_config_dword(isa_dev
, 0x64, ®
);
323 reg
&= ~0x00002000; /* disable 600ns interrupt mask */
324 if(!(reg
& 0x00004000))
325 printk(KERN_DEBUG
"%s: UDMA not BIOS enabled.\n", name
);
326 reg
|= 0x00004000; /* enable UDMA/33 support */
327 pci_write_config_dword(isa_dev
, 0x64, reg
);
331 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
332 else if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
) ||
333 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
334 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) {
336 /* Third Channel Test */
337 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
338 struct pci_dev
* findev
= NULL
;
340 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
341 PCI_DEVICE_ID_SERVERWORKS_CSB5
, NULL
);
343 pci_read_config_dword(findev
, 0x4C, ®4c
);
344 reg4c
&= ~0x000007FF;
347 pci_write_config_dword(findev
, 0x4C, reg4c
);
350 outb_p(0x06, 0x0c00);
351 dev
->irq
= inb_p(0x0c01);
353 struct pci_dev
* findev
= NULL
;
356 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
357 PCI_DEVICE_ID_SERVERWORKS_CSB6
, NULL
);
359 pci_read_config_byte(findev
, 0x41, ®41
);
361 pci_write_config_byte(findev
, 0x41, reg41
);
365 * This is a device pin issue on CSB6.
366 * Since there will be a future raid mode,
367 * early versions of the chipset require the
368 * interrupt pin to be set, and it is a compatibility
371 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
374 // pci_read_config_dword(dev, 0x40, &pioreg)
375 // pci_write_config_dword(dev, 0x40, 0x99999999);
376 // pci_read_config_dword(dev, 0x44, &dmareg);
377 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
378 /* setup the UDMA Control register
380 * 1. clear bit 6 to enable DMA
381 * 2. enable DMA modes with bits 0-1
385 * 11 : udma2/udma4/udma5
387 pci_read_config_byte(dev
, 0x5A, &btr
);
389 if (!(PCI_FUNC(dev
->devfn
) & 1))
392 btr
|= (svwks_revision
>= SVWKS_CSB5_REVISION_NEW
) ? 0x3 : 0x2;
393 pci_write_config_byte(dev
, 0x5A, btr
);
395 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
396 else if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
) {
397 pci_read_config_byte(dev
, 0x5A, &btr
);
400 pci_write_config_byte(dev
, 0x5A, btr
);
406 static unsigned int __devinit
ata66_svwks_svwks (ide_hwif_t
*hwif
)
411 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
412 * of the subsystem device ID indicate presence of an 80-pin cable.
413 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
414 * Bit 15 set = secondary IDE channel has 80-pin cable.
415 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
416 * Bit 14 set = primary IDE channel has 80-pin cable.
418 static unsigned int __devinit
ata66_svwks_dell (ide_hwif_t
*hwif
)
420 struct pci_dev
*dev
= hwif
->pci_dev
;
421 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
422 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
423 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
||
424 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
))
425 return ((1 << (hwif
->channel
+ 14)) &
426 dev
->subsystem_device
) ? 1 : 0;
430 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
431 * detect issue by attaching the drives directly to the board.
432 * This check follows the Dell precedent (how scary is that?!)
434 * WARNING: this only works on Alpine hardware!
436 static unsigned int __devinit
ata66_svwks_cobalt (ide_hwif_t
*hwif
)
438 struct pci_dev
*dev
= hwif
->pci_dev
;
439 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
&&
440 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
441 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
)
442 return ((1 << (hwif
->channel
+ 14)) &
443 dev
->subsystem_device
) ? 1 : 0;
447 static unsigned int __devinit
ata66_svwks (ide_hwif_t
*hwif
)
449 struct pci_dev
*dev
= hwif
->pci_dev
;
452 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SERVERWORKS
)
453 return ata66_svwks_svwks (hwif
);
456 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
457 return ata66_svwks_dell (hwif
);
460 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
)
461 return ata66_svwks_cobalt (hwif
);
463 /* Per Specified Design by OEM, and ASIC Architect */
464 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
465 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
))
471 static void __devinit
init_hwif_svwks (ide_hwif_t
*hwif
)
476 hwif
->irq
= hwif
->channel
? 15 : 14;
478 hwif
->tuneproc
= &svwks_tune_drive
;
479 hwif
->speedproc
= &svwks_tune_chipset
;
480 hwif
->udma_filter
= &svwks_udma_filter
;
484 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
)
485 hwif
->ultra_mask
= 0x3f;
487 hwif
->mwdma_mask
= 0x07;
491 if (!hwif
->dma_base
) {
492 hwif
->drives
[0].autotune
= 1;
493 hwif
->drives
[1].autotune
= 1;
497 hwif
->ide_dma_check
= &svwks_config_drive_xfer_rate
;
498 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
499 if (!hwif
->udma_four
)
500 hwif
->udma_four
= ata66_svwks(hwif
);
505 dma_stat
= inb(hwif
->dma_status
);
506 hwif
->drives
[0].autodma
= (dma_stat
& 0x20);
507 hwif
->drives
[1].autodma
= (dma_stat
& 0x40);
508 hwif
->drives
[0].autotune
= (!(dma_stat
& 0x20));
509 hwif
->drives
[1].autotune
= (!(dma_stat
& 0x40));
512 static int __devinit
init_setup_svwks (struct pci_dev
*dev
, ide_pci_device_t
*d
)
514 return ide_setup_pci_device(dev
, d
);
517 static int __devinit
init_setup_csb6 (struct pci_dev
*dev
, ide_pci_device_t
*d
)
519 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
520 d
->bootable
= NEVER_BOARD
;
521 if (dev
->resource
[0].start
== 0x01f1)
522 d
->bootable
= ON_BOARD
;
525 d
->channels
= ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
||
526 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
) &&
527 (!(PCI_FUNC(dev
->devfn
) & 1))) ? 1 : 2;
529 return ide_setup_pci_device(dev
, d
);
532 static ide_pci_device_t serverworks_chipsets
[] __devinitdata
= {
534 .name
= "SvrWks OSB4",
535 .init_setup
= init_setup_svwks
,
536 .init_chipset
= init_chipset_svwks
,
537 .init_hwif
= init_hwif_svwks
,
540 .bootable
= ON_BOARD
,
542 .name
= "SvrWks CSB5",
543 .init_setup
= init_setup_svwks
,
544 .init_chipset
= init_chipset_svwks
,
545 .init_hwif
= init_hwif_svwks
,
548 .bootable
= ON_BOARD
,
550 .name
= "SvrWks CSB6",
551 .init_setup
= init_setup_csb6
,
552 .init_chipset
= init_chipset_svwks
,
553 .init_hwif
= init_hwif_svwks
,
556 .bootable
= ON_BOARD
,
558 .name
= "SvrWks CSB6",
559 .init_setup
= init_setup_csb6
,
560 .init_chipset
= init_chipset_svwks
,
561 .init_hwif
= init_hwif_svwks
,
562 .channels
= 1, /* 2 */
564 .bootable
= ON_BOARD
,
566 .name
= "SvrWks HT1000",
567 .init_setup
= init_setup_svwks
,
568 .init_chipset
= init_chipset_svwks
,
569 .init_hwif
= init_hwif_svwks
,
570 .channels
= 1, /* 2 */
572 .bootable
= ON_BOARD
,
577 * svwks_init_one - called when a OSB/CSB is found
578 * @dev: the svwks device
579 * @id: the matching pci id
581 * Called when the PCI registration layer (or the IDE initialization)
582 * finds a device matching our IDE device tables.
585 static int __devinit
svwks_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
587 ide_pci_device_t
*d
= &serverworks_chipsets
[id
->driver_data
];
589 return d
->init_setup(dev
, d
);
592 static struct pci_device_id svwks_pci_tbl
[] = {
593 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
594 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
595 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
596 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
597 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
600 MODULE_DEVICE_TABLE(pci
, svwks_pci_tbl
);
602 static struct pci_driver driver
= {
603 .name
= "Serverworks_IDE",
604 .id_table
= svwks_pci_tbl
,
605 .probe
= svwks_init_one
,
608 static int __init
svwks_ide_init(void)
610 return ide_pci_register_driver(&driver
);
613 module_init(svwks_ide_init
);
615 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
616 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
617 MODULE_LICENSE("GPL");