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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / sparc64 / kernel / traps.c
bloba05b37f025c4406a91677b5d7ae7894f1d9601b3
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/kallsyms.h>
16 #include <linux/signal.h>
17 #include <linux/smp.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/kdebug.h>
21
22 #include <asm/smp.h>
23 #include <asm/delay.h>
24 #include <asm/system.h>
25 #include <asm/ptrace.h>
26 #include <asm/oplib.h>
27 #include <asm/page.h>
28 #include <asm/pgtable.h>
29 #include <asm/unistd.h>
30 #include <asm/uaccess.h>
31 #include <asm/fpumacro.h>
32 #include <asm/lsu.h>
33 #include <asm/dcu.h>
34 #include <asm/estate.h>
35 #include <asm/chafsr.h>
36 #include <asm/sfafsr.h>
37 #include <asm/psrcompat.h>
38 #include <asm/processor.h>
39 #include <asm/timer.h>
40 #include <asm/head.h>
41 #ifdef CONFIG_KMOD
42 #include <linux/kmod.h>
43 #endif
44 #include <asm/prom.h>
45
46
47 /* When an irrecoverable trap occurs at tl > 0, the trap entry
48 * code logs the trap state registers at every level in the trap
49 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
50 * is as follows:
51 */
52 struct tl1_traplog {
53 struct {
54 unsigned long tstate;
55 unsigned long tpc;
56 unsigned long tnpc;
57 unsigned long tt;
58 } trapstack[4];
59 unsigned long tl;
60 };
61
62 static void dump_tl1_traplog(struct tl1_traplog *p)
63 {
64 int i, limit;
65
66 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
67 "dumping track stack.\n", p->tl);
68
69 limit = (tlb_type == hypervisor) ? 2 : 4;
70 for (i = 0; i < limit; i++) {
71 printk(KERN_EMERG
72 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
73 "TNPC[%016lx] TT[%lx]\n",
74 i + 1,
75 p->trapstack[i].tstate, p->trapstack[i].tpc,
76 p->trapstack[i].tnpc, p->trapstack[i].tt);
77 print_symbol("TRAPLOG: TPC<%s>\n", p->trapstack[i].tpc);
78 }
79 }
80
81 void do_call_debug(struct pt_regs *regs)
82 {
83 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
84 }
85
86 void bad_trap(struct pt_regs *regs, long lvl)
87 {
88 char buffer[32];
89 siginfo_t info;
90
91 if (notify_die(DIE_TRAP, "bad trap", regs,
92 0, lvl, SIGTRAP) == NOTIFY_STOP)
93 return;
94
95 if (lvl < 0x100) {
96 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
97 die_if_kernel(buffer, regs);
98 }
99
100 lvl -= 0x100;
101 if (regs->tstate & TSTATE_PRIV) {
102 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
103 die_if_kernel(buffer, regs);
104 }
105 if (test_thread_flag(TIF_32BIT)) {
106 regs->tpc &= 0xffffffff;
107 regs->tnpc &= 0xffffffff;
108 }
109 info.si_signo = SIGILL;
110 info.si_errno = 0;
111 info.si_code = ILL_ILLTRP;
112 info.si_addr = (void __user *)regs->tpc;
113 info.si_trapno = lvl;
114 force_sig_info(SIGILL, &info, current);
115 }
116
117 void bad_trap_tl1(struct pt_regs *regs, long lvl)
118 {
119 char buffer[32];
120
121 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
122 0, lvl, SIGTRAP) == NOTIFY_STOP)
123 return;
124
125 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
126
127 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
128 die_if_kernel (buffer, regs);
129 }
130
131 #ifdef CONFIG_DEBUG_BUGVERBOSE
132 void do_BUG(const char *file, int line)
133 {
134 bust_spinlocks(1);
135 printk("kernel BUG at %s:%d!\n", file, line);
136 }
137 #endif
138
139 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
140 {
141 siginfo_t info;
142
143 if (notify_die(DIE_TRAP, "instruction access exception", regs,
144 0, 0x8, SIGTRAP) == NOTIFY_STOP)
145 return;
146
147 if (regs->tstate & TSTATE_PRIV) {
148 printk("spitfire_insn_access_exception: SFSR[%016lx] "
149 "SFAR[%016lx], going.\n", sfsr, sfar);
150 die_if_kernel("Iax", regs);
151 }
152 if (test_thread_flag(TIF_32BIT)) {
153 regs->tpc &= 0xffffffff;
154 regs->tnpc &= 0xffffffff;
155 }
156 info.si_signo = SIGSEGV;
157 info.si_errno = 0;
158 info.si_code = SEGV_MAPERR;
159 info.si_addr = (void __user *)regs->tpc;
160 info.si_trapno = 0;
161 force_sig_info(SIGSEGV, &info, current);
162 }
163
164 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
165 {
166 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
167 0, 0x8, SIGTRAP) == NOTIFY_STOP)
168 return;
169
170 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
171 spitfire_insn_access_exception(regs, sfsr, sfar);
172 }
173
174 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
175 {
176 unsigned short type = (type_ctx >> 16);
177 unsigned short ctx = (type_ctx & 0xffff);
178 siginfo_t info;
179
180 if (notify_die(DIE_TRAP, "instruction access exception", regs,
181 0, 0x8, SIGTRAP) == NOTIFY_STOP)
182 return;
183
184 if (regs->tstate & TSTATE_PRIV) {
185 printk("sun4v_insn_access_exception: ADDR[%016lx] "
186 "CTX[%04x] TYPE[%04x], going.\n",
187 addr, ctx, type);
188 die_if_kernel("Iax", regs);
189 }
190
191 if (test_thread_flag(TIF_32BIT)) {
192 regs->tpc &= 0xffffffff;
193 regs->tnpc &= 0xffffffff;
194 }
195 info.si_signo = SIGSEGV;
196 info.si_errno = 0;
197 info.si_code = SEGV_MAPERR;
198 info.si_addr = (void __user *) addr;
199 info.si_trapno = 0;
200 force_sig_info(SIGSEGV, &info, current);
201 }
202
203 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
204 {
205 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
206 0, 0x8, SIGTRAP) == NOTIFY_STOP)
207 return;
208
209 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
210 sun4v_insn_access_exception(regs, addr, type_ctx);
211 }
212
213 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
214 {
215 siginfo_t info;
216
217 if (notify_die(DIE_TRAP, "data access exception", regs,
218 0, 0x30, SIGTRAP) == NOTIFY_STOP)
219 return;
220
221 if (regs->tstate & TSTATE_PRIV) {
222 /* Test if this comes from uaccess places. */
223 const struct exception_table_entry *entry;
224
225 entry = search_exception_tables(regs->tpc);
226 if (entry) {
227 /* Ouch, somebody is trying VM hole tricks on us... */
228 #ifdef DEBUG_EXCEPTIONS
229 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
230 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
231 regs->tpc, entry->fixup);
232 #endif
233 regs->tpc = entry->fixup;
234 regs->tnpc = regs->tpc + 4;
235 return;
236 }
237 /* Shit... */
238 printk("spitfire_data_access_exception: SFSR[%016lx] "
239 "SFAR[%016lx], going.\n", sfsr, sfar);
240 die_if_kernel("Dax", regs);
241 }
242
243 info.si_signo = SIGSEGV;
244 info.si_errno = 0;
245 info.si_code = SEGV_MAPERR;
246 info.si_addr = (void __user *)sfar;
247 info.si_trapno = 0;
248 force_sig_info(SIGSEGV, &info, current);
249 }
250
251 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
252 {
253 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
254 0, 0x30, SIGTRAP) == NOTIFY_STOP)
255 return;
256
257 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
258 spitfire_data_access_exception(regs, sfsr, sfar);
259 }
260
261 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
262 {
263 unsigned short type = (type_ctx >> 16);
264 unsigned short ctx = (type_ctx & 0xffff);
265 siginfo_t info;
266
267 if (notify_die(DIE_TRAP, "data access exception", regs,
268 0, 0x8, SIGTRAP) == NOTIFY_STOP)
269 return;
270
271 if (regs->tstate & TSTATE_PRIV) {
272 printk("sun4v_data_access_exception: ADDR[%016lx] "
273 "CTX[%04x] TYPE[%04x], going.\n",
274 addr, ctx, type);
275 die_if_kernel("Dax", regs);
276 }
277
278 if (test_thread_flag(TIF_32BIT)) {
279 regs->tpc &= 0xffffffff;
280 regs->tnpc &= 0xffffffff;
281 }
282 info.si_signo = SIGSEGV;
283 info.si_errno = 0;
284 info.si_code = SEGV_MAPERR;
285 info.si_addr = (void __user *) addr;
286 info.si_trapno = 0;
287 force_sig_info(SIGSEGV, &info, current);
288 }
289
290 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
291 {
292 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
293 0, 0x8, SIGTRAP) == NOTIFY_STOP)
294 return;
295
296 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
297 sun4v_data_access_exception(regs, addr, type_ctx);
298 }
299
300 #ifdef CONFIG_PCI
301 /* This is really pathetic... */
302 extern volatile int pci_poke_in_progress;
303 extern volatile int pci_poke_cpu;
304 extern volatile int pci_poke_faulted;
305 #endif
306
307 /* When access exceptions happen, we must do this. */
308 static void spitfire_clean_and_reenable_l1_caches(void)
309 {
310 unsigned long va;
311
312 if (tlb_type != spitfire)
313 BUG();
314
315 /* Clean 'em. */
316 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
317 spitfire_put_icache_tag(va, 0x0);
318 spitfire_put_dcache_tag(va, 0x0);
319 }
320
321 /* Re-enable in LSU. */
322 __asm__ __volatile__("flush %%g6\n\t"
323 "membar #Sync\n\t"
324 "stxa %0, [%%g0] %1\n\t"
325 "membar #Sync"
326 : /* no outputs */
327 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
328 LSU_CONTROL_IM | LSU_CONTROL_DM),
329 "i" (ASI_LSU_CONTROL)
330 : "memory");
331 }
332
333 static void spitfire_enable_estate_errors(void)
334 {
335 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
336 "membar #Sync"
337 : /* no outputs */
338 : "r" (ESTATE_ERR_ALL),
339 "i" (ASI_ESTATE_ERROR_EN));
340 }
341
342 static char ecc_syndrome_table[] = {
343 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
344 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
345 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
346 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
347 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
348 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
349 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
350 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
351 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
352 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
353 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
354 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
355 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
356 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
357 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
358 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
359 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
360 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
361 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
362 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
363 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
364 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
365 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
366 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
367 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
368 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
369 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
370 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
371 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
372 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
373 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
374 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
375 };
376
377 static char *syndrome_unknown = "<Unknown>";
378
379 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
380 {
381 unsigned short scode;
382 char memmod_str[64], *p;
383
384 if (udbl & bit) {
385 scode = ecc_syndrome_table[udbl & 0xff];
386 if (prom_getunumber(scode, afar,
387 memmod_str, sizeof(memmod_str)) == -1)
388 p = syndrome_unknown;
389 else
390 p = memmod_str;
391 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
392 "Memory Module \"%s\"\n",
393 smp_processor_id(), scode, p);
394 }
395
396 if (udbh & bit) {
397 scode = ecc_syndrome_table[udbh & 0xff];
398 if (prom_getunumber(scode, afar,
399 memmod_str, sizeof(memmod_str)) == -1)
400 p = syndrome_unknown;
401 else
402 p = memmod_str;
403 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
404 "Memory Module \"%s\"\n",
405 smp_processor_id(), scode, p);
406 }
407
408 }
409
410 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
411 {
412
413 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
414 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
415 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
416
417 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
418
419 /* We always log it, even if someone is listening for this
420 * trap.
421 */
422 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
423 0, TRAP_TYPE_CEE, SIGTRAP);
424
425 /* The Correctable ECC Error trap does not disable I/D caches. So
426 * we only have to restore the ESTATE Error Enable register.
427 */
428 spitfire_enable_estate_errors();
429 }
430
431 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
432 {
433 siginfo_t info;
434
435 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
436 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
437 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
438
439 /* XXX add more human friendly logging of the error status
440 * XXX as is implemented for cheetah
441 */
442
443 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
444
445 /* We always log it, even if someone is listening for this
446 * trap.
447 */
448 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
449 0, tt, SIGTRAP);
450
451 if (regs->tstate & TSTATE_PRIV) {
452 if (tl1)
453 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
454 die_if_kernel("UE", regs);
455 }
456
457 /* XXX need more intelligent processing here, such as is implemented
458 * XXX for cheetah errors, in fact if the E-cache still holds the
459 * XXX line with bad parity this will loop
460 */
461
462 spitfire_clean_and_reenable_l1_caches();
463 spitfire_enable_estate_errors();
464
465 if (test_thread_flag(TIF_32BIT)) {
466 regs->tpc &= 0xffffffff;
467 regs->tnpc &= 0xffffffff;
468 }
469 info.si_signo = SIGBUS;
470 info.si_errno = 0;
471 info.si_code = BUS_OBJERR;
472 info.si_addr = (void *)0;
473 info.si_trapno = 0;
474 force_sig_info(SIGBUS, &info, current);
475 }
476
477 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
478 {
479 unsigned long afsr, tt, udbh, udbl;
480 int tl1;
481
482 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
483 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
484 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
485 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
486 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
487
488 #ifdef CONFIG_PCI
489 if (tt == TRAP_TYPE_DAE &&
490 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
491 spitfire_clean_and_reenable_l1_caches();
492 spitfire_enable_estate_errors();
493
494 pci_poke_faulted = 1;
495 regs->tnpc = regs->tpc + 4;
496 return;
497 }
498 #endif
499
500 if (afsr & SFAFSR_UE)
501 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
502
503 if (tt == TRAP_TYPE_CEE) {
504 /* Handle the case where we took a CEE trap, but ACK'd
505 * only the UE state in the UDB error registers.
506 */
507 if (afsr & SFAFSR_UE) {
508 if (udbh & UDBE_CE) {
509 __asm__ __volatile__(
510 "stxa %0, [%1] %2\n\t"
511 "membar #Sync"
512 : /* no outputs */
513 : "r" (udbh & UDBE_CE),
514 "r" (0x0), "i" (ASI_UDB_ERROR_W));
515 }
516 if (udbl & UDBE_CE) {
517 __asm__ __volatile__(
518 "stxa %0, [%1] %2\n\t"
519 "membar #Sync"
520 : /* no outputs */
521 : "r" (udbl & UDBE_CE),
522 "r" (0x18), "i" (ASI_UDB_ERROR_W));
523 }
524 }
525
526 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
527 }
528 }
529
530 int cheetah_pcache_forced_on;
531
532 void cheetah_enable_pcache(void)
533 {
534 unsigned long dcr;
535
536 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
537 smp_processor_id());
538
539 __asm__ __volatile__("ldxa [%%g0] %1, %0"
540 : "=r" (dcr)
541 : "i" (ASI_DCU_CONTROL_REG));
542 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
543 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
544 "membar #Sync"
545 : /* no outputs */
546 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
547 }
548
549 /* Cheetah error trap handling. */
550 static unsigned long ecache_flush_physbase;
551 static unsigned long ecache_flush_linesize;
552 static unsigned long ecache_flush_size;
553
554 /* WARNING: The error trap handlers in assembly know the precise
555 * layout of the following structure.
556 *
557 * C-level handlers below use this information to log the error
558 * and then determine how to recover (if possible).
559 */
560 struct cheetah_err_info {
561 /*0x00*/u64 afsr;
562 /*0x08*/u64 afar;
563
564 /* D-cache state */
565 /*0x10*/u64 dcache_data[4]; /* The actual data */
566 /*0x30*/u64 dcache_index; /* D-cache index */
567 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
568 /*0x40*/u64 dcache_utag; /* D-cache microtag */
569 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
570
571 /* I-cache state */
572 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
573 /*0x90*/u64 icache_index; /* I-cache index */
574 /*0x98*/u64 icache_tag; /* I-cache phys tag */
575 /*0xa0*/u64 icache_utag; /* I-cache microtag */
576 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
577 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
578 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
579
580 /* E-cache state */
581 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
582 /*0xe0*/u64 ecache_index; /* E-cache index */
583 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
584
585 /*0xf0*/u64 __pad[32 - 30];
586 };
587 #define CHAFSR_INVALID ((u64)-1L)
588
589 /* This table is ordered in priority of errors and matches the
590 * AFAR overwrite policy as well.
591 */
592
593 struct afsr_error_table {
594 unsigned long mask;
595 const char *name;
596 };
597
598 static const char CHAFSR_PERR_msg[] =
599 "System interface protocol error";
600 static const char CHAFSR_IERR_msg[] =
601 "Internal processor error";
602 static const char CHAFSR_ISAP_msg[] =
603 "System request parity error on incoming addresss";
604 static const char CHAFSR_UCU_msg[] =
605 "Uncorrectable E-cache ECC error for ifetch/data";
606 static const char CHAFSR_UCC_msg[] =
607 "SW Correctable E-cache ECC error for ifetch/data";
608 static const char CHAFSR_UE_msg[] =
609 "Uncorrectable system bus data ECC error for read";
610 static const char CHAFSR_EDU_msg[] =
611 "Uncorrectable E-cache ECC error for stmerge/blkld";
612 static const char CHAFSR_EMU_msg[] =
613 "Uncorrectable system bus MTAG error";
614 static const char CHAFSR_WDU_msg[] =
615 "Uncorrectable E-cache ECC error for writeback";
616 static const char CHAFSR_CPU_msg[] =
617 "Uncorrectable ECC error for copyout";
618 static const char CHAFSR_CE_msg[] =
619 "HW corrected system bus data ECC error for read";
620 static const char CHAFSR_EDC_msg[] =
621 "HW corrected E-cache ECC error for stmerge/blkld";
622 static const char CHAFSR_EMC_msg[] =
623 "HW corrected system bus MTAG ECC error";
624 static const char CHAFSR_WDC_msg[] =
625 "HW corrected E-cache ECC error for writeback";
626 static const char CHAFSR_CPC_msg[] =
627 "HW corrected ECC error for copyout";
628 static const char CHAFSR_TO_msg[] =
629 "Unmapped error from system bus";
630 static const char CHAFSR_BERR_msg[] =
631 "Bus error response from system bus";
632 static const char CHAFSR_IVC_msg[] =
633 "HW corrected system bus data ECC error for ivec read";
634 static const char CHAFSR_IVU_msg[] =
635 "Uncorrectable system bus data ECC error for ivec read";
636 static struct afsr_error_table __cheetah_error_table[] = {
637 { CHAFSR_PERR, CHAFSR_PERR_msg },
638 { CHAFSR_IERR, CHAFSR_IERR_msg },
639 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
640 { CHAFSR_UCU, CHAFSR_UCU_msg },
641 { CHAFSR_UCC, CHAFSR_UCC_msg },
642 { CHAFSR_UE, CHAFSR_UE_msg },
643 { CHAFSR_EDU, CHAFSR_EDU_msg },
644 { CHAFSR_EMU, CHAFSR_EMU_msg },
645 { CHAFSR_WDU, CHAFSR_WDU_msg },
646 { CHAFSR_CPU, CHAFSR_CPU_msg },
647 { CHAFSR_CE, CHAFSR_CE_msg },
648 { CHAFSR_EDC, CHAFSR_EDC_msg },
649 { CHAFSR_EMC, CHAFSR_EMC_msg },
650 { CHAFSR_WDC, CHAFSR_WDC_msg },
651 { CHAFSR_CPC, CHAFSR_CPC_msg },
652 { CHAFSR_TO, CHAFSR_TO_msg },
653 { CHAFSR_BERR, CHAFSR_BERR_msg },
654 /* These two do not update the AFAR. */
655 { CHAFSR_IVC, CHAFSR_IVC_msg },
656 { CHAFSR_IVU, CHAFSR_IVU_msg },
657 { 0, NULL },
658 };
659 static const char CHPAFSR_DTO_msg[] =
660 "System bus unmapped error for prefetch/storequeue-read";
661 static const char CHPAFSR_DBERR_msg[] =
662 "System bus error for prefetch/storequeue-read";
663 static const char CHPAFSR_THCE_msg[] =
664 "Hardware corrected E-cache Tag ECC error";
665 static const char CHPAFSR_TSCE_msg[] =
666 "SW handled correctable E-cache Tag ECC error";
667 static const char CHPAFSR_TUE_msg[] =
668 "Uncorrectable E-cache Tag ECC error";
669 static const char CHPAFSR_DUE_msg[] =
670 "System bus uncorrectable data ECC error due to prefetch/store-fill";
671 static struct afsr_error_table __cheetah_plus_error_table[] = {
672 { CHAFSR_PERR, CHAFSR_PERR_msg },
673 { CHAFSR_IERR, CHAFSR_IERR_msg },
674 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
675 { CHAFSR_UCU, CHAFSR_UCU_msg },
676 { CHAFSR_UCC, CHAFSR_UCC_msg },
677 { CHAFSR_UE, CHAFSR_UE_msg },
678 { CHAFSR_EDU, CHAFSR_EDU_msg },
679 { CHAFSR_EMU, CHAFSR_EMU_msg },
680 { CHAFSR_WDU, CHAFSR_WDU_msg },
681 { CHAFSR_CPU, CHAFSR_CPU_msg },
682 { CHAFSR_CE, CHAFSR_CE_msg },
683 { CHAFSR_EDC, CHAFSR_EDC_msg },
684 { CHAFSR_EMC, CHAFSR_EMC_msg },
685 { CHAFSR_WDC, CHAFSR_WDC_msg },
686 { CHAFSR_CPC, CHAFSR_CPC_msg },
687 { CHAFSR_TO, CHAFSR_TO_msg },
688 { CHAFSR_BERR, CHAFSR_BERR_msg },
689 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
690 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
691 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
692 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
693 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
694 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
695 /* These two do not update the AFAR. */
696 { CHAFSR_IVC, CHAFSR_IVC_msg },
697 { CHAFSR_IVU, CHAFSR_IVU_msg },
698 { 0, NULL },
699 };
700 static const char JPAFSR_JETO_msg[] =
701 "System interface protocol error, hw timeout caused";
702 static const char JPAFSR_SCE_msg[] =
703 "Parity error on system snoop results";
704 static const char JPAFSR_JEIC_msg[] =
705 "System interface protocol error, illegal command detected";
706 static const char JPAFSR_JEIT_msg[] =
707 "System interface protocol error, illegal ADTYPE detected";
708 static const char JPAFSR_OM_msg[] =
709 "Out of range memory error has occurred";
710 static const char JPAFSR_ETP_msg[] =
711 "Parity error on L2 cache tag SRAM";
712 static const char JPAFSR_UMS_msg[] =
713 "Error due to unsupported store";
714 static const char JPAFSR_RUE_msg[] =
715 "Uncorrectable ECC error from remote cache/memory";
716 static const char JPAFSR_RCE_msg[] =
717 "Correctable ECC error from remote cache/memory";
718 static const char JPAFSR_BP_msg[] =
719 "JBUS parity error on returned read data";
720 static const char JPAFSR_WBP_msg[] =
721 "JBUS parity error on data for writeback or block store";
722 static const char JPAFSR_FRC_msg[] =
723 "Foreign read to DRAM incurring correctable ECC error";
724 static const char JPAFSR_FRU_msg[] =
725 "Foreign read to DRAM incurring uncorrectable ECC error";
726 static struct afsr_error_table __jalapeno_error_table[] = {
727 { JPAFSR_JETO, JPAFSR_JETO_msg },
728 { JPAFSR_SCE, JPAFSR_SCE_msg },
729 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
730 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
731 { CHAFSR_PERR, CHAFSR_PERR_msg },
732 { CHAFSR_IERR, CHAFSR_IERR_msg },
733 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
734 { CHAFSR_UCU, CHAFSR_UCU_msg },
735 { CHAFSR_UCC, CHAFSR_UCC_msg },
736 { CHAFSR_UE, CHAFSR_UE_msg },
737 { CHAFSR_EDU, CHAFSR_EDU_msg },
738 { JPAFSR_OM, JPAFSR_OM_msg },
739 { CHAFSR_WDU, CHAFSR_WDU_msg },
740 { CHAFSR_CPU, CHAFSR_CPU_msg },
741 { CHAFSR_CE, CHAFSR_CE_msg },
742 { CHAFSR_EDC, CHAFSR_EDC_msg },
743 { JPAFSR_ETP, JPAFSR_ETP_msg },
744 { CHAFSR_WDC, CHAFSR_WDC_msg },
745 { CHAFSR_CPC, CHAFSR_CPC_msg },
746 { CHAFSR_TO, CHAFSR_TO_msg },
747 { CHAFSR_BERR, CHAFSR_BERR_msg },
748 { JPAFSR_UMS, JPAFSR_UMS_msg },
749 { JPAFSR_RUE, JPAFSR_RUE_msg },
750 { JPAFSR_RCE, JPAFSR_RCE_msg },
751 { JPAFSR_BP, JPAFSR_BP_msg },
752 { JPAFSR_WBP, JPAFSR_WBP_msg },
753 { JPAFSR_FRC, JPAFSR_FRC_msg },
754 { JPAFSR_FRU, JPAFSR_FRU_msg },
755 /* These two do not update the AFAR. */
756 { CHAFSR_IVU, CHAFSR_IVU_msg },
757 { 0, NULL },
758 };
759 static struct afsr_error_table *cheetah_error_table;
760 static unsigned long cheetah_afsr_errors;
761
762 /* This is allocated at boot time based upon the largest hardware
763 * cpu ID in the system. We allocate two entries per cpu, one for
764 * TL==0 logging and one for TL >= 1 logging.
765 */
766 struct cheetah_err_info *cheetah_error_log;
767
768 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
769 {
770 struct cheetah_err_info *p;
771 int cpu = smp_processor_id();
772
773 if (!cheetah_error_log)
774 return NULL;
775
776 p = cheetah_error_log + (cpu * 2);
777 if ((afsr & CHAFSR_TL1) != 0UL)
778 p++;
779
780 return p;
781 }
782
783 extern unsigned int tl0_icpe[], tl1_icpe[];
784 extern unsigned int tl0_dcpe[], tl1_dcpe[];
785 extern unsigned int tl0_fecc[], tl1_fecc[];
786 extern unsigned int tl0_cee[], tl1_cee[];
787 extern unsigned int tl0_iae[], tl1_iae[];
788 extern unsigned int tl0_dae[], tl1_dae[];
789 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
790 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
791 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
792 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
793 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
794
795 void __init cheetah_ecache_flush_init(void)
796 {
797 unsigned long largest_size, smallest_linesize, order, ver;
798 int i, sz;
799
800 /* Scan all cpu device tree nodes, note two values:
801 * 1) largest E-cache size
802 * 2) smallest E-cache line size
803 */
804 largest_size = 0UL;
805 smallest_linesize = ~0UL;
806
807 for (i = 0; i < NR_CPUS; i++) {
808 unsigned long val;
809
810 val = cpu_data(i).ecache_size;
811 if (!val)
812 continue;
813
814 if (val > largest_size)
815 largest_size = val;
816
817 val = cpu_data(i).ecache_line_size;
818 if (val < smallest_linesize)
819 smallest_linesize = val;
820
821 }
822
823 if (largest_size == 0UL || smallest_linesize == ~0UL) {
824 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
825 "parameters.\n");
826 prom_halt();
827 }
828
829 ecache_flush_size = (2 * largest_size);
830 ecache_flush_linesize = smallest_linesize;
831
832 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
833
834 if (ecache_flush_physbase == ~0UL) {
835 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
836 "contiguous physical memory.\n",
837 ecache_flush_size);
838 prom_halt();
839 }
840
841 /* Now allocate error trap reporting scoreboard. */
842 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
843 for (order = 0; order < MAX_ORDER; order++) {
844 if ((PAGE_SIZE << order) >= sz)
845 break;
846 }
847 cheetah_error_log = (struct cheetah_err_info *)
848 __get_free_pages(GFP_KERNEL, order);
849 if (!cheetah_error_log) {
850 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
851 "error logging scoreboard (%d bytes).\n", sz);
852 prom_halt();
853 }
854 memset(cheetah_error_log, 0, PAGE_SIZE << order);
855
856 /* Mark all AFSRs as invalid so that the trap handler will
857 * log new new information there.
858 */
859 for (i = 0; i < 2 * NR_CPUS; i++)
860 cheetah_error_log[i].afsr = CHAFSR_INVALID;
861
862 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
863 if ((ver >> 32) == __JALAPENO_ID ||
864 (ver >> 32) == __SERRANO_ID) {
865 cheetah_error_table = &__jalapeno_error_table[0];
866 cheetah_afsr_errors = JPAFSR_ERRORS;
867 } else if ((ver >> 32) == 0x003e0015) {
868 cheetah_error_table = &__cheetah_plus_error_table[0];
869 cheetah_afsr_errors = CHPAFSR_ERRORS;
870 } else {
871 cheetah_error_table = &__cheetah_error_table[0];
872 cheetah_afsr_errors = CHAFSR_ERRORS;
873 }
874
875 /* Now patch trap tables. */
876 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
877 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
878 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
879 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
880 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
881 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
882 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
883 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
884 if (tlb_type == cheetah_plus) {
885 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
886 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
887 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
888 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
889 }
890 flushi(PAGE_OFFSET);
891 }
892
893 static void cheetah_flush_ecache(void)
894 {
895 unsigned long flush_base = ecache_flush_physbase;
896 unsigned long flush_linesize = ecache_flush_linesize;
897 unsigned long flush_size = ecache_flush_size;
898
899 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
900 " bne,pt %%xcc, 1b\n\t"
901 " ldxa [%2 + %0] %3, %%g0\n\t"
902 : "=&r" (flush_size)
903 : "0" (flush_size), "r" (flush_base),
904 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
905 }
906
907 static void cheetah_flush_ecache_line(unsigned long physaddr)
908 {
909 unsigned long alias;
910
911 physaddr &= ~(8UL - 1UL);
912 physaddr = (ecache_flush_physbase +
913 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
914 alias = physaddr + (ecache_flush_size >> 1UL);
915 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
916 "ldxa [%1] %2, %%g0\n\t"
917 "membar #Sync"
918 : /* no outputs */
919 : "r" (physaddr), "r" (alias),
920 "i" (ASI_PHYS_USE_EC));
921 }
922
923 /* Unfortunately, the diagnostic access to the I-cache tags we need to
924 * use to clear the thing interferes with I-cache coherency transactions.
925 *
926 * So we must only flush the I-cache when it is disabled.
927 */
928 static void __cheetah_flush_icache(void)
929 {
930 unsigned int icache_size, icache_line_size;
931 unsigned long addr;
932
933 icache_size = local_cpu_data().icache_size;
934 icache_line_size = local_cpu_data().icache_line_size;
935
936 /* Clear the valid bits in all the tags. */
937 for (addr = 0; addr < icache_size; addr += icache_line_size) {
938 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
939 "membar #Sync"
940 : /* no outputs */
941 : "r" (addr | (2 << 3)),
942 "i" (ASI_IC_TAG));
943 }
944 }
945
946 static void cheetah_flush_icache(void)
947 {
948 unsigned long dcu_save;
949
950 /* Save current DCU, disable I-cache. */
951 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
952 "or %0, %2, %%g1\n\t"
953 "stxa %%g1, [%%g0] %1\n\t"
954 "membar #Sync"
955 : "=r" (dcu_save)
956 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
957 : "g1");
958
959 __cheetah_flush_icache();
960
961 /* Restore DCU register */
962 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
963 "membar #Sync"
964 : /* no outputs */
965 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
966 }
967
968 static void cheetah_flush_dcache(void)
969 {
970 unsigned int dcache_size, dcache_line_size;
971 unsigned long addr;
972
973 dcache_size = local_cpu_data().dcache_size;
974 dcache_line_size = local_cpu_data().dcache_line_size;
975
976 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
977 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
978 "membar #Sync"
979 : /* no outputs */
980 : "r" (addr), "i" (ASI_DCACHE_TAG));
981 }
982 }
983
984 /* In order to make the even parity correct we must do two things.
985 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
986 * Next, we clear out all 32-bytes of data for that line. Data of
987 * all-zero + tag parity value of zero == correct parity.
988 */
989 static void cheetah_plus_zap_dcache_parity(void)
990 {
991 unsigned int dcache_size, dcache_line_size;
992 unsigned long addr;
993
994 dcache_size = local_cpu_data().dcache_size;
995 dcache_line_size = local_cpu_data().dcache_line_size;
996
997 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
998 unsigned long tag = (addr >> 14);
999 unsigned long line;
1000
1001 __asm__ __volatile__("membar #Sync\n\t"
1002 "stxa %0, [%1] %2\n\t"
1003 "membar #Sync"
1004 : /* no outputs */
1005 : "r" (tag), "r" (addr),
1006 "i" (ASI_DCACHE_UTAG));
1007 for (line = addr; line < addr + dcache_line_size; line += 8)
1008 __asm__ __volatile__("membar #Sync\n\t"
1009 "stxa %%g0, [%0] %1\n\t"
1010 "membar #Sync"
1011 : /* no outputs */
1012 : "r" (line),
1013 "i" (ASI_DCACHE_DATA));
1014 }
1015 }
1016
1017 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1018 * something palatable to the memory controller driver get_unumber
1019 * routine.
1020 */
1021 #define MT0 137
1022 #define MT1 138
1023 #define MT2 139
1024 #define NONE 254
1025 #define MTC0 140
1026 #define MTC1 141
1027 #define MTC2 142
1028 #define MTC3 143
1029 #define C0 128
1030 #define C1 129
1031 #define C2 130
1032 #define C3 131
1033 #define C4 132
1034 #define C5 133
1035 #define C6 134
1036 #define C7 135
1037 #define C8 136
1038 #define M2 144
1039 #define M3 145
1040 #define M4 146
1041 #define M 147
1042 static unsigned char cheetah_ecc_syntab[] = {
1043 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1044 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1045 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1046 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1047 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1048 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1049 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1050 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1051 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1052 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1053 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1054 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1055 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1056 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1057 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1058 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1059 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1060 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1061 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1062 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1063 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1064 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1065 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1066 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1067 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1068 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1069 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1070 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1071 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1072 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1073 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1074 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1075 };
1076 static unsigned char cheetah_mtag_syntab[] = {
1077 NONE, MTC0,
1078 MTC1, NONE,
1079 MTC2, NONE,
1080 NONE, MT0,
1081 MTC3, NONE,
1082 NONE, MT1,
1083 NONE, MT2,
1084 NONE, NONE
1085 };
1086
1087 /* Return the highest priority error conditon mentioned. */
1088 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
1089 {
1090 unsigned long tmp = 0;
1091 int i;
1092
1093 for (i = 0; cheetah_error_table[i].mask; i++) {
1094 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1095 return tmp;
1096 }
1097 return tmp;
1098 }
1099
1100 static const char *cheetah_get_string(unsigned long bit)
1101 {
1102 int i;
1103
1104 for (i = 0; cheetah_error_table[i].mask; i++) {
1105 if ((bit & cheetah_error_table[i].mask) != 0UL)
1106 return cheetah_error_table[i].name;
1107 }
1108 return "???";
1109 }
1110
1111 extern int chmc_getunumber(int, unsigned long, char *, int);
1112
1113 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1114 unsigned long afsr, unsigned long afar, int recoverable)
1115 {
1116 unsigned long hipri;
1117 char unum[256];
1118
1119 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1120 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1121 afsr, afar,
1122 (afsr & CHAFSR_TL1) ? 1 : 0);
1123 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1124 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1125 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1126 printk("%s" "ERROR(%d): ",
1127 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1128 print_symbol("TPC<%s>\n", regs->tpc);
1129 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1130 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1131 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1132 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1133 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1134 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1135 hipri = cheetah_get_hipri(afsr);
1136 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1137 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1138 hipri, cheetah_get_string(hipri));
1139
1140 /* Try to get unumber if relevant. */
1141 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1142 CHAFSR_CPC | CHAFSR_CPU | \
1143 CHAFSR_UE | CHAFSR_CE | \
1144 CHAFSR_EDC | CHAFSR_EDU | \
1145 CHAFSR_UCC | CHAFSR_UCU | \
1146 CHAFSR_WDU | CHAFSR_WDC)
1147 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1148 if (afsr & ESYND_ERRORS) {
1149 int syndrome;
1150 int ret;
1151
1152 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1153 syndrome = cheetah_ecc_syntab[syndrome];
1154 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1155 if (ret != -1)
1156 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1157 (recoverable ? KERN_WARNING : KERN_CRIT),
1158 smp_processor_id(), unum);
1159 } else if (afsr & MSYND_ERRORS) {
1160 int syndrome;
1161 int ret;
1162
1163 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1164 syndrome = cheetah_mtag_syntab[syndrome];
1165 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1166 if (ret != -1)
1167 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1168 (recoverable ? KERN_WARNING : KERN_CRIT),
1169 smp_processor_id(), unum);
1170 }
1171
1172 /* Now dump the cache snapshots. */
1173 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1174 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1175 (int) info->dcache_index,
1176 info->dcache_tag,
1177 info->dcache_utag,
1178 info->dcache_stag);
1179 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1180 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1181 info->dcache_data[0],
1182 info->dcache_data[1],
1183 info->dcache_data[2],
1184 info->dcache_data[3]);
1185 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1186 "u[%016lx] l[%016lx]\n",
1187 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1188 (int) info->icache_index,
1189 info->icache_tag,
1190 info->icache_utag,
1191 info->icache_stag,
1192 info->icache_upper,
1193 info->icache_lower);
1194 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1195 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1196 info->icache_data[0],
1197 info->icache_data[1],
1198 info->icache_data[2],
1199 info->icache_data[3]);
1200 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1201 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1202 info->icache_data[4],
1203 info->icache_data[5],
1204 info->icache_data[6],
1205 info->icache_data[7]);
1206 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1207 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1208 (int) info->ecache_index, info->ecache_tag);
1209 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1210 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1211 info->ecache_data[0],
1212 info->ecache_data[1],
1213 info->ecache_data[2],
1214 info->ecache_data[3]);
1215
1216 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1217 while (afsr != 0UL) {
1218 unsigned long bit = cheetah_get_hipri(afsr);
1219
1220 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1221 (recoverable ? KERN_WARNING : KERN_CRIT),
1222 bit, cheetah_get_string(bit));
1223
1224 afsr &= ~bit;
1225 }
1226
1227 if (!recoverable)
1228 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1229 }
1230
1231 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1232 {
1233 unsigned long afsr, afar;
1234 int ret = 0;
1235
1236 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1237 : "=r" (afsr)
1238 : "i" (ASI_AFSR));
1239 if ((afsr & cheetah_afsr_errors) != 0) {
1240 if (logp != NULL) {
1241 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1242 : "=r" (afar)
1243 : "i" (ASI_AFAR));
1244 logp->afsr = afsr;
1245 logp->afar = afar;
1246 }
1247 ret = 1;
1248 }
1249 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1250 "membar #Sync\n\t"
1251 : : "r" (afsr), "i" (ASI_AFSR));
1252
1253 return ret;
1254 }
1255
1256 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1257 {
1258 struct cheetah_err_info local_snapshot, *p;
1259 int recoverable;
1260
1261 /* Flush E-cache */
1262 cheetah_flush_ecache();
1263
1264 p = cheetah_get_error_log(afsr);
1265 if (!p) {
1266 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1267 afsr, afar);
1268 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1269 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1270 prom_halt();
1271 }
1272
1273 /* Grab snapshot of logged error. */
1274 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1275
1276 /* If the current trap snapshot does not match what the
1277 * trap handler passed along into our args, big trouble.
1278 * In such a case, mark the local copy as invalid.
1279 *
1280 * Else, it matches and we mark the afsr in the non-local
1281 * copy as invalid so we may log new error traps there.
1282 */
1283 if (p->afsr != afsr || p->afar != afar)
1284 local_snapshot.afsr = CHAFSR_INVALID;
1285 else
1286 p->afsr = CHAFSR_INVALID;
1287
1288 cheetah_flush_icache();
1289 cheetah_flush_dcache();
1290
1291 /* Re-enable I-cache/D-cache */
1292 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1293 "or %%g1, %1, %%g1\n\t"
1294 "stxa %%g1, [%%g0] %0\n\t"
1295 "membar #Sync"
1296 : /* no outputs */
1297 : "i" (ASI_DCU_CONTROL_REG),
1298 "i" (DCU_DC | DCU_IC)
1299 : "g1");
1300
1301 /* Re-enable error reporting */
1302 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1303 "or %%g1, %1, %%g1\n\t"
1304 "stxa %%g1, [%%g0] %0\n\t"
1305 "membar #Sync"
1306 : /* no outputs */
1307 : "i" (ASI_ESTATE_ERROR_EN),
1308 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1309 : "g1");
1310
1311 /* Decide if we can continue after handling this trap and
1312 * logging the error.
1313 */
1314 recoverable = 1;
1315 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1316 recoverable = 0;
1317
1318 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1319 * error was logged while we had error reporting traps disabled.
1320 */
1321 if (cheetah_recheck_errors(&local_snapshot)) {
1322 unsigned long new_afsr = local_snapshot.afsr;
1323
1324 /* If we got a new asynchronous error, die... */
1325 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1326 CHAFSR_WDU | CHAFSR_CPU |
1327 CHAFSR_IVU | CHAFSR_UE |
1328 CHAFSR_BERR | CHAFSR_TO))
1329 recoverable = 0;
1330 }
1331
1332 /* Log errors. */
1333 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1334
1335 if (!recoverable)
1336 panic("Irrecoverable Fast-ECC error trap.\n");
1337
1338 /* Flush E-cache to kick the error trap handlers out. */
1339 cheetah_flush_ecache();
1340 }
1341
1342 /* Try to fix a correctable error by pushing the line out from
1343 * the E-cache. Recheck error reporting registers to see if the
1344 * problem is intermittent.
1345 */
1346 static int cheetah_fix_ce(unsigned long physaddr)
1347 {
1348 unsigned long orig_estate;
1349 unsigned long alias1, alias2;
1350 int ret;
1351
1352 /* Make sure correctable error traps are disabled. */
1353 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1354 "andn %0, %1, %%g1\n\t"
1355 "stxa %%g1, [%%g0] %2\n\t"
1356 "membar #Sync"
1357 : "=&r" (orig_estate)
1358 : "i" (ESTATE_ERROR_CEEN),
1359 "i" (ASI_ESTATE_ERROR_EN)
1360 : "g1");
1361
1362 /* We calculate alias addresses that will force the
1363 * cache line in question out of the E-cache. Then
1364 * we bring it back in with an atomic instruction so
1365 * that we get it in some modified/exclusive state,
1366 * then we displace it again to try and get proper ECC
1367 * pushed back into the system.
1368 */
1369 physaddr &= ~(8UL - 1UL);
1370 alias1 = (ecache_flush_physbase +
1371 (physaddr & ((ecache_flush_size >> 1) - 1)));
1372 alias2 = alias1 + (ecache_flush_size >> 1);
1373 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1374 "ldxa [%1] %3, %%g0\n\t"
1375 "casxa [%2] %3, %%g0, %%g0\n\t"
1376 "membar #StoreLoad | #StoreStore\n\t"
1377 "ldxa [%0] %3, %%g0\n\t"
1378 "ldxa [%1] %3, %%g0\n\t"
1379 "membar #Sync"
1380 : /* no outputs */
1381 : "r" (alias1), "r" (alias2),
1382 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1383
1384 /* Did that trigger another error? */
1385 if (cheetah_recheck_errors(NULL)) {
1386 /* Try one more time. */
1387 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1388 "membar #Sync"
1389 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1390 if (cheetah_recheck_errors(NULL))
1391 ret = 2;
1392 else
1393 ret = 1;
1394 } else {
1395 /* No new error, intermittent problem. */
1396 ret = 0;
1397 }
1398
1399 /* Restore error enables. */
1400 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1401 "membar #Sync"
1402 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1403
1404 return ret;
1405 }
1406
1407 /* Return non-zero if PADDR is a valid physical memory address. */
1408 static int cheetah_check_main_memory(unsigned long paddr)
1409 {
1410 unsigned long vaddr = PAGE_OFFSET + paddr;
1411
1412 if (vaddr > (unsigned long) high_memory)
1413 return 0;
1414
1415 return kern_addr_valid(vaddr);
1416 }
1417
1418 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1419 {
1420 struct cheetah_err_info local_snapshot, *p;
1421 int recoverable, is_memory;
1422
1423 p = cheetah_get_error_log(afsr);
1424 if (!p) {
1425 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1426 afsr, afar);
1427 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1428 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1429 prom_halt();
1430 }
1431
1432 /* Grab snapshot of logged error. */
1433 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1434
1435 /* If the current trap snapshot does not match what the
1436 * trap handler passed along into our args, big trouble.
1437 * In such a case, mark the local copy as invalid.
1438 *
1439 * Else, it matches and we mark the afsr in the non-local
1440 * copy as invalid so we may log new error traps there.
1441 */
1442 if (p->afsr != afsr || p->afar != afar)
1443 local_snapshot.afsr = CHAFSR_INVALID;
1444 else
1445 p->afsr = CHAFSR_INVALID;
1446
1447 is_memory = cheetah_check_main_memory(afar);
1448
1449 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1450 /* XXX Might want to log the results of this operation
1451 * XXX somewhere... -DaveM
1452 */
1453 cheetah_fix_ce(afar);
1454 }
1455
1456 {
1457 int flush_all, flush_line;
1458
1459 flush_all = flush_line = 0;
1460 if ((afsr & CHAFSR_EDC) != 0UL) {
1461 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1462 flush_line = 1;
1463 else
1464 flush_all = 1;
1465 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1466 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1467 flush_line = 1;
1468 else
1469 flush_all = 1;
1470 }
1471
1472 /* Trap handler only disabled I-cache, flush it. */
1473 cheetah_flush_icache();
1474
1475 /* Re-enable I-cache */
1476 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1477 "or %%g1, %1, %%g1\n\t"
1478 "stxa %%g1, [%%g0] %0\n\t"
1479 "membar #Sync"
1480 : /* no outputs */
1481 : "i" (ASI_DCU_CONTROL_REG),
1482 "i" (DCU_IC)
1483 : "g1");
1484
1485 if (flush_all)
1486 cheetah_flush_ecache();
1487 else if (flush_line)
1488 cheetah_flush_ecache_line(afar);
1489 }
1490
1491 /* Re-enable error reporting */
1492 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1493 "or %%g1, %1, %%g1\n\t"
1494 "stxa %%g1, [%%g0] %0\n\t"
1495 "membar #Sync"
1496 : /* no outputs */
1497 : "i" (ASI_ESTATE_ERROR_EN),
1498 "i" (ESTATE_ERROR_CEEN)
1499 : "g1");
1500
1501 /* Decide if we can continue after handling this trap and
1502 * logging the error.
1503 */
1504 recoverable = 1;
1505 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1506 recoverable = 0;
1507
1508 /* Re-check AFSR/AFAR */
1509 (void) cheetah_recheck_errors(&local_snapshot);
1510
1511 /* Log errors. */
1512 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1513
1514 if (!recoverable)
1515 panic("Irrecoverable Correctable-ECC error trap.\n");
1516 }
1517
1518 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1519 {
1520 struct cheetah_err_info local_snapshot, *p;
1521 int recoverable, is_memory;
1522
1523 #ifdef CONFIG_PCI
1524 /* Check for the special PCI poke sequence. */
1525 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1526 cheetah_flush_icache();
1527 cheetah_flush_dcache();
1528
1529 /* Re-enable I-cache/D-cache */
1530 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1531 "or %%g1, %1, %%g1\n\t"
1532 "stxa %%g1, [%%g0] %0\n\t"
1533 "membar #Sync"
1534 : /* no outputs */
1535 : "i" (ASI_DCU_CONTROL_REG),
1536 "i" (DCU_DC | DCU_IC)
1537 : "g1");
1538
1539 /* Re-enable error reporting */
1540 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1541 "or %%g1, %1, %%g1\n\t"
1542 "stxa %%g1, [%%g0] %0\n\t"
1543 "membar #Sync"
1544 : /* no outputs */
1545 : "i" (ASI_ESTATE_ERROR_EN),
1546 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1547 : "g1");
1548
1549 (void) cheetah_recheck_errors(NULL);
1550
1551 pci_poke_faulted = 1;
1552 regs->tpc += 4;
1553 regs->tnpc = regs->tpc + 4;
1554 return;
1555 }
1556 #endif
1557
1558 p = cheetah_get_error_log(afsr);
1559 if (!p) {
1560 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1561 afsr, afar);
1562 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1563 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1564 prom_halt();
1565 }
1566
1567 /* Grab snapshot of logged error. */
1568 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1569
1570 /* If the current trap snapshot does not match what the
1571 * trap handler passed along into our args, big trouble.
1572 * In such a case, mark the local copy as invalid.
1573 *
1574 * Else, it matches and we mark the afsr in the non-local
1575 * copy as invalid so we may log new error traps there.
1576 */
1577 if (p->afsr != afsr || p->afar != afar)
1578 local_snapshot.afsr = CHAFSR_INVALID;
1579 else
1580 p->afsr = CHAFSR_INVALID;
1581
1582 is_memory = cheetah_check_main_memory(afar);
1583
1584 {
1585 int flush_all, flush_line;
1586
1587 flush_all = flush_line = 0;
1588 if ((afsr & CHAFSR_EDU) != 0UL) {
1589 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1590 flush_line = 1;
1591 else
1592 flush_all = 1;
1593 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1594 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1595 flush_line = 1;
1596 else
1597 flush_all = 1;
1598 }
1599
1600 cheetah_flush_icache();
1601 cheetah_flush_dcache();
1602
1603 /* Re-enable I/D caches */
1604 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1605 "or %%g1, %1, %%g1\n\t"
1606 "stxa %%g1, [%%g0] %0\n\t"
1607 "membar #Sync"
1608 : /* no outputs */
1609 : "i" (ASI_DCU_CONTROL_REG),
1610 "i" (DCU_IC | DCU_DC)
1611 : "g1");
1612
1613 if (flush_all)
1614 cheetah_flush_ecache();
1615 else if (flush_line)
1616 cheetah_flush_ecache_line(afar);
1617 }
1618
1619 /* Re-enable error reporting */
1620 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1621 "or %%g1, %1, %%g1\n\t"
1622 "stxa %%g1, [%%g0] %0\n\t"
1623 "membar #Sync"
1624 : /* no outputs */
1625 : "i" (ASI_ESTATE_ERROR_EN),
1626 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1627 : "g1");
1628
1629 /* Decide if we can continue after handling this trap and
1630 * logging the error.
1631 */
1632 recoverable = 1;
1633 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1634 recoverable = 0;
1635
1636 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1637 * error was logged while we had error reporting traps disabled.
1638 */
1639 if (cheetah_recheck_errors(&local_snapshot)) {
1640 unsigned long new_afsr = local_snapshot.afsr;
1641
1642 /* If we got a new asynchronous error, die... */
1643 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1644 CHAFSR_WDU | CHAFSR_CPU |
1645 CHAFSR_IVU | CHAFSR_UE |
1646 CHAFSR_BERR | CHAFSR_TO))
1647 recoverable = 0;
1648 }
1649
1650 /* Log errors. */
1651 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1652
1653 /* "Recoverable" here means we try to yank the page from ever
1654 * being newly used again. This depends upon a few things:
1655 * 1) Must be main memory, and AFAR must be valid.
1656 * 2) If we trapped from user, OK.
1657 * 3) Else, if we trapped from kernel we must find exception
1658 * table entry (ie. we have to have been accessing user
1659 * space).
1660 *
1661 * If AFAR is not in main memory, or we trapped from kernel
1662 * and cannot find an exception table entry, it is unacceptable
1663 * to try and continue.
1664 */
1665 if (recoverable && is_memory) {
1666 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1667 /* OK, usermode access. */
1668 recoverable = 1;
1669 } else {
1670 const struct exception_table_entry *entry;
1671
1672 entry = search_exception_tables(regs->tpc);
1673 if (entry) {
1674 /* OK, kernel access to userspace. */
1675 recoverable = 1;
1676
1677 } else {
1678 /* BAD, privileged state is corrupted. */
1679 recoverable = 0;
1680 }
1681
1682 if (recoverable) {
1683 if (pfn_valid(afar >> PAGE_SHIFT))
1684 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1685 else
1686 recoverable = 0;
1687
1688 /* Only perform fixup if we still have a
1689 * recoverable condition.
1690 */
1691 if (recoverable) {
1692 regs->tpc = entry->fixup;
1693 regs->tnpc = regs->tpc + 4;
1694 }
1695 }
1696 }
1697 } else {
1698 recoverable = 0;
1699 }
1700
1701 if (!recoverable)
1702 panic("Irrecoverable deferred error trap.\n");
1703 }
1704
1705 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1706 *
1707 * Bit0: 0=dcache,1=icache
1708 * Bit1: 0=recoverable,1=unrecoverable
1709 *
1710 * The hardware has disabled both the I-cache and D-cache in
1711 * the %dcr register.
1712 */
1713 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1714 {
1715 if (type & 0x1)
1716 __cheetah_flush_icache();
1717 else
1718 cheetah_plus_zap_dcache_parity();
1719 cheetah_flush_dcache();
1720
1721 /* Re-enable I-cache/D-cache */
1722 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1723 "or %%g1, %1, %%g1\n\t"
1724 "stxa %%g1, [%%g0] %0\n\t"
1725 "membar #Sync"
1726 : /* no outputs */
1727 : "i" (ASI_DCU_CONTROL_REG),
1728 "i" (DCU_DC | DCU_IC)
1729 : "g1");
1730
1731 if (type & 0x2) {
1732 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1733 smp_processor_id(),
1734 (type & 0x1) ? 'I' : 'D',
1735 regs->tpc);
1736 print_symbol(KERN_EMERG "TPC<%s>\n", regs->tpc);
1737 panic("Irrecoverable Cheetah+ parity error.");
1738 }
1739
1740 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1741 smp_processor_id(),
1742 (type & 0x1) ? 'I' : 'D',
1743 regs->tpc);
1744 print_symbol(KERN_WARNING "TPC<%s>\n", regs->tpc);
1745 }
1746
1747 struct sun4v_error_entry {
1748 u64 err_handle;
1749 u64 err_stick;
1750
1751 u32 err_type;
1752 #define SUN4V_ERR_TYPE_UNDEFINED 0
1753 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1754 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1755 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1756 #define SUN4V_ERR_TYPE_WARNING_RES 4
1757
1758 u32 err_attrs;
1759 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1760 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1761 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1762 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1763 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1764 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1765 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1766 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1767
1768 u64 err_raddr;
1769 u32 err_size;
1770 u16 err_cpu;
1771 u16 err_pad;
1772 };
1773
1774 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1775 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1776
1777 static const char *sun4v_err_type_to_str(u32 type)
1778 {
1779 switch (type) {
1780 case SUN4V_ERR_TYPE_UNDEFINED:
1781 return "undefined";
1782 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1783 return "uncorrected resumable";
1784 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1785 return "precise nonresumable";
1786 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1787 return "deferred nonresumable";
1788 case SUN4V_ERR_TYPE_WARNING_RES:
1789 return "warning resumable";
1790 default:
1791 return "unknown";
1792 };
1793 }
1794
1795 extern void __show_regs(struct pt_regs * regs);
1796
1797 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1798 {
1799 int cnt;
1800
1801 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1802 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1803 pfx,
1804 ent->err_handle, ent->err_stick,
1805 ent->err_type,
1806 sun4v_err_type_to_str(ent->err_type));
1807 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1808 pfx,
1809 ent->err_attrs,
1810 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1811 "processor" : ""),
1812 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1813 "memory" : ""),
1814 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1815 "pio" : ""),
1816 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1817 "integer-regs" : ""),
1818 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1819 "fpu-regs" : ""),
1820 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1821 "user" : ""),
1822 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1823 "privileged" : ""),
1824 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1825 "queue-full" : ""));
1826 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1827 pfx,
1828 ent->err_raddr, ent->err_size, ent->err_cpu);
1829
1830 __show_regs(regs);
1831
1832 if ((cnt = atomic_read(ocnt)) != 0) {
1833 atomic_set(ocnt, 0);
1834 wmb();
1835 printk("%s: Queue overflowed %d times.\n",
1836 pfx, cnt);
1837 }
1838 }
1839
1840 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1841 * Log the event and clear the first word of the entry.
1842 */
1843 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1844 {
1845 struct sun4v_error_entry *ent, local_copy;
1846 struct trap_per_cpu *tb;
1847 unsigned long paddr;
1848 int cpu;
1849
1850 cpu = get_cpu();
1851
1852 tb = &trap_block[cpu];
1853 paddr = tb->resum_kernel_buf_pa + offset;
1854 ent = __va(paddr);
1855
1856 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1857
1858 /* We have a local copy now, so release the entry. */
1859 ent->err_handle = 0;
1860 wmb();
1861
1862 put_cpu();
1863
1864 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1865 /* If err_type is 0x4, it's a powerdown request. Do
1866 * not do the usual resumable error log because that
1867 * makes it look like some abnormal error.
1868 */
1869 printk(KERN_INFO "Power down request...\n");
1870 kill_cad_pid(SIGINT, 1);
1871 return;
1872 }
1873
1874 sun4v_log_error(regs, &local_copy, cpu,
1875 KERN_ERR "RESUMABLE ERROR",
1876 &sun4v_resum_oflow_cnt);
1877 }
1878
1879 /* If we try to printk() we'll probably make matters worse, by trying
1880 * to retake locks this cpu already holds or causing more errors. So
1881 * just bump a counter, and we'll report these counter bumps above.
1882 */
1883 void sun4v_resum_overflow(struct pt_regs *regs)
1884 {
1885 atomic_inc(&sun4v_resum_oflow_cnt);
1886 }
1887
1888 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1889 * Log the event, clear the first word of the entry, and die.
1890 */
1891 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1892 {
1893 struct sun4v_error_entry *ent, local_copy;
1894 struct trap_per_cpu *tb;
1895 unsigned long paddr;
1896 int cpu;
1897
1898 cpu = get_cpu();
1899
1900 tb = &trap_block[cpu];
1901 paddr = tb->nonresum_kernel_buf_pa + offset;
1902 ent = __va(paddr);
1903
1904 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1905
1906 /* We have a local copy now, so release the entry. */
1907 ent->err_handle = 0;
1908 wmb();
1909
1910 put_cpu();
1911
1912 #ifdef CONFIG_PCI
1913 /* Check for the special PCI poke sequence. */
1914 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1915 pci_poke_faulted = 1;
1916 regs->tpc += 4;
1917 regs->tnpc = regs->tpc + 4;
1918 return;
1919 }
1920 #endif
1921
1922 sun4v_log_error(regs, &local_copy, cpu,
1923 KERN_EMERG "NON-RESUMABLE ERROR",
1924 &sun4v_nonresum_oflow_cnt);
1925
1926 panic("Non-resumable error.");
1927 }
1928
1929 /* If we try to printk() we'll probably make matters worse, by trying
1930 * to retake locks this cpu already holds or causing more errors. So
1931 * just bump a counter, and we'll report these counter bumps above.
1932 */
1933 void sun4v_nonresum_overflow(struct pt_regs *regs)
1934 {
1935 /* XXX Actually even this can make not that much sense. Perhaps
1936 * XXX we should just pull the plug and panic directly from here?
1937 */
1938 atomic_inc(&sun4v_nonresum_oflow_cnt);
1939 }
1940
1941 unsigned long sun4v_err_itlb_vaddr;
1942 unsigned long sun4v_err_itlb_ctx;
1943 unsigned long sun4v_err_itlb_pte;
1944 unsigned long sun4v_err_itlb_error;
1945
1946 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1947 {
1948 if (tl > 1)
1949 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1950
1951 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1952 regs->tpc, tl);
1953 print_symbol(KERN_EMERG "SUN4V-ITLB: TPC<%s>\n", regs->tpc);
1954 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1955 "pte[%lx] error[%lx]\n",
1956 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1957 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1958
1959 prom_halt();
1960 }
1961
1962 unsigned long sun4v_err_dtlb_vaddr;
1963 unsigned long sun4v_err_dtlb_ctx;
1964 unsigned long sun4v_err_dtlb_pte;
1965 unsigned long sun4v_err_dtlb_error;
1966
1967 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1968 {
1969 if (tl > 1)
1970 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1971
1972 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1973 regs->tpc, tl);
1974 print_symbol(KERN_EMERG "SUN4V-DTLB: TPC<%s>\n", regs->tpc);
1975 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1976 "pte[%lx] error[%lx]\n",
1977 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1978 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1979
1980 prom_halt();
1981 }
1982
1983 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1984 {
1985 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1986 err, op);
1987 }
1988
1989 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1990 {
1991 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1992 err, op);
1993 }
1994
1995 void do_fpe_common(struct pt_regs *regs)
1996 {
1997 if (regs->tstate & TSTATE_PRIV) {
1998 regs->tpc = regs->tnpc;
1999 regs->tnpc += 4;
2000 } else {
2001 unsigned long fsr = current_thread_info()->xfsr[0];
2002 siginfo_t info;
2003
2004 if (test_thread_flag(TIF_32BIT)) {
2005 regs->tpc &= 0xffffffff;
2006 regs->tnpc &= 0xffffffff;
2007 }
2008 info.si_signo = SIGFPE;
2009 info.si_errno = 0;
2010 info.si_addr = (void __user *)regs->tpc;
2011 info.si_trapno = 0;
2012 info.si_code = __SI_FAULT;
2013 if ((fsr & 0x1c000) == (1 << 14)) {
2014 if (fsr & 0x10)
2015 info.si_code = FPE_FLTINV;
2016 else if (fsr & 0x08)
2017 info.si_code = FPE_FLTOVF;
2018 else if (fsr & 0x04)
2019 info.si_code = FPE_FLTUND;
2020 else if (fsr & 0x02)
2021 info.si_code = FPE_FLTDIV;
2022 else if (fsr & 0x01)
2023 info.si_code = FPE_FLTRES;
2024 }
2025 force_sig_info(SIGFPE, &info, current);
2026 }
2027 }
2028
2029 void do_fpieee(struct pt_regs *regs)
2030 {
2031 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2032 0, 0x24, SIGFPE) == NOTIFY_STOP)
2033 return;
2034
2035 do_fpe_common(regs);
2036 }
2037
2038 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2039
2040 void do_fpother(struct pt_regs *regs)
2041 {
2042 struct fpustate *f = FPUSTATE;
2043 int ret = 0;
2044
2045 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2046 0, 0x25, SIGFPE) == NOTIFY_STOP)
2047 return;
2048
2049 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2050 case (2 << 14): /* unfinished_FPop */
2051 case (3 << 14): /* unimplemented_FPop */
2052 ret = do_mathemu(regs, f);
2053 break;
2054 }
2055 if (ret)
2056 return;
2057 do_fpe_common(regs);
2058 }
2059
2060 void do_tof(struct pt_regs *regs)
2061 {
2062 siginfo_t info;
2063
2064 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2065 0, 0x26, SIGEMT) == NOTIFY_STOP)
2066 return;
2067
2068 if (regs->tstate & TSTATE_PRIV)
2069 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2070 if (test_thread_flag(TIF_32BIT)) {
2071 regs->tpc &= 0xffffffff;
2072 regs->tnpc &= 0xffffffff;
2073 }
2074 info.si_signo = SIGEMT;
2075 info.si_errno = 0;
2076 info.si_code = EMT_TAGOVF;
2077 info.si_addr = (void __user *)regs->tpc;
2078 info.si_trapno = 0;
2079 force_sig_info(SIGEMT, &info, current);
2080 }
2081
2082 void do_div0(struct pt_regs *regs)
2083 {
2084 siginfo_t info;
2085
2086 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2087 0, 0x28, SIGFPE) == NOTIFY_STOP)
2088 return;
2089
2090 if (regs->tstate & TSTATE_PRIV)
2091 die_if_kernel("TL0: Kernel divide by zero.", regs);
2092 if (test_thread_flag(TIF_32BIT)) {
2093 regs->tpc &= 0xffffffff;
2094 regs->tnpc &= 0xffffffff;
2095 }
2096 info.si_signo = SIGFPE;
2097 info.si_errno = 0;
2098 info.si_code = FPE_INTDIV;
2099 info.si_addr = (void __user *)regs->tpc;
2100 info.si_trapno = 0;
2101 force_sig_info(SIGFPE, &info, current);
2102 }
2103
2104 void instruction_dump (unsigned int *pc)
2105 {
2106 int i;
2107
2108 if ((((unsigned long) pc) & 3))
2109 return;
2110
2111 printk("Instruction DUMP:");
2112 for (i = -3; i < 6; i++)
2113 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2114 printk("\n");
2115 }
2116
2117 static void user_instruction_dump (unsigned int __user *pc)
2118 {
2119 int i;
2120 unsigned int buf[9];
2121
2122 if ((((unsigned long) pc) & 3))
2123 return;
2124
2125 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2126 return;
2127
2128 printk("Instruction DUMP:");
2129 for (i = 0; i < 9; i++)
2130 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2131 printk("\n");
2132 }
2133
2134 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2135 {
2136 unsigned long pc, fp, thread_base, ksp;
2137 struct thread_info *tp;
2138 struct reg_window *rw;
2139 int count = 0;
2140
2141 ksp = (unsigned long) _ksp;
2142 if (!tsk)
2143 tsk = current;
2144 tp = task_thread_info(tsk);
2145 if (ksp == 0UL) {
2146 if (tsk == current)
2147 asm("mov %%fp, %0" : "=r" (ksp));
2148 else
2149 ksp = tp->ksp;
2150 }
2151 if (tp == current_thread_info())
2152 flushw_all();
2153
2154 fp = ksp + STACK_BIAS;
2155 thread_base = (unsigned long) tp;
2156
2157 printk("Call Trace:");
2158 #ifdef CONFIG_KALLSYMS
2159 printk("\n");
2160 #endif
2161 do {
2162 /* Bogus frame pointer? */
2163 if (fp < (thread_base + sizeof(struct thread_info)) ||
2164 fp >= (thread_base + THREAD_SIZE))
2165 break;
2166 rw = (struct reg_window *)fp;
2167 pc = rw->ins[7];
2168 printk(" [%016lx] ", pc);
2169 print_symbol("%s\n", pc);
2170 fp = rw->ins[6] + STACK_BIAS;
2171 } while (++count < 16);
2172 #ifndef CONFIG_KALLSYMS
2173 printk("\n");
2174 #endif
2175 }
2176
2177 void dump_stack(void)
2178 {
2179 show_stack(current, NULL);
2180 }
2181
2182 EXPORT_SYMBOL(dump_stack);
2183
2184 static inline int is_kernel_stack(struct task_struct *task,
2185 struct reg_window *rw)
2186 {
2187 unsigned long rw_addr = (unsigned long) rw;
2188 unsigned long thread_base, thread_end;
2189
2190 if (rw_addr < PAGE_OFFSET) {
2191 if (task != &init_task)
2192 return 0;
2193 }
2194
2195 thread_base = (unsigned long) task_stack_page(task);
2196 thread_end = thread_base + sizeof(union thread_union);
2197 if (rw_addr >= thread_base &&
2198 rw_addr < thread_end &&
2199 !(rw_addr & 0x7UL))
2200 return 1;
2201
2202 return 0;
2203 }
2204
2205 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2206 {
2207 unsigned long fp = rw->ins[6];
2208
2209 if (!fp)
2210 return NULL;
2211
2212 return (struct reg_window *) (fp + STACK_BIAS);
2213 }
2214
2215 void die_if_kernel(char *str, struct pt_regs *regs)
2216 {
2217 static int die_counter;
2218 extern void smp_report_regs(void);
2219 int count = 0;
2220
2221 /* Amuse the user. */
2222 printk(
2223 " \\|/ ____ \\|/\n"
2224 " \"@'/ .. \\`@\"\n"
2225 " /_| \\__/ |_\\\n"
2226 " \\__U_/\n");
2227
2228 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
2229 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2230 __asm__ __volatile__("flushw");
2231 __show_regs(regs);
2232 if (regs->tstate & TSTATE_PRIV) {
2233 struct reg_window *rw = (struct reg_window *)
2234 (regs->u_regs[UREG_FP] + STACK_BIAS);
2235
2236 /* Stop the back trace when we hit userland or we
2237 * find some badly aligned kernel stack.
2238 */
2239 while (rw &&
2240 count++ < 30&&
2241 is_kernel_stack(current, rw)) {
2242 printk("Caller[%016lx]", rw->ins[7]);
2243 print_symbol(": %s", rw->ins[7]);
2244 printk("\n");
2245
2246 rw = kernel_stack_up(rw);
2247 }
2248 instruction_dump ((unsigned int *) regs->tpc);
2249 } else {
2250 if (test_thread_flag(TIF_32BIT)) {
2251 regs->tpc &= 0xffffffff;
2252 regs->tnpc &= 0xffffffff;
2253 }
2254 user_instruction_dump ((unsigned int __user *) regs->tpc);
2255 }
2256 #if 0
2257 #ifdef CONFIG_SMP
2258 smp_report_regs();
2259 #endif
2260 #endif
2261 if (regs->tstate & TSTATE_PRIV)
2262 do_exit(SIGKILL);
2263 do_exit(SIGSEGV);
2264 }
2265
2266 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2267 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2268
2269 extern int handle_popc(u32 insn, struct pt_regs *regs);
2270 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2271 extern int vis_emul(struct pt_regs *, unsigned int);
2272
2273 void do_illegal_instruction(struct pt_regs *regs)
2274 {
2275 unsigned long pc = regs->tpc;
2276 unsigned long tstate = regs->tstate;
2277 u32 insn;
2278 siginfo_t info;
2279
2280 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2281 0, 0x10, SIGILL) == NOTIFY_STOP)
2282 return;
2283
2284 if (tstate & TSTATE_PRIV)
2285 die_if_kernel("Kernel illegal instruction", regs);
2286 if (test_thread_flag(TIF_32BIT))
2287 pc = (u32)pc;
2288 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2289 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2290 if (handle_popc(insn, regs))
2291 return;
2292 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2293 if (handle_ldf_stq(insn, regs))
2294 return;
2295 } else if (tlb_type == hypervisor) {
2296 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2297 if (!vis_emul(regs, insn))
2298 return;
2299 } else {
2300 struct fpustate *f = FPUSTATE;
2301
2302 /* XXX maybe verify XFSR bits like
2303 * XXX do_fpother() does?
2304 */
2305 if (do_mathemu(regs, f))
2306 return;
2307 }
2308 }
2309 }
2310 info.si_signo = SIGILL;
2311 info.si_errno = 0;
2312 info.si_code = ILL_ILLOPC;
2313 info.si_addr = (void __user *)pc;
2314 info.si_trapno = 0;
2315 force_sig_info(SIGILL, &info, current);
2316 }
2317
2318 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2319
2320 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2321 {
2322 siginfo_t info;
2323
2324 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2325 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2326 return;
2327
2328 if (regs->tstate & TSTATE_PRIV) {
2329 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2330 return;
2331 }
2332 info.si_signo = SIGBUS;
2333 info.si_errno = 0;
2334 info.si_code = BUS_ADRALN;
2335 info.si_addr = (void __user *)sfar;
2336 info.si_trapno = 0;
2337 force_sig_info(SIGBUS, &info, current);
2338 }
2339
2340 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2341 {
2342 siginfo_t info;
2343
2344 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2345 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2346 return;
2347
2348 if (regs->tstate & TSTATE_PRIV) {
2349 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2350 return;
2351 }
2352 info.si_signo = SIGBUS;
2353 info.si_errno = 0;
2354 info.si_code = BUS_ADRALN;
2355 info.si_addr = (void __user *) addr;
2356 info.si_trapno = 0;
2357 force_sig_info(SIGBUS, &info, current);
2358 }
2359
2360 void do_privop(struct pt_regs *regs)
2361 {
2362 siginfo_t info;
2363
2364 if (notify_die(DIE_TRAP, "privileged operation", regs,
2365 0, 0x11, SIGILL) == NOTIFY_STOP)
2366 return;
2367
2368 if (test_thread_flag(TIF_32BIT)) {
2369 regs->tpc &= 0xffffffff;
2370 regs->tnpc &= 0xffffffff;
2371 }
2372 info.si_signo = SIGILL;
2373 info.si_errno = 0;
2374 info.si_code = ILL_PRVOPC;
2375 info.si_addr = (void __user *)regs->tpc;
2376 info.si_trapno = 0;
2377 force_sig_info(SIGILL, &info, current);
2378 }
2379
2380 void do_privact(struct pt_regs *regs)
2381 {
2382 do_privop(regs);
2383 }
2384
2385 /* Trap level 1 stuff or other traps we should never see... */
2386 void do_cee(struct pt_regs *regs)
2387 {
2388 die_if_kernel("TL0: Cache Error Exception", regs);
2389 }
2390
2391 void do_cee_tl1(struct pt_regs *regs)
2392 {
2393 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2394 die_if_kernel("TL1: Cache Error Exception", regs);
2395 }
2396
2397 void do_dae_tl1(struct pt_regs *regs)
2398 {
2399 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2400 die_if_kernel("TL1: Data Access Exception", regs);
2401 }
2402
2403 void do_iae_tl1(struct pt_regs *regs)
2404 {
2405 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2406 die_if_kernel("TL1: Instruction Access Exception", regs);
2407 }
2408
2409 void do_div0_tl1(struct pt_regs *regs)
2410 {
2411 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2412 die_if_kernel("TL1: DIV0 Exception", regs);
2413 }
2414
2415 void do_fpdis_tl1(struct pt_regs *regs)
2416 {
2417 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2418 die_if_kernel("TL1: FPU Disabled", regs);
2419 }
2420
2421 void do_fpieee_tl1(struct pt_regs *regs)
2422 {
2423 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2424 die_if_kernel("TL1: FPU IEEE Exception", regs);
2425 }
2426
2427 void do_fpother_tl1(struct pt_regs *regs)
2428 {
2429 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2430 die_if_kernel("TL1: FPU Other Exception", regs);
2431 }
2432
2433 void do_ill_tl1(struct pt_regs *regs)
2434 {
2435 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2436 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2437 }
2438
2439 void do_irq_tl1(struct pt_regs *regs)
2440 {
2441 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2442 die_if_kernel("TL1: IRQ Exception", regs);
2443 }
2444
2445 void do_lddfmna_tl1(struct pt_regs *regs)
2446 {
2447 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2448 die_if_kernel("TL1: LDDF Exception", regs);
2449 }
2450
2451 void do_stdfmna_tl1(struct pt_regs *regs)
2452 {
2453 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2454 die_if_kernel("TL1: STDF Exception", regs);
2455 }
2456
2457 void do_paw(struct pt_regs *regs)
2458 {
2459 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2460 }
2461
2462 void do_paw_tl1(struct pt_regs *regs)
2463 {
2464 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2465 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2466 }
2467
2468 void do_vaw(struct pt_regs *regs)
2469 {
2470 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2471 }
2472
2473 void do_vaw_tl1(struct pt_regs *regs)
2474 {
2475 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2476 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2477 }
2478
2479 void do_tof_tl1(struct pt_regs *regs)
2480 {
2481 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2482 die_if_kernel("TL1: Tag Overflow Exception", regs);
2483 }
2484
2485 void do_getpsr(struct pt_regs *regs)
2486 {
2487 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2488 regs->tpc = regs->tnpc;
2489 regs->tnpc += 4;
2490 if (test_thread_flag(TIF_32BIT)) {
2491 regs->tpc &= 0xffffffff;
2492 regs->tnpc &= 0xffffffff;
2493 }
2494 }
2495
2496 struct trap_per_cpu trap_block[NR_CPUS];
2497
2498 /* This can get invoked before sched_init() so play it super safe
2499 * and use hard_smp_processor_id().
2500 */
2501 void init_cur_cpu_trap(struct thread_info *t)
2502 {
2503 int cpu = hard_smp_processor_id();
2504 struct trap_per_cpu *p = &trap_block[cpu];
2505
2506 p->thread = t;
2507 p->pgd_paddr = 0;
2508 }
2509
2510 extern void thread_info_offsets_are_bolixed_dave(void);
2511 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2512 extern void tsb_config_offsets_are_bolixed_dave(void);
2513
2514 /* Only invoked on boot processor. */
2515 void __init trap_init(void)
2516 {
2517 /* Compile time sanity check. */
2518 if (TI_TASK != offsetof(struct thread_info, task) ||
2519 TI_FLAGS != offsetof(struct thread_info, flags) ||
2520 TI_CPU != offsetof(struct thread_info, cpu) ||
2521 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2522 TI_KSP != offsetof(struct thread_info, ksp) ||
2523 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2524 TI_KREGS != offsetof(struct thread_info, kregs) ||
2525 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2526 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2527 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2528 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2529 TI_GSR != offsetof(struct thread_info, gsr) ||
2530 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2531 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2532 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2533 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2534 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2535 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2536 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2537 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2538 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2539 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2540 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2541 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2542 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2543 (TI_FPREGS & (64 - 1)))
2544 thread_info_offsets_are_bolixed_dave();
2545
2546 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2547 (TRAP_PER_CPU_PGD_PADDR !=
2548 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2549 (TRAP_PER_CPU_CPU_MONDO_PA !=
2550 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2551 (TRAP_PER_CPU_DEV_MONDO_PA !=
2552 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2553 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2554 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2555 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2556 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2557 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2558 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2559 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2560 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2561 (TRAP_PER_CPU_FAULT_INFO !=
2562 offsetof(struct trap_per_cpu, fault_info)) ||
2563 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2564 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2565 (TRAP_PER_CPU_CPU_LIST_PA !=
2566 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2567 (TRAP_PER_CPU_TSB_HUGE !=
2568 offsetof(struct trap_per_cpu, tsb_huge)) ||
2569 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2570 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2571 (TRAP_PER_CPU_IRQ_WORKLIST !=
2572 offsetof(struct trap_per_cpu, irq_worklist)) ||
2573 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2574 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2575 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2576 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2577 (TRAP_PER_CPU_RESUM_QMASK !=
2578 offsetof(struct trap_per_cpu, resum_qmask)) ||
2579 (TRAP_PER_CPU_NONRESUM_QMASK !=
2580 offsetof(struct trap_per_cpu, nonresum_qmask)))
2581 trap_per_cpu_offsets_are_bolixed_dave();
2582
2583 if ((TSB_CONFIG_TSB !=
2584 offsetof(struct tsb_config, tsb)) ||
2585 (TSB_CONFIG_RSS_LIMIT !=
2586 offsetof(struct tsb_config, tsb_rss_limit)) ||
2587 (TSB_CONFIG_NENTRIES !=
2588 offsetof(struct tsb_config, tsb_nentries)) ||
2589 (TSB_CONFIG_REG_VAL !=
2590 offsetof(struct tsb_config, tsb_reg_val)) ||
2591 (TSB_CONFIG_MAP_VADDR !=
2592 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2593 (TSB_CONFIG_MAP_PTE !=
2594 offsetof(struct tsb_config, tsb_map_pte)))
2595 tsb_config_offsets_are_bolixed_dave();
2596
2597 /* Attach to the address space of init_task. On SMP we
2598 * do this in smp.c:smp_callin for other cpus.
2599 */
2600 atomic_inc(&init_mm.mm_count);
2601 current->active_mm = &init_mm;
2602 }
Tomato firmware and modifications.