2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
6 * In addition to the individual control of the communication
7 * channels, there are a few functions that globally affect the
8 * communication processor.
10 * Buffer descriptors must be allocated from the dual ported memory
11 * space. The allocator for that is here. When the communication
12 * process is reset, we reclaim the memory available. There is
13 * currently no deallocator for this memory.
14 * The amount of space available is platform dependent. On the
15 * MBX, the EPPC software loads additional microcode into the
16 * communication processor, and uses some of the DP ram for this
17 * purpose. Current, the first 512 bytes and the last 256 bytes of
18 * memory are used. Right now I am conservative and only use the
19 * memory that can never be used for microcode. If there are
20 * applications that require more DP ram, we can expand the boundaries
21 * but then we have to be careful of any downloaded microcode.
23 #include <linux/errno.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/param.h>
28 #include <linux/string.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <asm/mpc8xx.h>
35 #include <asm/pgtable.h>
36 #include <asm/8xx_immap.h>
37 #include <asm/commproc.h>
39 #include <asm/tlbflush.h>
40 #include <asm/rheap.h>
43 #include <asm/fs_pd.h>
45 #define CPM_MAP_SIZE (0x4000)
47 static void m8xx_cpm_dpinit(void);
48 static uint host_buffer
; /* One page of host buffer */
49 static uint host_end
; /* end + 1 */
50 cpm8xx_t
*cpmp
; /* Pointer to comm processor space */
53 static struct device_node
*cpm_pic_node
;
54 static struct irq_host
*cpm_pic_host
;
56 static void cpm_mask_irq(unsigned int irq
)
58 unsigned int cpm_vec
= (unsigned int)irq_map
[irq
].hwirq
;
60 clrbits32(&cpic_reg
->cpic_cimr
, (1 << cpm_vec
));
63 static void cpm_unmask_irq(unsigned int irq
)
65 unsigned int cpm_vec
= (unsigned int)irq_map
[irq
].hwirq
;
67 setbits32(&cpic_reg
->cpic_cimr
, (1 << cpm_vec
));
70 static void cpm_end_irq(unsigned int irq
)
72 unsigned int cpm_vec
= (unsigned int)irq_map
[irq
].hwirq
;
74 out_be32(&cpic_reg
->cpic_cisr
, (1 << cpm_vec
));
77 static struct irq_chip cpm_pic
= {
78 .typename
= " CPM PIC ",
80 .unmask
= cpm_unmask_irq
,
88 /* Get the vector by setting the ACK bit and then reading
91 out_be16(&cpic_reg
->cpic_civr
, 1);
92 cpm_vec
= in_be16(&cpic_reg
->cpic_civr
);
95 return irq_linear_revmap(cpm_pic_host
, cpm_vec
);
98 static int cpm_pic_host_match(struct irq_host
*h
, struct device_node
*node
)
100 return cpm_pic_node
== node
;
103 static int cpm_pic_host_map(struct irq_host
*h
, unsigned int virq
,
106 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq
, hw
);
108 get_irq_desc(virq
)->status
|= IRQ_LEVEL
;
109 set_irq_chip_and_handler(virq
, &cpm_pic
, handle_fasteoi_irq
);
113 /* The CPM can generate the error interrupt when there is a race condition
114 * between generating and masking interrupts. All we have to do is ACK it
115 * and return. This is a no-op function so we don't need any special
116 * tests in the interrupt handler.
118 static irqreturn_t
cpm_error_interrupt(int irq
, void *dev
)
123 static struct irqaction cpm_error_irqaction
= {
124 .handler
= cpm_error_interrupt
,
125 .mask
= CPU_MASK_NONE
,
129 static struct irq_host_ops cpm_pic_host_ops
= {
130 .match
= cpm_pic_host_match
,
131 .map
= cpm_pic_host_map
,
134 unsigned int cpm_pic_init(void)
136 struct device_node
*np
= NULL
;
138 unsigned int sirq
= NO_IRQ
, hwirq
, eirq
;
141 pr_debug("cpm_pic_init\n");
143 np
= of_find_compatible_node(NULL
, "cpm-pic", "CPM");
145 printk(KERN_ERR
"CPM PIC init: can not find cpm-pic node\n");
148 ret
= of_address_to_resource(np
, 0, &res
);
152 cpic_reg
= (void *)ioremap(res
.start
, res
.end
- res
.start
+ 1);
153 if (cpic_reg
== NULL
)
156 sirq
= irq_of_parse_and_map(np
, 0);
160 /* Initialize the CPM interrupt controller. */
161 hwirq
= (unsigned int)irq_map
[sirq
].hwirq
;
162 out_be32(&cpic_reg
->cpic_cicr
,
163 (CICR_SCD_SCC4
| CICR_SCC_SCC3
| CICR_SCB_SCC2
| CICR_SCA_SCC1
) |
164 ((hwirq
/2) << 13) | CICR_HP_MASK
);
166 out_be32(&cpic_reg
->cpic_cimr
, 0);
168 cpm_pic_node
= of_node_get(np
);
170 cpm_pic_host
= irq_alloc_host(IRQ_HOST_MAP_LINEAR
, 64, &cpm_pic_host_ops
, 64);
171 if (cpm_pic_host
== NULL
) {
172 printk(KERN_ERR
"CPM2 PIC: failed to allocate irq host!\n");
178 /* Install our own error handler. */
179 np
= of_find_node_by_type(NULL
, "cpm");
181 printk(KERN_ERR
"CPM PIC init: can not find cpm node\n");
184 eirq
= irq_of_parse_and_map(np
, 0);
188 if (setup_irq(eirq
, &cpm_error_irqaction
))
189 printk(KERN_ERR
"Could not allocate CPM error IRQ!");
191 setbits32(&cpic_reg
->cpic_cicr
, CICR_IEN
);
201 sysconf8xx_t
*siu_conf
;
203 commproc
= (cpm8xx_t
*)ioremap(CPM_MAP_ADDR
, CPM_MAP_SIZE
);
205 #ifdef CONFIG_UCODE_PATCH
208 out_be16(&commproc
->cp_cpcr
, CPM_CR_RST
| CPM_CR_FLG
);
212 while (in_be16(&commproc
->cp_cpcr
) & CPM_CR_FLG
);
214 cpm_load_patch(commproc
);
217 /* Set SDMA Bus Request priority 5.
218 * On 860T, this also enables FEC priority 6. I am not sure
219 * this is what we realy want for some applications, but the
220 * manual recommends it.
221 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
223 siu_conf
= (sysconf8xx_t
*)immr_map(im_siu_conf
);
224 out_be32(&siu_conf
->sc_sdcr
, 1);
225 immr_unmap(siu_conf
);
227 /* Reclaim the DP memory for our use. */
230 /* Tell everyone where the comm processor resides.
235 /* We used to do this earlier, but have to postpone as long as possible
236 * to ensure the kernel VM is now running.
239 alloc_host_memory(void)
243 /* Set the host page for allocation.
245 host_buffer
= (uint
)dma_alloc_coherent(NULL
, PAGE_SIZE
, &physaddr
,
247 host_end
= host_buffer
+ PAGE_SIZE
;
250 /* We also own one page of host buffer space for the allocation of
251 * UART "fifos" and the like.
254 m8xx_cpm_hostalloc(uint size
)
258 if (host_buffer
== 0)
261 if ((host_buffer
+ size
) >= host_end
)
264 retloc
= host_buffer
;
270 /* Set a baud rate generator. This needs lots of work. There are
271 * four BRGs, any of which can be wired to any channel.
272 * The internal baud rate clock is the system clock divided by 16.
273 * This assumes the baudrate is 16x oversampled by the uart.
275 #define BRG_INT_CLK (get_brgfreq())
276 #define BRG_UART_CLK (BRG_INT_CLK/16)
277 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
280 cpm_setbrg(uint brg
, uint rate
)
284 /* This is good enough to get SMCs running.....
286 bp
= (uint
*)&cpmp
->cp_brgc1
;
288 /* The BRG has a 12-bit counter. For really slow baud rates (or
289 * really fast processors), we may have to further divide by 16.
291 if (((BRG_UART_CLK
/ rate
) - 1) < 4096)
292 *bp
= (((BRG_UART_CLK
/ rate
) - 1) << 1) | CPM_BRG_EN
;
294 *bp
= (((BRG_UART_CLK_DIV16
/ rate
) - 1) << 1) |
295 CPM_BRG_EN
| CPM_BRG_DIV16
;
299 * dpalloc / dpfree bits.
301 static spinlock_t cpm_dpmem_lock
;
303 * 16 blocks should be enough to satisfy all requests
304 * until the memory subsystem goes up...
306 static rh_block_t cpm_boot_dpmem_rh_block
[16];
307 static rh_info_t cpm_dpmem_info
;
309 #define CPM_DPMEM_ALIGNMENT 8
310 static u8
* dpram_vbase
;
311 static uint dpram_pbase
;
313 void m8xx_cpm_dpinit(void)
315 spin_lock_init(&cpm_dpmem_lock
);
317 dpram_vbase
= immr_map_size(im_cpm
.cp_dpmem
, CPM_DATAONLY_BASE
+ CPM_DATAONLY_SIZE
);
318 dpram_pbase
= (uint
)&((immap_t
*)IMAP_ADDR
)->im_cpm
.cp_dpmem
;
320 /* Initialize the info header */
321 rh_init(&cpm_dpmem_info
, CPM_DPMEM_ALIGNMENT
,
322 sizeof(cpm_boot_dpmem_rh_block
) /
323 sizeof(cpm_boot_dpmem_rh_block
[0]),
324 cpm_boot_dpmem_rh_block
);
327 * Attach the usable dpmem area.
328 * XXX: This is actually crap. CPM_DATAONLY_BASE and
329 * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
330 * with the processor and the microcode patches applied / activated.
331 * But the following should be at least safe.
333 rh_attach_region(&cpm_dpmem_info
, CPM_DATAONLY_BASE
, CPM_DATAONLY_SIZE
);
337 * Allocate the requested size worth of DP memory.
338 * This function returns an offset into the DPRAM area.
339 * Use cpm_dpram_addr() to get the virtual address of the area.
341 unsigned long cpm_dpalloc(uint size
, uint align
)
346 spin_lock_irqsave(&cpm_dpmem_lock
, flags
);
347 cpm_dpmem_info
.alignment
= align
;
348 start
= rh_alloc(&cpm_dpmem_info
, size
, "commproc");
349 spin_unlock_irqrestore(&cpm_dpmem_lock
, flags
);
353 EXPORT_SYMBOL(cpm_dpalloc
);
355 int cpm_dpfree(unsigned long offset
)
360 spin_lock_irqsave(&cpm_dpmem_lock
, flags
);
361 ret
= rh_free(&cpm_dpmem_info
, offset
);
362 spin_unlock_irqrestore(&cpm_dpmem_lock
, flags
);
366 EXPORT_SYMBOL(cpm_dpfree
);
368 unsigned long cpm_dpalloc_fixed(unsigned long offset
, uint size
, uint align
)
373 spin_lock_irqsave(&cpm_dpmem_lock
, flags
);
374 cpm_dpmem_info
.alignment
= align
;
375 start
= rh_alloc_fixed(&cpm_dpmem_info
, offset
, size
, "commproc");
376 spin_unlock_irqrestore(&cpm_dpmem_lock
, flags
);
380 EXPORT_SYMBOL(cpm_dpalloc_fixed
);
382 void cpm_dpdump(void)
384 rh_dump(&cpm_dpmem_info
);
386 EXPORT_SYMBOL(cpm_dpdump
);
388 void *cpm_dpram_addr(unsigned long offset
)
390 return (void *)(dpram_vbase
+ offset
);
392 EXPORT_SYMBOL(cpm_dpram_addr
);
394 uint
cpm_dpram_phys(u8
* addr
)
396 return (dpram_pbase
+ (uint
)(addr
- dpram_vbase
));
398 EXPORT_SYMBOL(cpm_dpram_addr
);