2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19 #include <linux/irq.h>
21 #include <asm/sections.h>
24 #include <asm/pci-bridge.h>
25 #include <asm/machdep.h>
26 #include <asm/pmac_feature.h>
27 #include <asm/grackle.h>
28 #include <asm/ppc-pci.h>
33 #define DBG(x...) printk(x)
38 static int add_bridge(struct device_node
*dev
);
40 /* XXX Could be per-controller, but I don't think we risk anything by
41 * assuming we won't have both UniNorth and Bandit */
42 static int has_uninorth
;
44 static struct pci_controller
*u3_agp
;
45 static struct pci_controller
*u4_pcie
;
46 static struct pci_controller
*u3_ht
;
48 static int has_second_ohare
;
49 #endif /* CONFIG_PPC64 */
51 extern int pcibios_assign_bus_offset
;
53 struct device_node
*k2_skiplist
[2];
56 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
58 #define BANDIT_DEVID_2 8
59 #define BANDIT_REVID 3
61 #define BANDIT_DEVNUM 11
62 #define BANDIT_MAGIC 0x50
63 #define BANDIT_COHERENT 0x40
65 static int __init
fixup_one_level_bus_range(struct device_node
*node
, int higher
)
67 for (; node
!= 0;node
= node
->sibling
) {
68 const int * bus_range
;
69 const unsigned int *class_code
;
72 /* For PCI<->PCI bridges or CardBus bridges, we go down */
73 class_code
= of_get_property(node
, "class-code", NULL
);
74 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
75 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
77 bus_range
= of_get_property(node
, "bus-range", &len
);
78 if (bus_range
!= NULL
&& len
> 2 * sizeof(int)) {
79 if (bus_range
[1] > higher
)
80 higher
= bus_range
[1];
82 higher
= fixup_one_level_bus_range(node
->child
, higher
);
87 /* This routine fixes the "bus-range" property of all bridges in the
88 * system since they tend to have their "last" member wrong on macs
90 * Note that the bus numbers manipulated here are OF bus numbers, they
91 * are not Linux bus numbers.
93 static void __init
fixup_bus_range(struct device_node
*bridge
)
96 struct property
*prop
;
98 /* Lookup the "bus-range" property for the hose */
99 prop
= of_find_property(bridge
, "bus-range", &len
);
100 if (prop
== NULL
|| prop
->length
< 2 * sizeof(int))
103 bus_range
= prop
->value
;
104 bus_range
[1] = fixup_one_level_bus_range(bridge
->child
, bus_range
[1]);
108 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
110 * The "Bandit" version is present in all early PCI PowerMacs,
111 * and up to the first ones using Grackle. Some machines may
112 * have 2 bandit controllers (2 PCI busses).
114 * "Chaos" is used in some "Bandit"-type machines as a bridge
115 * for the separate display bus. It is accessed the same
116 * way as bandit, but cannot be probed for devices. It therefore
117 * has its own config access functions.
119 * The "UniNorth" version is present in all Core99 machines
120 * (iBook, G4, new IMacs, and all the recent Apple machines).
121 * It contains 3 controllers in one ASIC.
123 * The U3 is the bridge used on G5 machines. It contains an
124 * AGP bus which is dealt with the old UniNorth access routines
125 * and a HyperTransport bus which uses its own set of access
129 #define MACRISC_CFA0(devfn, off) \
130 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
131 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
132 | (((unsigned int)(off)) & 0xFCUL))
134 #define MACRISC_CFA1(bus, devfn, off) \
135 ((((unsigned int)(bus)) << 16) \
136 |(((unsigned int)(devfn)) << 8) \
137 |(((unsigned int)(off)) & 0xFCUL) \
140 static volatile void __iomem
*macrisc_cfg_access(struct pci_controller
* hose
,
141 u8 bus
, u8 dev_fn
, u8 offset
)
145 if (bus
== hose
->first_busno
) {
146 if (dev_fn
< (11 << 3))
148 caddr
= MACRISC_CFA0(dev_fn
, offset
);
150 caddr
= MACRISC_CFA1(bus
, dev_fn
, offset
);
152 /* Uninorth will return garbage if we don't read back the value ! */
154 out_le32(hose
->cfg_addr
, caddr
);
155 } while (in_le32(hose
->cfg_addr
) != caddr
);
157 offset
&= has_uninorth
? 0x07 : 0x03;
158 return hose
->cfg_data
+ offset
;
161 static int macrisc_read_config(struct pci_bus
*bus
, unsigned int devfn
,
162 int offset
, int len
, u32
*val
)
164 struct pci_controller
*hose
;
165 volatile void __iomem
*addr
;
167 hose
= pci_bus_to_host(bus
);
169 return PCIBIOS_DEVICE_NOT_FOUND
;
171 return PCIBIOS_BAD_REGISTER_NUMBER
;
172 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
174 return PCIBIOS_DEVICE_NOT_FOUND
;
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
184 *val
= in_le16(addr
);
187 *val
= in_le32(addr
);
190 return PCIBIOS_SUCCESSFUL
;
193 static int macrisc_write_config(struct pci_bus
*bus
, unsigned int devfn
,
194 int offset
, int len
, u32 val
)
196 struct pci_controller
*hose
;
197 volatile void __iomem
*addr
;
199 hose
= pci_bus_to_host(bus
);
201 return PCIBIOS_DEVICE_NOT_FOUND
;
203 return PCIBIOS_BAD_REGISTER_NUMBER
;
204 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
206 return PCIBIOS_DEVICE_NOT_FOUND
;
208 * Note: the caller has already checked that offset is
209 * suitably aligned and that len is 1, 2 or 4.
218 (void) in_le16(addr
);
222 (void) in_le32(addr
);
225 return PCIBIOS_SUCCESSFUL
;
228 static struct pci_ops macrisc_pci_ops
=
236 * Verify that a specific (bus, dev_fn) exists on chaos
238 static int chaos_validate_dev(struct pci_bus
*bus
, int devfn
, int offset
)
240 struct device_node
*np
;
241 const u32
*vendor
, *device
;
244 return PCIBIOS_BAD_REGISTER_NUMBER
;
245 np
= pci_busdev_to_OF_node(bus
, devfn
);
247 return PCIBIOS_DEVICE_NOT_FOUND
;
249 vendor
= of_get_property(np
, "vendor-id", NULL
);
250 device
= of_get_property(np
, "device-id", NULL
);
251 if (vendor
== NULL
|| device
== NULL
)
252 return PCIBIOS_DEVICE_NOT_FOUND
;
254 if ((*vendor
== 0x106b) && (*device
== 3) && (offset
>= 0x10)
255 && (offset
!= 0x14) && (offset
!= 0x18) && (offset
<= 0x24))
256 return PCIBIOS_BAD_REGISTER_NUMBER
;
258 return PCIBIOS_SUCCESSFUL
;
262 chaos_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
265 int result
= chaos_validate_dev(bus
, devfn
, offset
);
266 if (result
== PCIBIOS_BAD_REGISTER_NUMBER
)
268 if (result
!= PCIBIOS_SUCCESSFUL
)
270 return macrisc_read_config(bus
, devfn
, offset
, len
, val
);
274 chaos_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
277 int result
= chaos_validate_dev(bus
, devfn
, offset
);
278 if (result
!= PCIBIOS_SUCCESSFUL
)
280 return macrisc_write_config(bus
, devfn
, offset
, len
, val
);
283 static struct pci_ops chaos_pci_ops
=
289 static void __init
setup_chaos(struct pci_controller
*hose
,
290 struct resource
*addr
)
292 /* assume a `chaos' bridge */
293 hose
->ops
= &chaos_pci_ops
;
294 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
295 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
297 #endif /* CONFIG_PPC32 */
301 * These versions of U3 HyperTransport config space access ops do not
302 * implement self-view of the HT host yet
306 * This function deals with some "special cases" devices.
308 * 0 -> No special case
309 * 1 -> Skip the device but act as if the access was successfull
310 * (return 0xff's on reads, eventually, cache config space
311 * accesses in a later version)
312 * -1 -> Hide the device (unsuccessful acess)
314 static int u3_ht_skip_device(struct pci_controller
*hose
,
315 struct pci_bus
*bus
, unsigned int devfn
)
317 struct device_node
*busdn
, *dn
;
320 /* We only allow config cycles to devices that are in OF device-tree
321 * as we are apparently having some weird things going on with some
322 * revs of K2 on recent G5s
325 busdn
= pci_device_to_OF_node(bus
->self
);
327 busdn
= hose
->arch_data
;
328 for (dn
= busdn
->child
; dn
; dn
= dn
->sibling
)
329 if (PCI_DN(dn
) && PCI_DN(dn
)->devfn
== devfn
)
335 * When a device in K2 is powered down, we die on config
336 * cycle accesses. Fix that here.
339 if (k2_skiplist
[i
] == dn
)
345 #define U3_HT_CFA0(devfn, off) \
346 ((((unsigned int)devfn) << 8) | offset)
347 #define U3_HT_CFA1(bus, devfn, off) \
348 (U3_HT_CFA0(devfn, off) \
349 + (((unsigned int)bus) << 16) \
352 static volatile void __iomem
*u3_ht_cfg_access(struct pci_controller
* hose
,
353 u8 bus
, u8 devfn
, u8 offset
)
355 if (bus
== hose
->first_busno
) {
356 /* For now, we don't self probe U3 HT bridge */
357 if (PCI_SLOT(devfn
) == 0)
359 return hose
->cfg_data
+ U3_HT_CFA0(devfn
, offset
);
361 return hose
->cfg_data
+ U3_HT_CFA1(bus
, devfn
, offset
);
364 static int u3_ht_read_config(struct pci_bus
*bus
, unsigned int devfn
,
365 int offset
, int len
, u32
*val
)
367 struct pci_controller
*hose
;
368 volatile void __iomem
*addr
;
370 hose
= pci_bus_to_host(bus
);
372 return PCIBIOS_DEVICE_NOT_FOUND
;
374 return PCIBIOS_BAD_REGISTER_NUMBER
;
375 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
377 return PCIBIOS_DEVICE_NOT_FOUND
;
379 switch (u3_ht_skip_device(hose
, bus
, devfn
)) {
387 *val
= 0xffff; break;
389 *val
= 0xfffffffful
; break;
391 return PCIBIOS_SUCCESSFUL
;
393 return PCIBIOS_DEVICE_NOT_FOUND
;
397 * Note: the caller has already checked that offset is
398 * suitably aligned and that len is 1, 2 or 4.
405 *val
= in_le16(addr
);
408 *val
= in_le32(addr
);
411 return PCIBIOS_SUCCESSFUL
;
414 static int u3_ht_write_config(struct pci_bus
*bus
, unsigned int devfn
,
415 int offset
, int len
, u32 val
)
417 struct pci_controller
*hose
;
418 volatile void __iomem
*addr
;
420 hose
= pci_bus_to_host(bus
);
422 return PCIBIOS_DEVICE_NOT_FOUND
;
424 return PCIBIOS_BAD_REGISTER_NUMBER
;
425 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
427 return PCIBIOS_DEVICE_NOT_FOUND
;
429 switch (u3_ht_skip_device(hose
, bus
, devfn
)) {
433 return PCIBIOS_SUCCESSFUL
;
435 return PCIBIOS_DEVICE_NOT_FOUND
;
439 * Note: the caller has already checked that offset is
440 * suitably aligned and that len is 1, 2 or 4.
449 (void) in_le16(addr
);
452 out_le32((u32 __iomem
*)addr
, val
);
453 (void) in_le32(addr
);
456 return PCIBIOS_SUCCESSFUL
;
459 static struct pci_ops u3_ht_pci_ops
=
465 #define U4_PCIE_CFA0(devfn, off) \
466 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
467 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
468 | ((((unsigned int)(off)) >> 8) << 28) \
469 | (((unsigned int)(off)) & 0xfcU))
471 #define U4_PCIE_CFA1(bus, devfn, off) \
472 ((((unsigned int)(bus)) << 16) \
473 |(((unsigned int)(devfn)) << 8) \
474 | ((((unsigned int)(off)) >> 8) << 28) \
475 |(((unsigned int)(off)) & 0xfcU) \
478 static volatile void __iomem
*u4_pcie_cfg_access(struct pci_controller
* hose
,
479 u8 bus
, u8 dev_fn
, int offset
)
483 if (bus
== hose
->first_busno
) {
484 caddr
= U4_PCIE_CFA0(dev_fn
, offset
);
486 caddr
= U4_PCIE_CFA1(bus
, dev_fn
, offset
);
488 /* Uninorth will return garbage if we don't read back the value ! */
490 out_le32(hose
->cfg_addr
, caddr
);
491 } while (in_le32(hose
->cfg_addr
) != caddr
);
494 return hose
->cfg_data
+ offset
;
497 static int u4_pcie_read_config(struct pci_bus
*bus
, unsigned int devfn
,
498 int offset
, int len
, u32
*val
)
500 struct pci_controller
*hose
;
501 volatile void __iomem
*addr
;
503 hose
= pci_bus_to_host(bus
);
505 return PCIBIOS_DEVICE_NOT_FOUND
;
506 if (offset
>= 0x1000)
507 return PCIBIOS_BAD_REGISTER_NUMBER
;
508 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
510 return PCIBIOS_DEVICE_NOT_FOUND
;
512 * Note: the caller has already checked that offset is
513 * suitably aligned and that len is 1, 2 or 4.
520 *val
= in_le16(addr
);
523 *val
= in_le32(addr
);
526 return PCIBIOS_SUCCESSFUL
;
529 static int u4_pcie_write_config(struct pci_bus
*bus
, unsigned int devfn
,
530 int offset
, int len
, u32 val
)
532 struct pci_controller
*hose
;
533 volatile void __iomem
*addr
;
535 hose
= pci_bus_to_host(bus
);
537 return PCIBIOS_DEVICE_NOT_FOUND
;
538 if (offset
>= 0x1000)
539 return PCIBIOS_BAD_REGISTER_NUMBER
;
540 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
542 return PCIBIOS_DEVICE_NOT_FOUND
;
544 * Note: the caller has already checked that offset is
545 * suitably aligned and that len is 1, 2 or 4.
554 (void) in_le16(addr
);
558 (void) in_le32(addr
);
561 return PCIBIOS_SUCCESSFUL
;
564 static struct pci_ops u4_pcie_pci_ops
=
570 #endif /* CONFIG_PPC64 */
574 * For a bandit bridge, turn on cache coherency if necessary.
575 * N.B. we could clean this up using the hose ops directly.
577 static void __init
init_bandit(struct pci_controller
*bp
)
579 unsigned int vendev
, magic
;
582 /* read the word at offset 0 in config space for device 11 */
583 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + PCI_VENDOR_ID
);
585 vendev
= in_le32(bp
->cfg_data
);
586 if (vendev
== (PCI_DEVICE_ID_APPLE_BANDIT
<< 16) +
587 PCI_VENDOR_ID_APPLE
) {
588 /* read the revision id */
589 out_le32(bp
->cfg_addr
,
590 (1UL << BANDIT_DEVNUM
) + PCI_REVISION_ID
);
592 rev
= in_8(bp
->cfg_data
);
593 if (rev
!= BANDIT_REVID
)
595 "Unknown revision %d for bandit\n", rev
);
596 } else if (vendev
!= (BANDIT_DEVID_2
<< 16) + PCI_VENDOR_ID_APPLE
) {
597 printk(KERN_WARNING
"bandit isn't? (%x)\n", vendev
);
601 /* read the word at offset 0x50 */
602 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + BANDIT_MAGIC
);
604 magic
= in_le32(bp
->cfg_data
);
605 if ((magic
& BANDIT_COHERENT
) != 0)
607 magic
|= BANDIT_COHERENT
;
609 out_le32(bp
->cfg_data
, magic
);
610 printk(KERN_INFO
"Cache coherency enabled for bandit/PSX\n");
614 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
616 static void __init
init_p2pbridge(void)
618 struct device_node
*p2pbridge
;
619 struct pci_controller
* hose
;
623 /* XXX it would be better here to identify the specific
624 PCI-PCI bridge chip we have. */
625 p2pbridge
= of_find_node_by_name(NULL
, "pci-bridge");
626 if (p2pbridge
== NULL
627 || p2pbridge
->parent
== NULL
628 || strcmp(p2pbridge
->parent
->name
, "pci") != 0)
630 if (pci_device_from_OF_node(p2pbridge
, &bus
, &devfn
) < 0) {
631 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
634 /* Warning: At this point, we have not yet renumbered all busses.
635 * So we must use OF walking to find out hose
637 hose
= pci_find_hose_for_OF_device(p2pbridge
);
639 DBG("Can't find hose for PCI<->PCI bridge\n");
642 if (early_read_config_word(hose
, bus
, devfn
,
643 PCI_BRIDGE_CONTROL
, &val
) < 0) {
644 printk(KERN_ERR
"init_p2pbridge: couldn't read bridge"
648 val
&= ~PCI_BRIDGE_CTL_MASTER_ABORT
;
649 early_write_config_word(hose
, bus
, devfn
, PCI_BRIDGE_CONTROL
, val
);
651 of_node_put(p2pbridge
);
654 static void __init
init_second_ohare(void)
656 struct device_node
*np
= of_find_node_by_name(NULL
, "pci106b,7");
657 unsigned char bus
, devfn
;
663 /* This must run before we initialize the PICs since the second
664 * ohare hosts a PIC that will be accessed there.
666 if (pci_device_from_OF_node(np
, &bus
, &devfn
) == 0) {
667 struct pci_controller
* hose
=
668 pci_find_hose_for_OF_device(np
);
670 printk(KERN_ERR
"Can't find PCI hose for OHare2 !\n");
673 early_read_config_word(hose
, bus
, devfn
, PCI_COMMAND
, &cmd
);
674 cmd
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
675 cmd
&= ~PCI_COMMAND_IO
;
676 early_write_config_word(hose
, bus
, devfn
, PCI_COMMAND
, cmd
);
678 has_second_ohare
= 1;
682 * Some Apple desktop machines have a NEC PD720100A USB2 controller
683 * on the motherboard. Open Firmware, on these, will disable the
684 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
685 * code re-enables it ;)
687 static void __init
fixup_nec_usb2(void)
689 struct device_node
*nec
;
691 for (nec
= NULL
; (nec
= of_find_node_by_name(nec
, "usb")) != NULL
;) {
692 struct pci_controller
*hose
;
697 prop
= of_get_property(nec
, "vendor-id", NULL
);
702 prop
= of_get_property(nec
, "device-id", NULL
);
707 prop
= of_get_property(nec
, "reg", NULL
);
710 devfn
= (prop
[0] >> 8) & 0xff;
711 bus
= (prop
[0] >> 16) & 0xff;
712 if (PCI_FUNC(devfn
) != 0)
714 hose
= pci_find_hose_for_OF_device(nec
);
717 early_read_config_dword(hose
, bus
, devfn
, 0xe4, &data
);
719 printk("Found NEC PD720100A USB2 chip with disabled"
720 " EHCI, fixing up...\n");
722 early_write_config_dword(hose
, bus
, devfn
, 0xe4, data
);
727 static void __init
setup_bandit(struct pci_controller
*hose
,
728 struct resource
*addr
)
730 hose
->ops
= ¯isc_pci_ops
;
731 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
732 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
736 static int __init
setup_uninorth(struct pci_controller
*hose
,
737 struct resource
*addr
)
739 pci_assign_all_buses
= 1;
741 hose
->ops
= ¯isc_pci_ops
;
742 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
743 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
744 /* We "know" that the bridge at f2000000 has the PCI slots. */
745 return addr
->start
== 0xf2000000;
747 #endif /* CONFIG_PPC32 */
750 static void __init
setup_u3_agp(struct pci_controller
* hose
)
752 /* On G5, we move AGP up to high bus number so we don't need
753 * to reassign bus numbers for HT. If we ever have P2P bridges
754 * on AGP, we'll have to move pci_assign_all_busses to the
755 * pci_controller structure so we enable it for AGP and not for
757 * We hard code the address because of the different size of
758 * the reg address cell, we shall fix that by killing struct
759 * reg_property and using some accessor functions instead
761 hose
->first_busno
= 0xf0;
762 hose
->last_busno
= 0xff;
764 hose
->ops
= ¯isc_pci_ops
;
765 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
766 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
770 static void __init
setup_u4_pcie(struct pci_controller
* hose
)
772 /* We currently only implement the "non-atomic" config space, to
773 * be optimised later.
775 hose
->ops
= &u4_pcie_pci_ops
;
776 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
777 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
779 /* The bus contains a bridge from root -> device, we need to
780 * make it visible on bus 0 so that we pick the right type
781 * of config cycles. If we didn't, we would have to force all
782 * config cycles to be type 1. So we override the "bus-range"
785 hose
->first_busno
= 0x00;
786 hose
->last_busno
= 0xff;
790 static void __init
setup_u3_ht(struct pci_controller
* hose
)
792 struct device_node
*np
= (struct device_node
*)hose
->arch_data
;
793 struct pci_controller
*other
= NULL
;
797 hose
->ops
= &u3_ht_pci_ops
;
799 /* We hard code the address because of the different size of
800 * the reg address cell, we shall fix that by killing struct
801 * reg_property and using some accessor functions instead
803 hose
->cfg_data
= ioremap(0xf2000000, 0x02000000);
806 * /ht node doesn't expose a "ranges" property, so we "remove"
807 * regions that have been allocated to AGP. So far, this version of
808 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
809 * to /ht. We need to fix that sooner or later by either parsing all
810 * child "ranges" properties or figuring out the U3 address space
811 * decoding logic and then read its configuration register (if any).
813 hose
->io_base_phys
= 0xf4000000;
814 hose
->pci_io_size
= 0x00400000;
815 hose
->io_resource
.name
= np
->full_name
;
816 hose
->io_resource
.start
= 0;
817 hose
->io_resource
.end
= 0x003fffff;
818 hose
->io_resource
.flags
= IORESOURCE_IO
;
819 hose
->pci_mem_offset
= 0;
820 hose
->first_busno
= 0;
821 hose
->last_busno
= 0xef;
822 hose
->mem_resources
[0].name
= np
->full_name
;
823 hose
->mem_resources
[0].start
= 0x80000000;
824 hose
->mem_resources
[0].end
= 0xefffffff;
825 hose
->mem_resources
[0].flags
= IORESOURCE_MEM
;
831 else if (u4_pcie
!= NULL
)
835 DBG("U3/4 has no AGP/PCIE, using full resource range\n");
839 /* Fixup bus range vs. PCIE */
841 hose
->last_busno
= u4_pcie
->first_busno
- 1;
843 /* We "remove" the AGP resources from the resources allocated to HT,
844 * that is we create "holes". However, that code does assumptions
845 * that so far happen to be true (cross fingers...), typically that
846 * resources in the AGP node are properly ordered
849 for (i
=0; i
<3; i
++) {
850 struct resource
*res
= &other
->mem_resources
[i
];
851 if (res
->flags
!= IORESOURCE_MEM
)
853 /* We don't care about "fine" resources */
854 if (res
->start
>= 0xf0000000)
856 /* Check if it's just a matter of "shrinking" us in one
859 if (hose
->mem_resources
[cur
].start
== res
->start
) {
860 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
861 cur
, hose
->mem_resources
[cur
].start
,
863 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
866 if (hose
->mem_resources
[cur
].end
== res
->end
) {
867 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
868 cur
, hose
->mem_resources
[cur
].end
,
870 hose
->mem_resources
[cur
].end
= res
->start
- 1;
873 /* No, it's not the case, we need a hole */
875 /* not enough resources for a hole, we drop part
878 printk(KERN_WARNING
"Running out of resources"
879 " for /ht host !\n");
880 hose
->mem_resources
[cur
].end
= res
->start
- 1;
884 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
885 cur
-1, res
->start
- 1, cur
, res
->end
+ 1);
886 hose
->mem_resources
[cur
].name
= np
->full_name
;
887 hose
->mem_resources
[cur
].flags
= IORESOURCE_MEM
;
888 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
889 hose
->mem_resources
[cur
].end
= hose
->mem_resources
[cur
-1].end
;
890 hose
->mem_resources
[cur
-1].end
= res
->start
- 1;
893 #endif /* CONFIG_PPC64 */
896 * We assume that if we have a G3 powermac, we have one bridge called
897 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
898 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
900 static int __init
add_bridge(struct device_node
*dev
)
903 struct pci_controller
*hose
;
904 struct resource rsrc
;
906 const int *bus_range
;
907 int primary
= 1, has_address
= 0;
909 DBG("Adding PCI host bridge %s\n", dev
->full_name
);
911 /* Fetch host bridge registers address */
912 has_address
= (of_address_to_resource(dev
, 0, &rsrc
) == 0);
914 /* Get bus range if any */
915 bus_range
= of_get_property(dev
, "bus-range", &len
);
916 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
917 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
918 " bus 0\n", dev
->full_name
);
921 /* XXX Different prototypes, to be merged */
923 hose
= pcibios_alloc_controller(dev
);
925 hose
= pcibios_alloc_controller();
929 hose
->arch_data
= dev
;
930 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
931 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
935 /* 64 bits only bridges */
937 if (of_device_is_compatible(dev
, "u3-agp")) {
939 disp_name
= "U3-AGP";
941 } else if (of_device_is_compatible(dev
, "u3-ht")) {
945 } else if (of_device_is_compatible(dev
, "u4-pcie")) {
947 disp_name
= "U4-PCIE";
950 printk(KERN_INFO
"Found %s PCI host bridge. Firmware bus number:"
951 " %d->%d\n", disp_name
, hose
->first_busno
, hose
->last_busno
);
952 #endif /* CONFIG_PPC64 */
954 /* 32 bits only bridges */
956 if (of_device_is_compatible(dev
, "uni-north")) {
957 primary
= setup_uninorth(hose
, &rsrc
);
958 disp_name
= "UniNorth";
959 } else if (strcmp(dev
->name
, "pci") == 0) {
960 /* XXX assume this is a mpc106 (grackle) */
962 disp_name
= "Grackle (MPC106)";
963 } else if (strcmp(dev
->name
, "bandit") == 0) {
964 setup_bandit(hose
, &rsrc
);
965 disp_name
= "Bandit";
966 } else if (strcmp(dev
->name
, "chaos") == 0) {
967 setup_chaos(hose
, &rsrc
);
971 printk(KERN_INFO
"Found %s PCI host bridge at 0x%016llx. "
972 "Firmware bus number: %d->%d\n",
973 disp_name
, (unsigned long long)rsrc
.start
, hose
->first_busno
,
975 #endif /* CONFIG_PPC32 */
977 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
978 hose
, hose
->cfg_addr
, hose
->cfg_data
);
980 /* Interpret the "ranges" property */
981 /* This also maps the I/O region and sets isa_io/mem_base */
982 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
984 /* Fixup "bus-range" OF property */
985 fixup_bus_range(dev
);
990 void __devinit
pmac_pci_irq_fixup(struct pci_dev
*dev
)
993 /* Fixup interrupt for the modem/ethernet combo controller.
994 * on machines with a second ohare chip.
995 * The number in the device tree (27) is bogus (correct for
996 * the ethernet-only board but not the combo ethernet/modem
997 * board). The real interrupt is 28 on the second controller
1000 if (has_second_ohare
&&
1001 dev
->vendor
== PCI_VENDOR_ID_DEC
&&
1002 dev
->device
== PCI_DEVICE_ID_DEC_TULIP_PLUS
) {
1003 dev
->irq
= irq_create_mapping(NULL
, 60);
1004 set_irq_type(dev
->irq
, IRQ_TYPE_LEVEL_LOW
);
1006 #endif /* CONFIG_PPC32 */
1010 static void __init
pmac_fixup_phb_resources(void)
1012 struct pci_controller
*hose
, *tmp
;
1014 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1015 printk(KERN_INFO
"PCI Host %d, io start: %lx; io end: %lx\n",
1016 hose
->global_number
,
1017 hose
->io_resource
.start
, hose
->io_resource
.end
);
1022 void __init
pmac_pci_init(void)
1024 struct device_node
*np
, *root
;
1025 struct device_node
*ht
= NULL
;
1027 root
= of_find_node_by_path("/");
1029 printk(KERN_CRIT
"pmac_pci_init: can't find root "
1030 "of device tree\n");
1033 for (np
= NULL
; (np
= of_get_next_child(root
, np
)) != NULL
;) {
1034 if (np
->name
== NULL
)
1036 if (strcmp(np
->name
, "bandit") == 0
1037 || strcmp(np
->name
, "chaos") == 0
1038 || strcmp(np
->name
, "pci") == 0) {
1039 if (add_bridge(np
) == 0)
1042 if (strcmp(np
->name
, "ht") == 0) {
1050 /* Probe HT last as it relies on the agp resources to be already
1053 if (ht
&& add_bridge(ht
) != 0)
1057 * We need to call pci_setup_phb_io for the HT bridge first
1058 * so it gets the I/O port numbers starting at 0, and we
1059 * need to call it for the AGP bridge after that so it gets
1060 * small positive I/O port numbers.
1063 pci_setup_phb_io(u3_ht
, 1);
1065 pci_setup_phb_io(u3_agp
, 0);
1067 pci_setup_phb_io(u4_pcie
, 0);
1070 * On ppc64, fixup the IO resources on our host bridges as
1071 * the common code does it only for children of the host bridges
1073 pmac_fixup_phb_resources();
1075 /* Setup the linkage between OF nodes and PHBs */
1076 pci_devs_phb_init();
1078 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1079 * assume there is no P2P bridge on the AGP bus, which should be a
1080 * safe assumptions for now. We should do something better in the
1084 struct device_node
*np
= u3_agp
->arch_data
;
1085 PCI_DN(np
)->busno
= 0xf0;
1086 for (np
= np
->child
; np
; np
= np
->sibling
)
1087 PCI_DN(np
)->busno
= 0xf0;
1089 /* pmac_check_ht_link(); */
1091 /* Tell pci.c to not use the common resource allocation mechanism */
1094 #else /* CONFIG_PPC64 */
1096 init_second_ohare();
1099 /* We are still having some issues with the Xserve G4, enabling
1100 * some offset between bus number and domains for now when we
1101 * assign all busses should help for now
1103 if (pci_assign_all_buses
)
1104 pcibios_assign_bus_offset
= 0x10;
1109 pmac_pci_enable_device_hook(struct pci_dev
*dev
, int initial
)
1111 struct device_node
* node
;
1115 node
= pci_device_to_OF_node(dev
);
1117 /* We don't want to enable USB controllers absent from the OF tree
1118 * (iBook second controller)
1120 if (dev
->vendor
== PCI_VENDOR_ID_APPLE
1121 && dev
->class == PCI_CLASS_SERIAL_USB_OHCI
1123 printk(KERN_INFO
"Apple USB OHCI %s disabled by firmware\n",
1131 uninorth_child
= node
->parent
&&
1132 of_device_is_compatible(node
->parent
, "uni-north");
1134 /* Firewire & GMAC were disabled after PCI probe, the driver is
1135 * claiming them, we must re-enable them now.
1137 if (uninorth_child
&& !strcmp(node
->name
, "firewire") &&
1138 (of_device_is_compatible(node
, "pci106b,18") ||
1139 of_device_is_compatible(node
, "pci106b,30") ||
1140 of_device_is_compatible(node
, "pci11c1,5811"))) {
1141 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, node
, 0, 1);
1142 pmac_call_feature(PMAC_FTR_1394_ENABLE
, node
, 0, 1);
1145 if (uninorth_child
&& !strcmp(node
->name
, "ethernet") &&
1146 of_device_is_compatible(node
, "gmac")) {
1147 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, node
, 0, 1);
1155 * Make sure PCI is correctly configured
1157 * We use old pci_bios versions of the function since, by
1158 * default, gmac is not powered up, and so will be absent
1159 * from the kernel initial PCI lookup.
1161 * Should be replaced by 2.4 new PCI mechanisms and really
1162 * register the device.
1164 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1165 cmd
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
1166 | PCI_COMMAND_INVALIDATE
;
1167 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1168 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 16);
1169 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
1170 L1_CACHE_BYTES
>> 2);
1176 /* We power down some devices after they have been probed. They'll
1177 * be powered back on later on
1179 void __init
pmac_pcibios_after_init(void)
1181 struct device_node
* nd
;
1183 #ifdef CONFIG_BLK_DEV_IDE
1184 struct pci_dev
*dev
= NULL
;
1186 /* OF fails to initialize IDE controllers on macs
1187 * (and maybe other machines)
1189 * Ideally, this should be moved to the IDE layer, but we need
1190 * to check specifically with Andre Hedrick how to do it cleanly
1191 * since the common IDE code seem to care about the fact that the
1192 * BIOS may have disabled a controller.
1196 for_each_pci_dev(dev
) {
1197 if ((dev
->class >> 16) != PCI_BASE_CLASS_STORAGE
)
1199 if (pci_enable_device(dev
))
1201 "pci: Failed to enable %s\n", pci_name(dev
));
1203 #endif /* CONFIG_BLK_DEV_IDE */
1205 for_each_node_by_name(nd
, "firewire") {
1206 if (nd
->parent
&& (of_device_is_compatible(nd
, "pci106b,18") ||
1207 of_device_is_compatible(nd
, "pci106b,30") ||
1208 of_device_is_compatible(nd
, "pci11c1,5811"))
1209 && of_device_is_compatible(nd
->parent
, "uni-north")) {
1210 pmac_call_feature(PMAC_FTR_1394_ENABLE
, nd
, 0, 0);
1211 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, nd
, 0, 0);
1215 for_each_node_by_name(nd
, "ethernet") {
1216 if (nd
->parent
&& of_device_is_compatible(nd
, "gmac")
1217 && of_device_is_compatible(nd
->parent
, "uni-north"))
1218 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, nd
, 0, 0);
1224 void pmac_pci_fixup_cardbus(struct pci_dev
* dev
)
1226 if (!machine_is(powermac
))
1229 * Fix the interrupt routing on the various cardbus bridges
1230 * used on powerbooks
1232 if (dev
->vendor
!= PCI_VENDOR_ID_TI
)
1234 if (dev
->device
== PCI_DEVICE_ID_TI_1130
||
1235 dev
->device
== PCI_DEVICE_ID_TI_1131
) {
1237 /* Enable PCI interrupt */
1238 if (pci_read_config_byte(dev
, 0x91, &val
) == 0)
1239 pci_write_config_byte(dev
, 0x91, val
| 0x30);
1240 /* Disable ISA interrupt mode */
1241 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1242 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1244 if (dev
->device
== PCI_DEVICE_ID_TI_1210
||
1245 dev
->device
== PCI_DEVICE_ID_TI_1211
||
1246 dev
->device
== PCI_DEVICE_ID_TI_1410
||
1247 dev
->device
== PCI_DEVICE_ID_TI_1510
) {
1249 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1250 signal out the MFUNC0 pin */
1251 if (pci_read_config_byte(dev
, 0x8c, &val
) == 0)
1252 pci_write_config_byte(dev
, 0x8c, (val
& ~0x0f) | 2);
1253 /* Disable ISA interrupt mode */
1254 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1255 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_ANY_ID
, pmac_pci_fixup_cardbus
);
1261 void pmac_pci_fixup_pciata(struct pci_dev
* dev
)
1266 * On PowerMacs, we try to switch any PCI ATA controller to
1269 if (!machine_is(powermac
))
1272 /* Some controllers don't have the class IDE */
1273 if (dev
->vendor
== PCI_VENDOR_ID_PROMISE
)
1274 switch(dev
->device
) {
1275 case PCI_DEVICE_ID_PROMISE_20246
:
1276 case PCI_DEVICE_ID_PROMISE_20262
:
1277 case PCI_DEVICE_ID_PROMISE_20263
:
1278 case PCI_DEVICE_ID_PROMISE_20265
:
1279 case PCI_DEVICE_ID_PROMISE_20267
:
1280 case PCI_DEVICE_ID_PROMISE_20268
:
1281 case PCI_DEVICE_ID_PROMISE_20269
:
1282 case PCI_DEVICE_ID_PROMISE_20270
:
1283 case PCI_DEVICE_ID_PROMISE_20271
:
1284 case PCI_DEVICE_ID_PROMISE_20275
:
1285 case PCI_DEVICE_ID_PROMISE_20276
:
1286 case PCI_DEVICE_ID_PROMISE_20277
:
1289 /* Others, check PCI class */
1290 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
1293 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1294 if ((progif
& 5) != 5) {
1295 printk(KERN_INFO
"Forcing PCI IDE into native mode: %s\n",
1297 (void) pci_write_config_byte(dev
, PCI_CLASS_PROG
, progif
|5);
1298 if (pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
) ||
1300 printk(KERN_ERR
"Rewrite of PROGIF failed !\n");
1303 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, pmac_pci_fixup_pciata
);
1307 * Disable second function on K2-SATA, it's broken
1308 * and disable IO BARs on first one
1310 static void fixup_k2_sata(struct pci_dev
* dev
)
1315 if (PCI_FUNC(dev
->devfn
) > 0) {
1316 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1317 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
1318 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1319 for (i
= 0; i
< 6; i
++) {
1320 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1321 dev
->resource
[i
].flags
= 0;
1322 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
,
1326 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1327 cmd
&= ~PCI_COMMAND_IO
;
1328 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1329 for (i
= 0; i
< 5; i
++) {
1330 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1331 dev
->resource
[i
].flags
= 0;
1332 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
,
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, 0x0240, fixup_k2_sata
);