release/src-rt-6.x/linux/linux-2.6/arch/mips/sgi-ip22/ip22-eisa.c

   1 /*
   2  * Basic EISA bus support for the SGI Indigo-2.
   3  *
   4  * (C) 2002 Pascal Dameme <netinet@freesurf.fr>
   5  *      and Marc Zyngier <mzyngier@freesurf.fr>
   6  *
   7  * This code is released under both the GPL version 2 and BSD
   8  * licenses.  Either license may be used.
   9  *
  10  * This code offers a very basic support for this EISA bus present in
  11  * the SGI Indigo-2. It currently only supports PIO (forget about DMA
  12  * for the time being). This is enough for a low-end ethernet card,
  13  * but forget about your favorite SCSI card...
  14  *
  15  * TODO :
  16  * - Fix bugs...
  17  * - Add ISA support
  18  * - Add DMA (yeah, right...).
  19  * - Fix more bugs.
  20  */
  21
  22 #include <linux/eisa.h>
  23 #include <linux/types.h>
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <linux/kernel_stat.h>
  27 #include <linux/signal.h>
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33 #include <asm/mipsregs.h>
  34 #include <asm/addrspace.h>
  35 #include <asm/processor.h>
  36 #include <asm/sgi/ioc.h>
  37 #include <asm/sgi/mc.h>
  38 #include <asm/sgi/ip22.h>
  39
  40 /* I2 has four EISA slots. */
  41 #define IP22_EISA_MAX_SLOTS       4
  42 #define EISA_MAX_IRQ             16
  43
  44 #define EIU_MODE_REG     0x0001ffc0
  45 #define EIU_STAT_REG     0x0001ffc4
  46 #define EIU_PREMPT_REG   0x0001ffc8
  47 #define EIU_QUIET_REG    0x0001ffcc
  48 #define EIU_INTRPT_ACK   0x00010004
  49
  50 static char __init *decode_eisa_sig(unsigned long addr)
  51 {
  52         static char sig_str[EISA_SIG_LEN];
  53         u8 sig[4];
  54         u16 rev;
  55         int i;
  56
  57         for (i = 0; i < 4; i++) {
  58                 sig[i] = inb (addr + i);
  59
  60                 if (!i && (sig[0] & 0x80))
  61                         return NULL;
  62         }
  63
  64         sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
  65         sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
  66         sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
  67         rev = (sig[2] << 8) | sig[3];
  68         sprintf(sig_str + 3, "%04X", rev);
  69
  70         return sig_str;
  71 }
  72
  73 static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
  74 {
  75         u8 eisa_irq;
  76         u8 dma1, dma2;
  77
  78         eisa_irq = inb(EIU_INTRPT_ACK);
  79         dma1 = inb(EISA_DMA1_STATUS);
  80         dma2 = inb(EISA_DMA2_STATUS);
  81
  82         if (eisa_irq < EISA_MAX_IRQ) {
  83                 do_IRQ(eisa_irq);
  84                 return IRQ_HANDLED;
  85         }
  86
  87         /* Oops, Bad Stuff Happened... */
  88         printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
  89
  90         outb(0x20, EISA_INT2_CTRL);
  91         outb(0x20, EISA_INT1_CTRL);
  92
  93         return IRQ_NONE;
  94 }
  95
  96 static void enable_eisa1_irq(unsigned int irq)
  97 {
  98         u8 mask;
  99
 100         mask = inb(EISA_INT1_MASK);
 101         mask &= ~((u8) (1 << irq));
 102         outb(mask, EISA_INT1_MASK);
 103 }
 104
 105 static unsigned int startup_eisa1_irq(unsigned int irq)
 106 {
 107         u8 edge;
 108
 109         /* Only use edge interrupts for EISA */
 110
 111         edge = inb(EISA_INT1_EDGE_LEVEL);
 112         edge &= ~((u8) (1 << irq));
 113         outb(edge, EISA_INT1_EDGE_LEVEL);
 114
 115         enable_eisa1_irq(irq);
 116         return 0;
 117 }
 118
 119 static void disable_eisa1_irq(unsigned int irq)
 120 {
 121         u8 mask;
 122
 123         mask = inb(EISA_INT1_MASK);
 124         mask |= ((u8) (1 << irq));
 125         outb(mask, EISA_INT1_MASK);
 126 }
 127
 128 static void mask_and_ack_eisa1_irq(unsigned int irq)
 129 {
 130         disable_eisa1_irq(irq);
 131
 132         outb(0x20, EISA_INT1_CTRL);
 133 }
 134
 135 static void end_eisa1_irq(unsigned int irq)
 136 {
 137         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 138                 enable_eisa1_irq(irq);
 139 }
 140
 141 static struct irq_chip ip22_eisa1_irq_type = {
 142         .name           = "IP22 EISA",
 143         .startup        = startup_eisa1_irq,
 144         .ack            = mask_and_ack_eisa1_irq,
 145         .mask           = disable_eisa1_irq,
 146         .mask_ack       = mask_and_ack_eisa1_irq,
 147         .unmask         = enable_eisa1_irq,
 148         .end            = end_eisa1_irq,
 149 };
 150
 151 static void enable_eisa2_irq(unsigned int irq)
 152 {
 153         u8 mask;
 154
 155         mask = inb(EISA_INT2_MASK);
 156         mask &= ~((u8) (1 << (irq - 8)));
 157         outb(mask, EISA_INT2_MASK);
 158 }
 159
 160 static unsigned int startup_eisa2_irq(unsigned int irq)
 161 {
 162         u8 edge;
 163
 164         /* Only use edge interrupts for EISA */
 165
 166         edge = inb(EISA_INT2_EDGE_LEVEL);
 167         edge &= ~((u8) (1 << (irq - 8)));
 168         outb(edge, EISA_INT2_EDGE_LEVEL);
 169
 170         enable_eisa2_irq(irq);
 171         return 0;
 172 }
 173
 174 static void disable_eisa2_irq(unsigned int irq)
 175 {
 176         u8 mask;
 177
 178         mask = inb(EISA_INT2_MASK);
 179         mask |= ((u8) (1 << (irq - 8)));
 180         outb(mask, EISA_INT2_MASK);
 181 }
 182
 183 static void mask_and_ack_eisa2_irq(unsigned int irq)
 184 {
 185         disable_eisa2_irq(irq);
 186
 187         outb(0x20, EISA_INT2_CTRL);
 188 }
 189
 190 static void end_eisa2_irq(unsigned int irq)
 191 {
 192         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 193                 enable_eisa2_irq(irq);
 194 }
 195
 196 static struct irq_chip ip22_eisa2_irq_type = {
 197         .name           = "IP22 EISA",
 198         .startup        = startup_eisa2_irq,
 199         .ack            = mask_and_ack_eisa2_irq,
 200         .mask           = disable_eisa2_irq,
 201         .mask_ack       = mask_and_ack_eisa2_irq,
 202         .unmask         = enable_eisa2_irq,
 203         .end            = end_eisa2_irq,
 204 };
 205
 206 static struct irqaction eisa_action = {
 207         .handler        = ip22_eisa_intr,
 208         .name           = "EISA",
 209 };
 210
 211 static struct irqaction cascade_action = {
 212         .handler        = no_action,
 213         .name           = "EISA cascade",
 214 };
 215
 216 int __init ip22_eisa_init(void)
 217 {
 218         int i, c;
 219         char *str;
 220
 221         if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
 222                 printk(KERN_INFO "EISA: bus not present.\n");
 223                 return 1;
 224         }
 225
 226         printk(KERN_INFO "EISA: Probing bus...\n");
 227         for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
 228                 if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
 229                         printk(KERN_INFO "EISA: slot %d : %s detected.\n",
 230                                i, str);
 231                         c++;
 232                 }
 233         }
 234         printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
 235 #ifdef CONFIG_ISA
 236         printk(KERN_INFO "ISA support compiled in.\n");
 237 #endif
 238
 239         /* Warning : BlackMagicAhead(tm).
 240            Please wave your favorite dead chicken over the busses */
 241
 242         /* First say hello to the EIU */
 243         outl(0x0000FFFF, EIU_PREMPT_REG);
 244         outl(1, EIU_QUIET_REG);
 245         outl(0x40f3c07F, EIU_MODE_REG);
 246
 247         /* Now be nice to the EISA chipset */
 248         outb(1, EISA_EXT_NMI_RESET_CTRL);
 249         udelay(50);     /* Wait long enough for the dust to settle */
 250         outb(0, EISA_EXT_NMI_RESET_CTRL);
 251         outb(0x11, EISA_INT1_CTRL);
 252         outb(0x11, EISA_INT2_CTRL);
 253         outb(0, EISA_INT1_MASK);
 254         outb(8, EISA_INT2_MASK);
 255         outb(4, EISA_INT1_MASK);
 256         outb(2, EISA_INT2_MASK);
 257         outb(1, EISA_INT1_MASK);
 258         outb(1, EISA_INT2_MASK);
 259         outb(0xfb, EISA_INT1_MASK);
 260         outb(0xff, EISA_INT2_MASK);
 261         outb(0, EISA_DMA2_WRITE_SINGLE);
 262
 263         for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
 264                 if (i < (SGINT_EISA + 8))
 265                         set_irq_chip(i, &ip22_eisa1_irq_type);
 266                 else
 267                         set_irq_chip(i, &ip22_eisa2_irq_type);
 268         }
 269
 270         /* Cannot use request_irq because of kmalloc not being ready at such
 271          * an early stage. Yes, I've been bitten... */
 272         setup_irq(SGI_EISA_IRQ, &eisa_action);
 273         setup_irq(SGINT_EISA + 2, &cascade_action);
 274
 275         EISA_bus = 1;
 276         return 0;
 277 }