2 * Cobalt Qube/Raq PCI support
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
18 #include <asm/gt64120.h>
22 static void qube_raq_galileo_early_fixup(struct pci_dev
*dev
)
24 if (dev
->devfn
== PCI_DEVFN(0, 0) &&
25 (dev
->class >> 8) == PCI_CLASS_MEMORY_OTHER
) {
27 dev
->class = (PCI_CLASS_BRIDGE_HOST
<< 8) | (dev
->class & 0xff);
29 printk(KERN_INFO
"Galileo: fixed bridge class\n");
33 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL
, PCI_DEVICE_ID_MARVELL_GT64111
,
34 qube_raq_galileo_early_fixup
);
36 static void qube_raq_via_bmIDE_fixup(struct pci_dev
*dev
)
38 unsigned short cfgword
;
41 /* Enable Bus Mastering and fast back to back. */
42 pci_read_config_word(dev
, PCI_COMMAND
, &cfgword
);
43 cfgword
|= (PCI_COMMAND_FAST_BACK
| PCI_COMMAND_MASTER
);
44 pci_write_config_word(dev
, PCI_COMMAND
, cfgword
);
46 /* Enable both ide interfaces. ROM only enables primary one. */
47 pci_write_config_byte(dev
, 0x40, 0xb);
49 /* Set latency timer to reasonable value. */
50 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, <
);
52 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
53 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, 8);
56 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_1
,
57 qube_raq_via_bmIDE_fixup
);
59 static void qube_raq_galileo_fixup(struct pci_dev
*dev
)
61 unsigned short galileo_id
;
63 if (dev
->devfn
!= PCI_DEVFN(0, 0))
66 /* Fix PCI latency-timer and cache-line-size values in Galileo
69 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
70 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, 8);
73 * The code described by the comment below has been removed
74 * as it causes bus mastering by the Ethernet controllers
75 * to break under any kind of network load. We always set
76 * the retry timeouts to their maximum.
78 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
80 * On all machines prior to Q2, we had the STOP line disconnected
81 * from Galileo to VIA on PCI. The new Galileo does not function
82 * correctly unless we have it connected.
84 * Therefore we must set the disconnect/retry cycle values to
85 * something sensible when using the new Galileo.
87 pci_read_config_word(dev
, PCI_REVISION_ID
, &galileo_id
);
88 galileo_id
&= 0xff; /* mask off class info */
90 printk(KERN_INFO
"Galileo: revision %u\n", galileo_id
);
93 if (galileo_id
>= 0x10) {
94 /* New Galileo, assumes PCI stop line to VIA is connected. */
95 GT_WRITE(GT_PCI0_TOR_OFS
, 0x4020);
96 } else if (galileo_id
== 0x1 || galileo_id
== 0x2)
100 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
101 timeo
= GT_READ(GT_PCI0_TOR_OFS
);
102 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
103 GT_WRITE(GT_PCI0_TOR_OFS
,
104 (0xff << 16) | /* retry count */
105 (0xff << 8) | /* timeout 1 */
106 0xff); /* timeout 0 */
108 /* enable PCI retry exceeded interrupt */
109 GT_WRITE(GT_INTRMASK_OFS
, GT_INTR_RETRYCTR0_MSK
| GT_READ(GT_INTRMASK_OFS
));
113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL
, PCI_DEVICE_ID_MARVELL_GT64111
,
114 qube_raq_galileo_fixup
);
118 static void qube_raq_via_board_id_fixup(struct pci_dev
*dev
)
123 retval
= pci_read_config_byte(dev
, VIA_COBALT_BRD_ID_REG
, &id
);
125 panic("Cannot read board ID");
129 cobalt_board_id
= VIA_COBALT_BRD_REG_to_ID(id
);
131 printk(KERN_INFO
"Cobalt board ID: %d\n", cobalt_board_id
);
134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
,
135 qube_raq_via_board_id_fixup
);
137 static char irq_tab_qube1
[] __initdata
= {
138 [COBALT_PCICONF_CPU
] = 0,
139 [COBALT_PCICONF_ETH0
] = COBALT_QUBE1_ETH0_IRQ
,
140 [COBALT_PCICONF_RAQSCSI
] = COBALT_SCSI_IRQ
,
141 [COBALT_PCICONF_VIA
] = 0,
142 [COBALT_PCICONF_PCISLOT
] = COBALT_QUBE_SLOT_IRQ
,
143 [COBALT_PCICONF_ETH1
] = 0
146 static char irq_tab_cobalt
[] __initdata
= {
147 [COBALT_PCICONF_CPU
] = 0,
148 [COBALT_PCICONF_ETH0
] = COBALT_ETH0_IRQ
,
149 [COBALT_PCICONF_RAQSCSI
] = COBALT_SCSI_IRQ
,
150 [COBALT_PCICONF_VIA
] = 0,
151 [COBALT_PCICONF_PCISLOT
] = COBALT_QUBE_SLOT_IRQ
,
152 [COBALT_PCICONF_ETH1
] = COBALT_ETH1_IRQ
155 static char irq_tab_raq2
[] __initdata
= {
156 [COBALT_PCICONF_CPU
] = 0,
157 [COBALT_PCICONF_ETH0
] = COBALT_ETH0_IRQ
,
158 [COBALT_PCICONF_RAQSCSI
] = COBALT_RAQ_SCSI_IRQ
,
159 [COBALT_PCICONF_VIA
] = 0,
160 [COBALT_PCICONF_PCISLOT
] = COBALT_QUBE_SLOT_IRQ
,
161 [COBALT_PCICONF_ETH1
] = COBALT_ETH1_IRQ
164 int __init
pcibios_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
166 if (cobalt_board_id
< COBALT_BRD_ID_QUBE2
)
167 return irq_tab_qube1
[slot
];
169 if (cobalt_board_id
== COBALT_BRD_ID_RAQ2
)
170 return irq_tab_raq2
[slot
];
172 return irq_tab_cobalt
[slot
];
175 /* Do platform specific device initialization at pci_enable_device() time */
176 int pcibios_plat_dev_init(struct pci_dev
*dev
)