2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 * This file contains exception handler for address error exception with the
12 * special capability to execute faulting instructions in software. The
13 * handler does not try to handle the case when the program counter points
14 * to an address not aligned to a word boundary.
16 * Putting data to unaligned addresses is a bad practice even on Intel where
17 * only the performance is affected. Much worse is that such code is non-
18 * portable. Due to several programs that die on MIPS due to alignment
19 * problems I decided to implement this handler anyway though I originally
20 * didn't intend to do this at all for user code.
22 * For now I enable fixing of address errors by default to make life easier.
23 * I however intend to disable this somewhen in the future when the alignment
24 * problems with user programs have been fixed. For programmers this is the
27 * Fixing address errors is a per process option. The option is inherited
28 * across fork(2) and execve(2) calls. If you really want to use the
29 * option in your user programs - I discourage the use of the software
30 * emulation strongly - use the following code in your userland stuff:
32 * #include <sys/sysmips.h>
35 * sysmips(MIPS_FIXADE, x);
38 * The argument x is 0 for disabling software emulation, enabled otherwise.
40 * Below a little program to play around with this feature.
43 * #include <sys/sysmips.h>
46 * unsigned char bar[8];
49 * main(int argc, char *argv[])
51 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
52 * unsigned int *p = (unsigned int *) (x.bar + 3);
56 * sysmips(MIPS_FIXADE, atoi(argv[1]));
58 * printf("*p = %08lx\n", *p);
62 * for(i = 0; i <= 7; i++)
63 * printf("%02x ", x.bar[i]);
67 * Coprocessor loads are not supported; I think this case is unimportant
70 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
71 * exception for the R6000.
72 * A store crossing a page boundary might be executed only partially.
73 * Undo the partial store in this case.
76 #include <linux/module.h>
77 #include <linux/signal.h>
78 #include <linux/smp.h>
79 #include <linux/sched.h>
81 #include <asm/branch.h>
82 #include <asm/byteorder.h>
84 #include <asm/uaccess.h>
85 #include <asm/system.h>
87 #define STR(x) __STR(x)
91 unsigned long unaligned_instructions
;
94 static inline int emulate_load_store_insn(struct pt_regs
*regs
,
95 void __user
*addr
, unsigned int __user
*pc
,
96 unsigned long **regptr
, unsigned long *newvalue
)
98 union mips_instruction insn
;
105 * This load never faults.
107 __get_user(insn
.word
, pc
);
109 switch (insn
.i_format
.opcode
) {
111 * These are instructions that a compiler doesn't generate. We
112 * can assume therefore that the code is MIPS-aware and
113 * really buggy. Emulating these instructions would break the
122 * For these instructions the only way to create an address
123 * error is an attempted access to kernel/supervisor address
140 * The remaining opcodes are the ones that are really of interest.
143 if (!access_ok(VERIFY_READ
, addr
, 2))
146 __asm__
__volatile__ (".set\tnoat\n"
148 "1:\tlb\t%0, 0(%2)\n"
149 "2:\tlbu\t$1, 1(%2)\n\t"
151 #ifdef __LITTLE_ENDIAN
152 "1:\tlb\t%0, 1(%2)\n"
153 "2:\tlbu\t$1, 0(%2)\n\t"
159 ".section\t.fixup,\"ax\"\n\t"
163 ".section\t__ex_table,\"a\"\n\t"
164 STR(PTR
)"\t1b, 4b\n\t"
165 STR(PTR
)"\t2b, 4b\n\t"
167 : "=&r" (value
), "=r" (res
)
168 : "r" (addr
), "i" (-EFAULT
));
172 *regptr
= ®s
->regs
[insn
.i_format
.rt
];
176 if (!access_ok(VERIFY_READ
, addr
, 4))
179 __asm__
__volatile__ (
181 "1:\tlwl\t%0, (%2)\n"
182 "2:\tlwr\t%0, 3(%2)\n\t"
184 #ifdef __LITTLE_ENDIAN
185 "1:\tlwl\t%0, 3(%2)\n"
186 "2:\tlwr\t%0, (%2)\n\t"
189 "3:\t.section\t.fixup,\"ax\"\n\t"
193 ".section\t__ex_table,\"a\"\n\t"
194 STR(PTR
)"\t1b, 4b\n\t"
195 STR(PTR
)"\t2b, 4b\n\t"
197 : "=&r" (value
), "=r" (res
)
198 : "r" (addr
), "i" (-EFAULT
));
202 *regptr
= ®s
->regs
[insn
.i_format
.rt
];
206 if (!access_ok(VERIFY_READ
, addr
, 2))
209 __asm__
__volatile__ (
212 "1:\tlbu\t%0, 0(%2)\n"
213 "2:\tlbu\t$1, 1(%2)\n\t"
215 #ifdef __LITTLE_ENDIAN
216 "1:\tlbu\t%0, 1(%2)\n"
217 "2:\tlbu\t$1, 0(%2)\n\t"
223 ".section\t.fixup,\"ax\"\n\t"
227 ".section\t__ex_table,\"a\"\n\t"
228 STR(PTR
)"\t1b, 4b\n\t"
229 STR(PTR
)"\t2b, 4b\n\t"
231 : "=&r" (value
), "=r" (res
)
232 : "r" (addr
), "i" (-EFAULT
));
236 *regptr
= ®s
->regs
[insn
.i_format
.rt
];
242 * A 32-bit kernel might be running on a 64-bit processor. But
243 * if we're on a 32-bit processor and an i-cache incoherency
244 * or race makes us see a 64-bit instruction here the sdl/sdr
245 * would blow up, so for now we don't handle unaligned 64-bit
246 * instructions on 32-bit kernels.
248 if (!access_ok(VERIFY_READ
, addr
, 4))
251 __asm__
__volatile__ (
253 "1:\tlwl\t%0, (%2)\n"
254 "2:\tlwr\t%0, 3(%2)\n\t"
256 #ifdef __LITTLE_ENDIAN
257 "1:\tlwl\t%0, 3(%2)\n"
258 "2:\tlwr\t%0, (%2)\n\t"
260 "dsll\t%0, %0, 32\n\t"
261 "dsrl\t%0, %0, 32\n\t"
263 "3:\t.section\t.fixup,\"ax\"\n\t"
267 ".section\t__ex_table,\"a\"\n\t"
268 STR(PTR
)"\t1b, 4b\n\t"
269 STR(PTR
)"\t2b, 4b\n\t"
271 : "=&r" (value
), "=r" (res
)
272 : "r" (addr
), "i" (-EFAULT
));
276 *regptr
= ®s
->regs
[insn
.i_format
.rt
];
278 #endif /* CONFIG_64BIT */
280 /* Cannot handle 64-bit instructions in 32-bit kernel */
286 * A 32-bit kernel might be running on a 64-bit processor. But
287 * if we're on a 32-bit processor and an i-cache incoherency
288 * or race makes us see a 64-bit instruction here the sdl/sdr
289 * would blow up, so for now we don't handle unaligned 64-bit
290 * instructions on 32-bit kernels.
292 if (!access_ok(VERIFY_READ
, addr
, 8))
295 __asm__
__volatile__ (
297 "1:\tldl\t%0, (%2)\n"
298 "2:\tldr\t%0, 7(%2)\n\t"
300 #ifdef __LITTLE_ENDIAN
301 "1:\tldl\t%0, 7(%2)\n"
302 "2:\tldr\t%0, (%2)\n\t"
305 "3:\t.section\t.fixup,\"ax\"\n\t"
309 ".section\t__ex_table,\"a\"\n\t"
310 STR(PTR
)"\t1b, 4b\n\t"
311 STR(PTR
)"\t2b, 4b\n\t"
313 : "=&r" (value
), "=r" (res
)
314 : "r" (addr
), "i" (-EFAULT
));
318 *regptr
= ®s
->regs
[insn
.i_format
.rt
];
320 #endif /* CONFIG_64BIT */
322 /* Cannot handle 64-bit instructions in 32-bit kernel */
326 if (!access_ok(VERIFY_WRITE
, addr
, 2))
329 value
= regs
->regs
[insn
.i_format
.rt
];
330 __asm__
__volatile__ (
333 "1:\tsb\t%1, 1(%2)\n\t"
335 "2:\tsb\t$1, 0(%2)\n\t"
338 #ifdef __LITTLE_ENDIAN
340 "1:\tsb\t%1, 0(%2)\n\t"
342 "2:\tsb\t$1, 1(%2)\n\t"
347 ".section\t.fixup,\"ax\"\n\t"
351 ".section\t__ex_table,\"a\"\n\t"
352 STR(PTR
)"\t1b, 4b\n\t"
353 STR(PTR
)"\t2b, 4b\n\t"
356 : "r" (value
), "r" (addr
), "i" (-EFAULT
));
362 if (!access_ok(VERIFY_WRITE
, addr
, 4))
365 value
= regs
->regs
[insn
.i_format
.rt
];
366 __asm__
__volatile__ (
369 "2:\tswr\t%1, 3(%2)\n\t"
371 #ifdef __LITTLE_ENDIAN
372 "1:\tswl\t%1, 3(%2)\n"
373 "2:\tswr\t%1, (%2)\n\t"
377 ".section\t.fixup,\"ax\"\n\t"
381 ".section\t__ex_table,\"a\"\n\t"
382 STR(PTR
)"\t1b, 4b\n\t"
383 STR(PTR
)"\t2b, 4b\n\t"
386 : "r" (value
), "r" (addr
), "i" (-EFAULT
));
394 * A 32-bit kernel might be running on a 64-bit processor. But
395 * if we're on a 32-bit processor and an i-cache incoherency
396 * or race makes us see a 64-bit instruction here the sdl/sdr
397 * would blow up, so for now we don't handle unaligned 64-bit
398 * instructions on 32-bit kernels.
400 if (!access_ok(VERIFY_WRITE
, addr
, 8))
403 value
= regs
->regs
[insn
.i_format
.rt
];
404 __asm__
__volatile__ (
407 "2:\tsdr\t%1, 7(%2)\n\t"
409 #ifdef __LITTLE_ENDIAN
410 "1:\tsdl\t%1, 7(%2)\n"
411 "2:\tsdr\t%1, (%2)\n\t"
415 ".section\t.fixup,\"ax\"\n\t"
419 ".section\t__ex_table,\"a\"\n\t"
420 STR(PTR
)"\t1b, 4b\n\t"
421 STR(PTR
)"\t2b, 4b\n\t"
424 : "r" (value
), "r" (addr
), "i" (-EFAULT
));
428 #endif /* CONFIG_64BIT */
430 /* Cannot handle 64-bit instructions in 32-bit kernel */
438 * I herewith declare: this does not happen. So send SIGBUS.
447 * These are the coprocessor 2 load/stores. The current
448 * implementations don't use cp2 and cp2 should always be
449 * disabled in c0_status. So send SIGILL.
450 * (No longer true: The Sony Praystation uses cp2 for
451 * 3D matrix operations. Dunno if that thingy has a MMU ...)
455 * Pheeee... We encountered an yet unknown instruction or
456 * cache coherence problem. Die sucker, die ...
461 #ifdef CONFIG_PROC_FS
462 unaligned_instructions
++;
468 /* Did we have an exception handler installed? */
469 if (fixup_exception(regs
))
472 die_if_kernel ("Unhandled kernel unaligned access", regs
);
473 force_sig(SIGSEGV
, current
);
478 die_if_kernel("Unhandled kernel unaligned access", regs
);
479 force_sig(SIGBUS
, current
);
484 die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs
);
485 force_sig(SIGILL
, current
);
490 asmlinkage
void do_ade(struct pt_regs
*regs
)
492 unsigned long *regptr
, newval
;
493 unsigned int __user
*pc
;
497 * Did we catch a fault trying to load an instruction?
498 * Or are we running in MIPS16 mode?
500 if ((regs
->cp0_badvaddr
== regs
->cp0_epc
) || (regs
->cp0_epc
& 0x1))
503 pc
= (unsigned int __user
*) exception_epc(regs
);
504 if (user_mode(regs
) && (current
->thread
.mflags
& MF_FIXADE
) == 0)
508 * Do branch emulation only if we didn't forward the exception.
509 * This is all so but ugly ...
512 if (!user_mode(regs
))
514 if (!emulate_load_store_insn(regs
, (void __user
*)regs
->cp0_badvaddr
, pc
,
516 compute_return_epc(regs
);
518 * Now that branch is evaluated, update the dest
519 * register if necessary
529 die_if_kernel("Kernel unaligned instruction access", regs
);
530 force_sig(SIGBUS
, current
);
533 * XXX On return from the signal handler we should advance the epc