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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / blackfin / kernel / setup.c
blob83060f98d15d265cfcfbc50f657743f7e99255c4
1 /*
2 * File: arch/blackfin/kernel/setup.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30 #include <linux/delay.h>
31 #include <linux/console.h>
32 #include <linux/bootmem.h>
33 #include <linux/seq_file.h>
34 #include <linux/cpu.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37
38 #include <linux/ext2_fs.h>
39 #include <linux/cramfs_fs.h>
40 #include <linux/romfs_fs.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/blackfin.h>
44 #include <asm/cplbinit.h>
45
46 u16 _bfin_swrst;
47
48 unsigned long memory_start, memory_end, physical_mem_end;
49 unsigned long reserved_mem_dcache_on;
50 unsigned long reserved_mem_icache_on;
51 EXPORT_SYMBOL(memory_start);
52 EXPORT_SYMBOL(memory_end);
53 EXPORT_SYMBOL(physical_mem_end);
54 EXPORT_SYMBOL(_ramend);
55
56 #ifdef CONFIG_MTD_UCLINUX
57 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
58 unsigned long _ebss;
59 EXPORT_SYMBOL(memory_mtd_end);
60 EXPORT_SYMBOL(memory_mtd_start);
61 EXPORT_SYMBOL(mtd_size);
62 #endif
63
64 char __initdata command_line[COMMAND_LINE_SIZE];
65
66 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67 static void generate_cpl_tables(void);
68 #endif
69
70 void __init bf53x_cache_init(void)
71 {
72 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
73 generate_cpl_tables();
74 #endif
75
76 #ifdef CONFIG_BLKFIN_CACHE
77 bfin_icache_init();
78 printk(KERN_INFO "Instruction Cache Enabled\n");
79 #endif
80
81 #ifdef CONFIG_BLKFIN_DCACHE
82 bfin_dcache_init();
83 printk(KERN_INFO "Data Cache Enabled"
84 # if defined CONFIG_BLKFIN_WB
85 " (write-back)"
86 # elif defined CONFIG_BLKFIN_WT
87 " (write-through)"
88 # endif
89 "\n");
90 #endif
91 }
92
93 void __init bf53x_relocate_l1_mem(void)
94 {
95 unsigned long l1_code_length;
96 unsigned long l1_data_a_length;
97 unsigned long l1_data_b_length;
98
99 l1_code_length = _etext_l1 - _stext_l1;
100 if (l1_code_length > L1_CODE_LENGTH)
101 l1_code_length = L1_CODE_LENGTH;
102 /* cannot complain as printk is not available as yet.
103 * But we can continue booting and complain later!
104 */
105
106 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
107 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
108
109 l1_data_a_length = _ebss_l1 - _sdata_l1;
110 if (l1_data_a_length > L1_DATA_A_LENGTH)
111 l1_data_a_length = L1_DATA_A_LENGTH;
112
113 /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
114 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
115
116 l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
117 if (l1_data_b_length > L1_DATA_B_LENGTH)
118 l1_data_b_length = L1_DATA_B_LENGTH;
119
120 /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
121 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
122 l1_data_a_length, l1_data_b_length);
123
124 }
125
126 /*
127 * Initial parsing of the command line. Currently, we support:
128 * - Controlling the linux memory size: mem=xxx[KMG]
129 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
130 * $ -> reserved memory is dcacheable
131 * # -> reserved memory is icacheable
132 */
133 static __init void parse_cmdline_early(char *cmdline_p)
134 {
135 char c = ' ', *to = cmdline_p;
136 unsigned int memsize;
137 for (;;) {
138 if (c == ' ') {
139
140 if (!memcmp(to, "mem=", 4)) {
141 to += 4;
142 memsize = memparse(to, &to);
143 if (memsize)
144 _ramend = memsize;
145
146 } else if (!memcmp(to, "max_mem=", 8)) {
147 to += 8;
148 memsize = memparse(to, &to);
149 if (memsize) {
150 physical_mem_end = memsize;
151 if (*to != ' ') {
152 if (*to == '$'
153 || *(to + 1) == '$')
154 reserved_mem_dcache_on =
155 1;
156 if (*to == '#'
157 || *(to + 1) == '#')
158 reserved_mem_icache_on =
159 1;
160 }
161 }
162 }
163
164 }
165 c = *(to++);
166 if (!c)
167 break;
168 }
169 }
170
171 void __init setup_arch(char **cmdline_p)
172 {
173 int bootmap_size;
174 unsigned long l1_length, sclk, cclk;
175 #ifdef CONFIG_MTD_UCLINUX
176 unsigned long mtd_phys = 0;
177 #endif
178
179 #ifdef CONFIG_DUMMY_CONSOLE
180 conswitchp = &dummy_con;
181 #endif
182 cclk = get_cclk();
183 sclk = get_sclk();
184
185 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
186 if (cclk == sclk)
187 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
188 #endif
189
190 #if defined(ANOMALY_05000266)
191 bfin_read_IMDMA_D0_IRQ_STATUS();
192 bfin_read_IMDMA_D1_IRQ_STATUS();
193 #endif
194
195 #ifdef DEBUG_SERIAL_EARLY_INIT
196 bfin_console_init(); /* early console registration */
197 /* this give a chance to get printk() working before crash. */
198 #endif
199
200 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot
203 */
204 flash_probe();
205 #endif
206
207 #if defined(CONFIG_CMDLINE_BOOL)
208 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
209 command_line[sizeof(command_line) - 1] = 0;
210 #endif
211
212 /* Keep a copy of command line */
213 *cmdline_p = &command_line[0];
214 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
215 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
216
217 /* setup memory defaults from the user config */
218 physical_mem_end = 0;
219 _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
220
221 parse_cmdline_early(&command_line[0]);
222
223 if (physical_mem_end == 0)
224 physical_mem_end = _ramend;
225
226 /* by now the stack is part of the init task */
227 memory_end = _ramend - DMA_UNCACHED_REGION;
228
229 _ramstart = (unsigned long)__bss_stop;
230 memory_start = PAGE_ALIGN(_ramstart);
231
232 #if defined(CONFIG_MTD_UCLINUX)
233 /* generic memory mapped MTD driver */
234 memory_mtd_end = memory_end;
235
236 mtd_phys = _ramstart;
237 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
238
239 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
240 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
241 mtd_size =
242 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
243 # endif
244
245 # if defined(CONFIG_CRAMFS)
246 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
247 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
248 # endif
249
250 # if defined(CONFIG_ROMFS_FS)
251 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
252 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
253 mtd_size =
254 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
255 # if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
256 /* Due to a Hardware Anomaly we need to limit the size of usable
257 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
258 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
259 */
260 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
261 if (memory_end >= 56 * 1024 * 1024)
262 memory_end = 56 * 1024 * 1024;
263 # else
264 if (memory_end >= 60 * 1024 * 1024)
265 memory_end = 60 * 1024 * 1024;
266 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
267 # endif /* ANOMALY_05000263 */
268 # endif /* CONFIG_ROMFS_FS */
269
270 memory_end -= mtd_size;
271
272 if (mtd_size == 0) {
273 console_init();
274 panic("Don't boot kernel without rootfs attached.\n");
275 }
276
277 /* Relocate MTD image to the top of memory after the uncached memory area */
278 dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
279
280 memory_mtd_start = memory_end;
281 _ebss = memory_mtd_start; /* define _ebss for compatible */
282 #endif /* CONFIG_MTD_UCLINUX */
283
284 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
285 /* Due to a Hardware Anomaly we need to limit the size of usable
286 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
287 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
288 */
289 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
290 if (memory_end >= 56 * 1024 * 1024)
291 memory_end = 56 * 1024 * 1024;
292 #else
293 if (memory_end >= 60 * 1024 * 1024)
294 memory_end = 60 * 1024 * 1024;
295 #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
296 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
297 #endif /* ANOMALY_05000263 */
298
299 #if !defined(CONFIG_MTD_UCLINUX)
300 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
301 #endif
302 init_mm.start_code = (unsigned long)_stext;
303 init_mm.end_code = (unsigned long)_etext;
304 init_mm.end_data = (unsigned long)_edata;
305 init_mm.brk = (unsigned long)0;
306
307 init_leds();
308
309 printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
310 if (bfin_compiled_revid() == 0xffff)
311 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
312 else if (bfin_compiled_revid() == -1)
313 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
314 else
315 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
316 if (bfin_revid() != bfin_compiled_revid()) {
317 if (bfin_compiled_revid() == -1)
318 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
319 bfin_revid());
320 else if (bfin_compiled_revid() != 0xffff)
321 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
322 bfin_compiled_revid(), bfin_revid());
323 }
324 if (bfin_revid() < SUPPORTED_REVID)
325 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
326 CPU, bfin_revid());
327 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
328
329 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
330 cclk / 1000000, sclk / 1000000);
331
332 #if defined(ANOMALY_05000273)
333 if ((cclk >> 1) <= sclk)
334 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
335 #endif
336
337 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
338 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
339
340 printk(KERN_INFO "Memory map:\n"
341 KERN_INFO " text = 0x%p-0x%p\n"
342 KERN_INFO " rodata = 0x%p-0x%p\n"
343 KERN_INFO " data = 0x%p-0x%p\n"
344 KERN_INFO " stack = 0x%p-0x%p\n"
345 KERN_INFO " init = 0x%p-0x%p\n"
346 KERN_INFO " bss = 0x%p-0x%p\n"
347 KERN_INFO " available = 0x%p-0x%p\n"
348 #ifdef CONFIG_MTD_UCLINUX
349 KERN_INFO " rootfs = 0x%p-0x%p\n"
350 #endif
351 #if DMA_UNCACHED_REGION > 0
352 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
353 #endif
354 , _stext, _etext,
355 __start_rodata, __end_rodata,
356 _sdata, _edata,
357 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
358 __init_begin, __init_end,
359 __bss_start, __bss_stop,
360 (void*)_ramstart, (void*)memory_end
361 #ifdef CONFIG_MTD_UCLINUX
362 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
363 #endif
364 #if DMA_UNCACHED_REGION > 0
365 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
366 #endif
367 );
368
369 /*
370 * give all the memory to the bootmap allocator, tell it to put the
371 * boot mem_map at the start of memory
372 */
373 bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
374 PAGE_OFFSET >> PAGE_SHIFT,
375 memory_end >> PAGE_SHIFT);
376 /*
377 * free the usable memory, we have to make sure we do not free
378 * the bootmem bitmap so we then reserve it after freeing it :-)
379 */
380 free_bootmem(memory_start, memory_end - memory_start);
381
382 reserve_bootmem(memory_start, bootmap_size);
383 /*
384 * get kmalloc into gear
385 */
386 paging_init();
387
388 /* check the size of the l1 area */
389 l1_length = _etext_l1 - _stext_l1;
390 if (l1_length > L1_CODE_LENGTH)
391 panic("L1 memory overflow\n");
392
393 l1_length = _ebss_l1 - _sdata_l1;
394 if (l1_length > L1_DATA_A_LENGTH)
395 panic("L1 memory overflow\n");
396
397 #ifdef BF561_FAMILY
398 _bfin_swrst = bfin_read_SICA_SWRST();
399 #else
400 _bfin_swrst = bfin_read_SWRST();
401 #endif
402
403 bf53x_cache_init();
404
405 printk(KERN_INFO "Hardware Trace Enabled\n");
406 bfin_write_TBUFCTL(0x03);
407 }
408
409 static int __init topology_init(void)
410 {
411 #if defined (CONFIG_BF561)
412 static struct cpu cpu[2];
413 register_cpu(&cpu[0], 0);
414 register_cpu(&cpu[1], 1);
415 return 0;
416 #else
417 static struct cpu cpu[1];
418 return register_cpu(cpu, 0);
419 #endif
420 }
421
422 subsys_initcall(topology_init);
423
424 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
425 static u16 __init lock_kernel_check(u32 start, u32 end)
426 {
427 if ((start <= (u32) _stext && end >= (u32) _end)
428 || (start >= (u32) _stext && end <= (u32) _end))
429 return IN_KERNEL;
430 return 0;
431 }
432
433 static unsigned short __init
434 fill_cplbtab(struct cplb_tab *table,
435 unsigned long start, unsigned long end,
436 unsigned long block_size, unsigned long cplb_data)
437 {
438 int i;
439
440 switch (block_size) {
441 case SIZE_4M:
442 i = 3;
443 break;
444 case SIZE_1M:
445 i = 2;
446 break;
447 case SIZE_4K:
448 i = 1;
449 break;
450 case SIZE_1K:
451 default:
452 i = 0;
453 break;
454 }
455
456 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
457
458 while ((start < end) && (table->pos < table->size)) {
459
460 table->tab[table->pos++] = start;
461
462 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
463 table->tab[table->pos++] =
464 cplb_data | CPLB_LOCK | CPLB_DIRTY;
465 else
466 table->tab[table->pos++] = cplb_data;
467
468 start += block_size;
469 }
470 return 0;
471 }
472
473 static unsigned short __init
474 close_cplbtab(struct cplb_tab *table)
475 {
476
477 while (table->pos < table->size) {
478
479 table->tab[table->pos++] = 0;
480 table->tab[table->pos++] = 0; /* !CPLB_VALID */
481 }
482 return 0;
483 }
484
485 /* helper function */
486 static void __fill_code_cplbtab(struct cplb_tab *t, int i,
487 u32 a_start, u32 a_end)
488 {
489 if (cplb_data[i].psize) {
490 fill_cplbtab(t,
491 cplb_data[i].start,
492 cplb_data[i].end,
493 cplb_data[i].psize,
494 cplb_data[i].i_conf);
495 } else {
496 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
497 if (i == SDRAM_KERN) {
498 fill_cplbtab(t,
499 cplb_data[i].start,
500 cplb_data[i].end,
501 SIZE_4M,
502 cplb_data[i].i_conf);
503 } else {
504 #endif
505 fill_cplbtab(t,
506 cplb_data[i].start,
507 a_start,
508 SIZE_1M,
509 cplb_data[i].i_conf);
510 fill_cplbtab(t,
511 a_start,
512 a_end,
513 SIZE_4M,
514 cplb_data[i].i_conf);
515 fill_cplbtab(t, a_end,
516 cplb_data[i].end,
517 SIZE_1M,
518 cplb_data[i].i_conf);
519 }
520 }
521 }
522
523 static void __fill_data_cplbtab(struct cplb_tab *t, int i,
524 u32 a_start, u32 a_end)
525 {
526 if (cplb_data[i].psize) {
527 fill_cplbtab(t,
528 cplb_data[i].start,
529 cplb_data[i].end,
530 cplb_data[i].psize,
531 cplb_data[i].d_conf);
532 } else {
533 fill_cplbtab(t,
534 cplb_data[i].start,
535 a_start, SIZE_1M,
536 cplb_data[i].d_conf);
537 fill_cplbtab(t, a_start,
538 a_end, SIZE_4M,
539 cplb_data[i].d_conf);
540 fill_cplbtab(t, a_end,
541 cplb_data[i].end,
542 SIZE_1M,
543 cplb_data[i].d_conf);
544 }
545 }
546 static void __init generate_cpl_tables(void)
547 {
548
549 u16 i, j, process;
550 u32 a_start, a_end, as, ae, as_1m;
551
552 struct cplb_tab *t_i = NULL;
553 struct cplb_tab *t_d = NULL;
554 struct s_cplb cplb;
555
556 cplb.init_i.size = MAX_CPLBS;
557 cplb.init_d.size = MAX_CPLBS;
558 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
559 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
560
561 cplb.init_i.pos = 0;
562 cplb.init_d.pos = 0;
563 cplb.switch_i.pos = 0;
564 cplb.switch_d.pos = 0;
565
566 cplb.init_i.tab = icplb_table;
567 cplb.init_d.tab = dcplb_table;
568 cplb.switch_i.tab = ipdt_table;
569 cplb.switch_d.tab = dpdt_table;
570
571 cplb_data[SDRAM_KERN].end = memory_end;
572
573 #ifdef CONFIG_MTD_UCLINUX
574 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
575 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
576 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
577 # if defined(CONFIG_ROMFS_FS)
578 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
579
580 /*
581 * The ROMFS_FS size is often not multiple of 1MB.
582 * This can cause multiple CPLB sets covering the same memory area.
583 * This will then cause multiple CPLB hit exceptions.
584 * Workaround: We ensure a contiguous memory area by extending the kernel
585 * memory section over the mtd section.
586 * For ROMFS_FS memory must be covered with ICPLBs anyways.
587 * So there is no difference between kernel and mtd memory setup.
588 */
589
590 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
591 cplb_data[SDRAM_RAM_MTD].valid = 0;
592
593 # endif
594 #else
595 cplb_data[SDRAM_RAM_MTD].valid = 0;
596 #endif
597
598 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
599 cplb_data[SDRAM_DMAZ].end = _ramend;
600
601 cplb_data[RES_MEM].start = _ramend;
602 cplb_data[RES_MEM].end = physical_mem_end;
603
604 if (reserved_mem_dcache_on)
605 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
606 else
607 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
608
609 if (reserved_mem_icache_on)
610 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
611 else
612 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
613
614 for (i = ZERO_P; i <= L2_MEM; i++) {
615 if (!cplb_data[i].valid)
616 continue;
617
618 as_1m = cplb_data[i].start % SIZE_1M;
619
620 /*
621 * We need to make sure all sections are properly 1M aligned
622 * However between Kernel Memory and the Kernel mtd section,
623 * depending on the rootfs size, there can be overlapping
624 * memory areas.
625 */
626
627 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
628 #ifdef CONFIG_MTD_UCLINUX
629 if (i == SDRAM_RAM_MTD) {
630 if ((cplb_data[SDRAM_KERN].end + 1) >
631 cplb_data[SDRAM_RAM_MTD].start)
632 cplb_data[SDRAM_RAM_MTD].start =
633 (cplb_data[i].start &
634 (-2*SIZE_1M)) + SIZE_1M;
635 else
636 cplb_data[SDRAM_RAM_MTD].start =
637 (cplb_data[i].start &
638 (-2*SIZE_1M));
639 } else
640 #endif
641 printk(KERN_WARNING
642 "Unaligned Start of %s at 0x%X\n",
643 cplb_data[i].name, cplb_data[i].start);
644 }
645
646 as = cplb_data[i].start % SIZE_4M;
647 ae = cplb_data[i].end % SIZE_4M;
648
649 if (as)
650 a_start = cplb_data[i].start + (SIZE_4M - (as));
651 else
652 a_start = cplb_data[i].start;
653
654 a_end = cplb_data[i].end - ae;
655
656 for (j = INITIAL_T; j <= SWITCH_T; j++) {
657
658 switch (j) {
659 case INITIAL_T:
660 if (cplb_data[i].attr & INITIAL_T) {
661 t_i = &cplb.init_i;
662 t_d = &cplb.init_d;
663 process = 1;
664 } else
665 process = 0;
666 break;
667 case SWITCH_T:
668 if (cplb_data[i].attr & SWITCH_T) {
669 t_i = &cplb.switch_i;
670 t_d = &cplb.switch_d;
671 process = 1;
672 } else
673 process = 0;
674 break;
675 default:
676 process = 0;
677 break;
678 }
679
680 if (!process)
681 continue;
682 if (cplb_data[i].attr & I_CPLB)
683 __fill_code_cplbtab(t_i, i, a_start, a_end);
684
685 if (cplb_data[i].attr & D_CPLB)
686 __fill_data_cplbtab(t_d, i, a_start, a_end);
687 }
688 }
689
690 /* close tables */
691
692 close_cplbtab(&cplb.init_i);
693 close_cplbtab(&cplb.init_d);
694
695 cplb.init_i.tab[cplb.init_i.pos] = -1;
696 cplb.init_d.tab[cplb.init_d.pos] = -1;
697 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
698 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
699
700 }
701
702 #endif
703
704 static u_long get_vco(void)
705 {
706 u_long msel;
707 u_long vco;
708
709 msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
710 if (0 == msel)
711 msel = 64;
712
713 vco = CONFIG_CLKIN_HZ;
714 vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
715 vco = msel * vco;
716 return vco;
717 }
718
719 /*Get the Core clock*/
720 u_long get_cclk(void)
721 {
722 u_long csel, ssel;
723 if (bfin_read_PLL_STAT() & 0x1)
724 return CONFIG_CLKIN_HZ;
725
726 ssel = bfin_read_PLL_DIV();
727 csel = ((ssel >> 4) & 0x03);
728 ssel &= 0xf;
729 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
730 return get_vco() / ssel;
731 return get_vco() >> csel;
732 }
733
734 EXPORT_SYMBOL(get_cclk);
735
736 /* Get the System clock */
737 u_long get_sclk(void)
738 {
739 u_long ssel;
740
741 if (bfin_read_PLL_STAT() & 0x1)
742 return CONFIG_CLKIN_HZ;
743
744 ssel = (bfin_read_PLL_DIV() & 0xf);
745 if (0 == ssel) {
746 printk(KERN_WARNING "Invalid System Clock\n");
747 ssel = 1;
748 }
749
750 return get_vco() / ssel;
751 }
752
753 EXPORT_SYMBOL(get_sclk);
754
755 /*
756 * Get CPU information for use by the procfs.
757 */
758 static int show_cpuinfo(struct seq_file *m, void *v)
759 {
760 char *cpu, *mmu, *fpu, *name;
761 uint32_t revid;
762
763 u_long cclk = 0, sclk = 0;
764 u_int dcache_size = 0, dsup_banks = 0;
765
766 cpu = CPU;
767 mmu = "none";
768 fpu = "none";
769 revid = bfin_revid();
770 name = bfin_board_name;
771
772 cclk = get_cclk();
773 sclk = get_sclk();
774
775 seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
776 "MMU:\t\t%s\n"
777 "FPU:\t\t%s\n"
778 "Core Clock:\t%9lu Hz\n"
779 "System Clock:\t%9lu Hz\n"
780 "BogoMips:\t%lu.%02lu\n"
781 "Calibration:\t%lu loops\n",
782 cpu, revid, mmu, fpu,
783 cclk,
784 sclk,
785 (loops_per_jiffy * HZ) / 500000,
786 ((loops_per_jiffy * HZ) / 5000) % 100,
787 (loops_per_jiffy * HZ));
788 seq_printf(m, "Board Name:\t%s\n", name);
789 seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
790 seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
791 if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
792 seq_printf(m, "I-CACHE:\tON\n");
793 else
794 seq_printf(m, "I-CACHE:\tOFF\n");
795 if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
796 seq_printf(m, "D-CACHE:\tON"
797 #if defined CONFIG_BLKFIN_WB
798 " (write-back)"
799 #elif defined CONFIG_BLKFIN_WT
800 " (write-through)"
801 #endif
802 "\n");
803 else
804 seq_printf(m, "D-CACHE:\tOFF\n");
805
806
807 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
808 case ACACHE_BSRAM:
809 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
810 dcache_size = 16;
811 dsup_banks = 1;
812 break;
813 case ACACHE_BCACHE:
814 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
815 dcache_size = 32;
816 dsup_banks = 2;
817 break;
818 case ASRAM_BSRAM:
819 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
820 dcache_size = 0;
821 dsup_banks = 0;
822 break;
823 default:
824 break;
825 }
826
827
828 seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
829 seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
830 seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
831 BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
832 seq_printf(m,
833 "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
834 dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
835 BLKFIN_DLINES);
836 #ifdef CONFIG_BLKFIN_CACHE_LOCK
837 switch (read_iloc()) {
838 case WAY0_L:
839 seq_printf(m, "Way0 Locked-Down\n");
840 break;
841 case WAY1_L:
842 seq_printf(m, "Way1 Locked-Down\n");
843 break;
844 case WAY01_L:
845 seq_printf(m, "Way0,Way1 Locked-Down\n");
846 break;
847 case WAY2_L:
848 seq_printf(m, "Way2 Locked-Down\n");
849 break;
850 case WAY02_L:
851 seq_printf(m, "Way0,Way2 Locked-Down\n");
852 break;
853 case WAY12_L:
854 seq_printf(m, "Way1,Way2 Locked-Down\n");
855 break;
856 case WAY012_L:
857 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
858 break;
859 case WAY3_L:
860 seq_printf(m, "Way3 Locked-Down\n");
861 break;
862 case WAY03_L:
863 seq_printf(m, "Way0,Way3 Locked-Down\n");
864 break;
865 case WAY13_L:
866 seq_printf(m, "Way1,Way3 Locked-Down\n");
867 break;
868 case WAY013_L:
869 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
870 break;
871 case WAY32_L:
872 seq_printf(m, "Way3,Way2 Locked-Down\n");
873 break;
874 case WAY320_L:
875 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
876 break;
877 case WAY321_L:
878 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
879 break;
880 case WAYALL_L:
881 seq_printf(m, "All Ways are locked\n");
882 break;
883 default:
884 seq_printf(m, "No Ways are locked\n");
885 }
886 #endif
887 return 0;
888 }
889
890 static void *c_start(struct seq_file *m, loff_t *pos)
891 {
892 return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
893 }
894
895 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
896 {
897 ++*pos;
898 return c_start(m, pos);
899 }
900
901 static void c_stop(struct seq_file *m, void *v)
902 {
903 }
904
905 struct seq_operations cpuinfo_op = {
906 .start = c_start,
907 .next = c_next,
908 .stop = c_stop,
909 .show = show_cpuinfo,
910 };
911
912 void __init cmdline_init(const char *r0)
913 {
914 if (r0)
915 strncpy(command_line, r0, COMMAND_LINE_SIZE);
916 }
Tomato firmware and modifications.