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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / bcm57xx / sys / tigon3.c
blob83de7031e3c84d0f40463ee5aa842e79c6d75a2c
1 /******************************************************************************/
2 /* */
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2005 Broadcom */
4 /* Corporation. */
5 /* All rights reserved. */
6 /* */
7 /* This program is free software; you can redistribute it and/or modify */
8 /* it under the terms of the GNU General Public License as published by */
9 /* the Free Software Foundation, located in the file LICENSE. */
10 /* */
11 /* History: */
12 /******************************************************************************/
13
14 /* $Id: tigon3.c 286395 2011-09-27 18:49:01Z $ */
15
16 #include <bcm57xx_cfg.h>
17 #include "mm.h"
18 #include "bcmdevs.h"
19 #include "bcmutils.h"
20 #include "siutils.h"
21 #include "bcmrobo.h"
22
23 /******************************************************************************/
24 /* Local functions. */
25 /******************************************************************************/
26
27 LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
28 LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
29
30 static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
31 static LM_VOID LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice);
32
33 LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
34 LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
35
36 static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice);
37 static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
38 STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
39 LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
40 #ifdef INCLUDE_TBI_SUPPORT
41 STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
42 STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
43 #endif
44 STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
45 STATIC LM_VOID LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice);
46 STATIC LM_STATUS LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice);
47 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
48 LM_VOID LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2);
49 STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
50 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
51 STATIC LM_STATUS LM_DisableChip(PLM_DEVICE_BLOCK pDevice);
52 STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
53 STATIC LM_STATUS LM_DisableFW(PLM_DEVICE_BLOCK pDevice);
54 STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
55 PT3_SND_BD pSendBd);
56 STATIC LM_VOID LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice,
57 LM_RESET_TYPE Mode);
58 STATIC LM_VOID LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice,
59 LM_RESET_TYPE Mode);
60 STATIC LM_VOID LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice,
61 LM_RESET_TYPE Mode);
62 STATIC void LM_GetPhyId(LM_DEVICE_BLOCK *pDevice);
63
64 /******************************************************************************/
65 /* External functions. */
66 /******************************************************************************/
67
68 LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
69 #ifdef INCLUDE_TCP_SEG_SUPPORT
70 LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice);
71 LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice);
72 #endif
73
74 LM_UINT32
75 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
76 {
77 #ifdef PCIX_TARGET_WORKAROUND
78 if (pDevice->Flags & UNDI_FIX_FLAG)
79 {
80 return (LM_RegRdInd(pDevice, Register));
81 }
82 else
83 #endif
84 {
85 return (REG_RD_OFFSET(pDevice, Register));
86 }
87 }
88
89 /* Mainly used to flush posted write before delaying */
90 LM_VOID
91 LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
92 {
93 LM_UINT32 dummy;
94
95 #ifdef PCIX_TARGET_WORKAROUND
96 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
97 {
98 return;
99 }
100 else
101 #endif
102 {
103 if (pDevice->Flags & REG_RD_BACK_FLAG)
104 return;
105
106 dummy = REG_RD_OFFSET(pDevice, Register);
107 }
108 }
109
110 LM_VOID
111 LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32,
112 LM_UINT32 ReadBack)
113 {
114 #ifdef PCIX_TARGET_WORKAROUND
115 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
116 {
117 LM_RegWrInd(pDevice, Register, Value32);
118 }
119 else
120 #endif
121 {
122 LM_UINT32 dummy;
123
124 REG_WR_OFFSET(pDevice, Register, Value32);
125 if (ReadBack && (pDevice->Flags & REG_RD_BACK_FLAG))
126 {
127 dummy = REG_RD_OFFSET(pDevice, Register);
128 }
129 }
130 }
131
132 /******************************************************************************/
133 /* Description: */
134 /* */
135 /* Return: */
136 /******************************************************************************/
137 LM_UINT32
138 LM_RegRdInd(
139 PLM_DEVICE_BLOCK pDevice,
140 LM_UINT32 Register) {
141 LM_UINT32 Value32;
142
143 MM_ACQUIRE_UNDI_LOCK(pDevice);
144 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
145 MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
146 MM_RELEASE_UNDI_LOCK(pDevice);
147
148 return MM_SWAP_LE32(Value32);
149 } /* LM_RegRdInd */
150
151
152
153 /******************************************************************************/
154 /* Description: */
155 /* */
156 /* Return: */
157 /******************************************************************************/
158 LM_VOID
159 LM_RegWrInd(
160 PLM_DEVICE_BLOCK pDevice,
161 LM_UINT32 Register,
162 LM_UINT32 Value32) {
163
164 MM_ACQUIRE_UNDI_LOCK(pDevice);
165 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
166 MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, MM_SWAP_LE32(Value32));
167 MM_RELEASE_UNDI_LOCK(pDevice);
168 } /* LM_RegWrInd */
169
170
171
172 /******************************************************************************/
173 /* Description: */
174 /* */
175 /* Return: */
176 /******************************************************************************/
177 LM_UINT32
178 LM_MemRdInd(
179 PLM_DEVICE_BLOCK pDevice,
180 LM_UINT32 MemAddr) {
181 LM_UINT32 Value32;
182
183 MM_ACQUIRE_UNDI_LOCK(pDevice);
184 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
185 MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
186 MM_RELEASE_UNDI_LOCK(pDevice);
187
188 return MM_SWAP_LE32(Value32);
189 } /* LM_MemRdInd */
190
191
192
193 /******************************************************************************/
194 /* Description: */
195 /* */
196 /* Return: */
197 /******************************************************************************/
198 LM_VOID
199 LM_MemWrInd(
200 PLM_DEVICE_BLOCK pDevice,
201 LM_UINT32 MemAddr,
202 LM_UINT32 Value32) {
203 MM_ACQUIRE_UNDI_LOCK(pDevice);
204 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
205 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, MM_SWAP_LE32(Value32));
206 MM_RELEASE_UNDI_LOCK(pDevice);
207 } /* LM_MemWrInd */
208
209
210 /******************************************************************************/
211 /* Description: */
212 /* */
213 /* Return: */
214 /******************************************************************************/
215 LM_STATUS
216 LM_QueueRxPackets(
217 PLM_DEVICE_BLOCK pDevice) {
218 LM_STATUS Lmstatus;
219 PLM_PACKET pPacket;
220 PT3_RCV_BD pRcvBd = 0;
221 LM_UINT32 StdBdAdded = 0;
222 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
223 LM_UINT32 JumboBdAdded = 0;
224 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
225 LM_UINT32 ConIdx, Idx;
226 LM_UINT32 Diff = 0;
227
228 Lmstatus = LM_STATUS_SUCCESS;
229
230 if (pDevice->Flags & RX_BD_LIMIT_64_FLAG)
231 {
232 ConIdx = pDevice->pStatusBlkVirt->RcvStdConIdx;
233 Diff = (pDevice->RxStdProdIdx - ConIdx) &
234 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
235 if (Diff >= 56)
236 {
237 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
238 {
239 pDevice->QueueAgain = TRUE;
240 }
241 return LM_STATUS_SUCCESS;
242 }
243 }
244
245 pDevice->QueueAgain = FALSE;
246
247 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
248 while(pPacket) {
249 switch(pPacket->u.Rx.RcvProdRing) {
250 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
251 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
252 /* Initialize the buffer descriptor. */
253 Idx = pDevice->RxJumboProdIdx;
254 pRcvBd = &pDevice->pRxJumboBdVirt[Idx];
255
256 pPacket->u.Rx.RcvRingProdIdx = Idx;
257 pDevice->RxJumboRing[Idx] = pPacket;
258 /* Update the producer index. */
259 pDevice->RxJumboProdIdx = (Idx + 1) &
260 T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
261
262 JumboBdAdded++;
263 break;
264 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
265
266 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
267 /* Initialize the buffer descriptor. */
268 Idx = pDevice->RxStdProdIdx;
269 pRcvBd = &pDevice->pRxStdBdVirt[Idx];
270
271 pPacket->u.Rx.RcvRingProdIdx = Idx;
272 pDevice->RxStdRing[Idx] = pPacket;
273 /* Update the producer index. */
274 pDevice->RxStdProdIdx = (Idx + 1) &
275 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
276
277 StdBdAdded++;
278 break;
279
280 case T3_UNKNOWN_RCV_PROD_RING:
281 default:
282 Lmstatus = LM_STATUS_FAILURE;
283 break;
284 } /* switch */
285
286 /* Bail out if there is any error. */
287 if(Lmstatus != LM_STATUS_SUCCESS)
288 {
289 break;
290 }
291
292 /* Initialize the receive buffer pointer */
293 MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
294
295 /* The opaque field may point to an offset from a fix addr. */
296 pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
297 MM_UINT_PTR(pDevice->pPacketDescBase));
298
299 if ((pDevice->Flags & RX_BD_LIMIT_64_FLAG) &&
300 ((Diff + StdBdAdded) >= 63))
301 {
302 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
303 {
304 pDevice->QueueAgain = TRUE;
305 }
306 break;
307 }
308 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
309 } /* while */
310
311 MM_WMB();
312 /* Update the procedure index. */
313 if(StdBdAdded)
314 {
315 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low,
316 pDevice->RxStdProdIdx);
317 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
318 {
319 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
320 }
321 }
322 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
323 if(JumboBdAdded)
324 {
325 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
326 pDevice->RxJumboProdIdx);
327 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
328 {
329 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
330 }
331 }
332 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
333
334 return Lmstatus;
335 } /* LM_QueueRxPackets */
336
337
338
339
340 #define EEPROM_CMD_TIMEOUT 100000
341 #define NVRAM_CMD_TIMEOUT 100000
342
343
344 /******************************************************************************/
345 /* Description: */
346 /* */
347 /* Return: */
348 /******************************************************************************/
349 STATIC LM_STATUS LM_NVRAM_AcquireLock( PLM_DEVICE_BLOCK pDevice )
350 {
351 LM_UINT i;
352 LM_UINT32 value32;
353 LM_STATUS status;
354
355 status = LM_STATUS_SUCCESS;
356
357 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
358 if (pDevice->Flags & SB_CORE_FLAG)
359 return status;
360
361 /* Request access to the flash interface. */
362 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_SET1 );
363
364 /*
365 * The worst case wait time for Nvram arbitration
366 * using serial eprom is about 45 msec on a 5704
367 * with the other channel loading boot code.
368 */
369 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
370 {
371 value32 = REG_RD( pDevice, Nvram.SwArb );
372 if( value32 & SW_ARB_GNT1 )
373 {
374 break;
375 }
376 MM_Wait(20);
377 }
378
379
380 return status;
381 } /* LM_NVRAM_AcquireLock */
382
383
384
385 /******************************************************************************/
386 /* Description: */
387 /* */
388 /* Return: */
389 /******************************************************************************/
390 STATIC LM_STATUS LM_NVRAM_ReleaseLock( PLM_DEVICE_BLOCK pDevice )
391 {
392 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
393 if (pDevice->Flags & SB_CORE_FLAG)
394 return LM_STATUS_SUCCESS;
395
396 /* Relinquish nvram interface. */
397 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 );
398 REG_RD_BACK( pDevice, Nvram.SwArb );
399
400 return LM_STATUS_SUCCESS;
401 } /* LM_NVRAM_ReleaseLock */
402
403
404
405 /******************************************************************************/
406 /* Description: */
407 /* */
408 /* Return: */
409 /******************************************************************************/
410 STATIC LM_STATUS
411 LM_EEPROM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
412 {
413 LM_UINT32 i;
414 LM_UINT32 value32;
415 LM_STATUS status;
416
417 status = LM_STATUS_SUCCESS;
418
419 REG_WR( pDevice, Grc.EepromAddr, cmd );
420
421 for( i = 0; i < EEPROM_CMD_TIMEOUT; i++ )
422 {
423 value32 = REG_RD( pDevice, Grc.EepromAddr );
424 if( value32 & SEEPROM_ADDR_COMPLETE )
425 {
426 break;
427 }
428 MM_Wait(20);
429 }
430
431 if( i == EEPROM_CMD_TIMEOUT )
432 {
433 B57_ERR(("EEPROM command (0x%x) timed out!\n", cmd));
434 status = LM_STATUS_FAILURE;
435 }
436
437 return status;
438 } /* LM_EEPROM_ExecuteCommand */
439
440
441
442 /******************************************************************************/
443 /* Description: */
444 /* */
445 /* Return: */
446 /******************************************************************************/
447 STATIC LM_STATUS
448 LM_NVRAM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
449 {
450 LM_UINT32 i;
451 LM_UINT32 value32;
452 LM_STATUS status;
453
454 status = LM_STATUS_SUCCESS;
455
456 REG_WR( pDevice, Nvram.Cmd, cmd );
457 REG_RD_BACK( pDevice, Nvram.Cmd );
458 MM_Wait(10);
459
460 /* Wait for the command to complete. */
461 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
462 {
463 value32 = REG_RD( pDevice, Nvram.Cmd );
464 if( value32 & NVRAM_CMD_DONE )
465 {
466 break;
467 }
468 MM_Wait(1);
469 }
470
471 if( i == NVRAM_CMD_TIMEOUT )
472 {
473 B57_ERR(("NVRAM command (0x%x) timed out!\n", cmd));
474 status = LM_STATUS_FAILURE;
475 }
476
477 return status;
478 } /* LM_NVRAM_ExecuteCommand */
479
480
481
482 /******************************************************************************/
483 /* Description: */
484 /* */
485 /* Return: */
486 /******************************************************************************/
487 STATIC LM_STATUS
488 LM_EEPROM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
489 LM_UINT32 * data )
490 {
491 LM_UINT32 value32;
492 LM_UINT32 Addr;
493 LM_UINT32 Dev;
494 LM_STATUS status;
495
496 Dev = offset / pDevice->flashinfo.chipsize;
497 Addr = offset % pDevice->flashinfo.chipsize;
498
499 value32 = REG_RD( pDevice, Grc.EepromAddr );
500 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
501 SEEPROM_ADDR_RW_MASK);
502 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
503 SEEPROM_ADDR_START | SEEPROM_ADDR_READ;
504
505 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
506 if( status == LM_STATUS_SUCCESS )
507 {
508 value32 = REG_RD( pDevice, Grc.EepromData );
509
510 /* The endianess of the eeprom and flash interface is different */
511 *data = MM_SWAP_LE32( value32 );
512 }
513
514 return status;
515 } /* LM_EEPROM_Read_UINT32 */
516
517
518
519 /******************************************************************************/
520 /* Description: */
521 /* */
522 /* Return: */
523 /******************************************************************************/
524 STATIC LM_STATUS
525 LM_NVRAM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
526 LM_UINT32 * data )
527 {
528 LM_UINT32 physaddr;
529 LM_UINT32 ctrlreg;
530 LM_UINT32 value32;
531 LM_STATUS status;
532
533 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
534 pDevice->flashinfo.buffered == TRUE )
535 {
536 /*
537 * One supported flash part has 9 address bits to address a
538 * particular page and another 9 address bits to address a
539 * particular byte within that page.
540 */
541 LM_UINT32 pagenmbr;
542
543 pagenmbr = offset / pDevice->flashinfo.pagesize;
544 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
545
546 physaddr = pagenmbr + (offset % pDevice->flashinfo.pagesize);
547 }
548 else
549 {
550 physaddr = offset;
551 }
552
553 REG_WR( pDevice, Nvram.Addr, physaddr );
554
555 ctrlreg = NVRAM_CMD_DONE | NVRAM_CMD_DO_IT |
556 NVRAM_CMD_LAST | NVRAM_CMD_FIRST | NVRAM_CMD_RD;
557
558 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
559 if( status == LM_STATUS_SUCCESS )
560 {
561 value32 = REG_RD( pDevice, Nvram.ReadData );
562
563 /*
564 * Data is swapped so that the byte stream is the same
565 * in big and little endian systems. Caller will do
566 * additional swapping depending on how it wants to
567 * look at the data.
568 */
569 *data = MM_SWAP_BE32( value32 );
570 }
571
572 return status;
573 } /* LM_NVRAM_Read_UINT32 */
574
575
576 /******************************************************************************/
577 /* Description: */
578 /* */
579 /* Return: */
580 /******************************************************************************/
581 STATIC LM_VOID
582 LM_EEPROM_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
583 {
584 LM_UINT32 cursize;
585 LM_UINT32 value32;
586 LM_STATUS status;
587
588 /*
589 * Initialize the chipsize to the largest EEPROM size we support.
590 * This will intentionally restrict our sizing operations to the
591 * first EEPROM chip.
592 */
593 pDevice->flashinfo.chipsize = ATMEL_AT24C512_CHIP_SIZE;
594
595 value32 = 0;
596
597 /* If anything fails, use the smallest chip as the default chip size. */
598 cursize = ATMEL_AT24C64_CHIP_SIZE;
599
600 status = LM_NvramRead(pDevice, 0, &value32);
601 if( status != LM_STATUS_SUCCESS )
602 {
603 goto done;
604 }
605
606 value32 = MM_SWAP_BE32(value32);
607 if( value32 != 0x669955aa )
608 {
609 goto done;
610 }
611
612 /*
613 * Size the chip by reading offsets at increasing powers of two.
614 * When we encounter our validation signature, we know the addressing
615 * has wrapped around, and thus have our chip size.
616 */
617 while( cursize < ATMEL_AT24C64_CHIP_SIZE )
618 {
619 status = LM_NvramRead(pDevice, cursize, &value32);
620 if( status != LM_STATUS_SUCCESS )
621 {
622 cursize = ATMEL_AT24C64_CHIP_SIZE;
623 break;
624 }
625
626 value32 = MM_SWAP_BE32(value32);
627 if( value32 == 0x669955aa )
628 {
629 break;
630 }
631 cursize <<= 1;
632 }
633
634 done:
635
636 *size = cursize;
637 pDevice->flashinfo.pagesize = cursize;
638
639
640 } /* LM_EEPROM_ReadSize */
641
642 /******************************************************************************/
643 /* Description: */
644 /* */
645 /* Return: */
646 /******************************************************************************/
647 STATIC LM_STATUS
648 LM_FLASH_Atmel_Buffered_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
649 {
650 LM_UINT32 config3;
651 LM_UINT32 value32;
652 LM_STATUS status;
653
654 /* Temporarily replace the read command with a "read ID" command. */
655 config3 = REG_RD( pDevice, Nvram.Config3 );
656 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
657 value32 |= NVRAM_READ_COMMAND(0x57);
658 REG_WR( pDevice, Nvram.Config3, value32 );
659
660 REG_WR( pDevice, Nvram.Addr, 0x0 );
661
662 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
663
664 /* Restore the original read command. */
665 REG_WR( pDevice, Nvram.Config3, config3 );
666 if( status == LM_STATUS_SUCCESS )
667 {
668 switch( value32 & 0x3c )
669 {
670 case 0x0c:
671 *size = (1 * (1<<20))/8;
672 break;
673 case 0x14:
674 *size = (2 * (1<<20))/8;
675 break;
676 case 0x1c:
677 *size = (4 * (1<<20))/8;
678 break;
679 case 0x24:
680 *size = (8 * (1<<20))/8;
681 break;
682 }
683 }
684
685 return status;
686 } /* LM_FLASH_Atmel_Buffered_ReadSize */
687
688
689
690 /******************************************************************************/
691 /* Description: */
692 /* */
693 /* Return: */
694 /******************************************************************************/
695 STATIC LM_STATUS
696 LM_FLASH_ST_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
697 {
698 LM_STATUS status;
699 LM_UINT32 i;
700 LM_UINT32 ctrlreg;
701 LM_UINT32 value32;
702 LM_UINT32 config1;
703
704 /* We need to get the size through pass-thru mode. */
705 config1 = REG_RD( pDevice, Nvram.Config1 );
706 value32 = config1 | FLASH_PASS_THRU_MODE;
707 REG_WR( pDevice, Nvram.Config1, value32 );
708
709 /* Issue the "read ID" command. */
710 REG_WR( pDevice, Nvram.WriteData, 0x9f );
711
712 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_FIRST | NVRAM_CMD_WR;
713 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
714 if( status == LM_STATUS_FAILURE )
715 {
716 goto done;
717 }
718
719 /* Read in the "read ID" response. */
720 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
721
722 /* Discard the first three bytes. */
723 for( i = 0; i < 2; i++ )
724 {
725 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
726 if( status == LM_STATUS_FAILURE )
727 {
728 goto done;
729 }
730
731 value32 = REG_RD(pDevice, Nvram.ReadData);
732 }
733
734 ctrlreg |= NVRAM_CMD_LAST;
735
736 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
737 if( status == LM_STATUS_SUCCESS )
738 {
739 value32 = REG_RD(pDevice, Nvram.ReadData) & 0xff;
740 switch( value32 )
741 {
742 case 0x11:
743 *size = (1 * (1<<20)) / 8;
744 break;
745 case 0x12:
746 *size = (2 * (1<<20)) / 8;
747 break;
748 case 0x13:
749 *size = (4 * (1<<20)) / 8;
750 break;
751 case 0x14:
752 *size = (8 * (1<<20)) / 8;
753 break;
754 }
755 }
756
757 done:
758
759 /* Restore the previous flash mode. */
760 REG_WR( pDevice, Nvram.Config1, config1 );
761
762 return status;
763 } /* LM_FLASH_ST_ReadSize */
764
765
766
767 /******************************************************************************/
768 /* Description: */
769 /* */
770 /* Return: */
771 /******************************************************************************/
772 STATIC LM_STATUS
773 LM_FLASH_Saifun_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
774 {
775 LM_UINT32 config3;
776 LM_UINT32 value32;
777 LM_STATUS status;
778
779 /* Temporarily replace the read command with a "read ID" command. */
780 config3 = REG_RD( pDevice, Nvram.Config3 );
781 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
782 value32 |= NVRAM_READ_COMMAND(0xab);
783 REG_WR( pDevice, Nvram.Config3, value32 );
784
785 REG_WR( pDevice, Nvram.Addr, 0x0 );
786
787 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
788
789 /* Restore the original read command. */
790 REG_WR( pDevice, Nvram.Config3, config3 );
791
792 if( status == LM_STATUS_SUCCESS )
793 {
794 switch( value32 & 0xff )
795 {
796 case 0x05:
797 *size = (512 * (1<<10)/8);
798 break;
799 case 0x10:
800 *size = (1 * (1<<20)/8);
801 break;
802 case 0x11:
803 *size = (2 * (1<<20)/8);
804 break;
805 }
806 }
807
808 return status;
809 } /* LM_FLASH_Saifun_ReadSize */
810
811
812
813 /******************************************************************************/
814 /* Description: */
815 /* */
816 /* Return: */
817 /******************************************************************************/
818 STATIC LM_STATUS
819 LM_FLASH_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
820 {
821 LM_UINT32 value32;
822 LM_STATUS status;
823
824 status = LM_NVRAM_AcquireLock( pDevice );
825 if( status == LM_STATUS_FAILURE )
826 {
827 return status;
828 }
829
830 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
831 {
832 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
833 {
834 value32 = REG_RD( pDevice, Nvram.NvmAccess );
835 value32 |= NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE;
836 REG_WR( pDevice, Nvram.NvmAccess, value32 );
837 }
838 }
839
840 switch( pDevice->flashinfo.jedecnum )
841 {
842 case JEDEC_ST:
843 status = LM_FLASH_ST_ReadSize( pDevice, size );
844 break;
845 case JEDEC_ATMEL:
846 if( pDevice->flashinfo.buffered == TRUE )
847 {
848 status = LM_FLASH_Atmel_Buffered_ReadSize( pDevice, size );
849 }
850 else
851 {
852 status = LM_STATUS_FAILURE;
853 }
854 break;
855 case JEDEC_SAIFUN:
856 status = LM_FLASH_Saifun_ReadSize( pDevice, size );
857 break;
858 case JEDEC_SST:
859 default:
860 status = LM_STATUS_FAILURE;
861 }
862
863 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
864 {
865 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
866 {
867 value32 = REG_RD( pDevice, Nvram.NvmAccess );
868 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
869 REG_WR( pDevice, Nvram.NvmAccess, value32 );
870 }
871 }
872
873 LM_NVRAM_ReleaseLock( pDevice );
874
875 return status;
876 } /* LM_FLASH_ReadSize */
877
878 STATIC LM_VOID LM_NVRAM_Detect_570X( PLM_DEVICE_BLOCK pDevice )
879 {
880 LM_UINT32 value32;
881
882 value32 = REG_RD(pDevice, Nvram.Config1);
883
884 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
885 {
886 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
887 }
888 else
889 {
890 /*
891 * 5705 and older products do not have bits 24 and 25 defined.
892 * If we've gotten here, then we can guarantee the flash is
893 * an Atmel AT45DB011DB.
894 */
895 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
896 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
897 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
898 pDevice->flashinfo.buffered = TRUE;
899 }
900 } /* LM_NVRAM_Detect_570X */
901
902 STATIC LM_VOID LM_NVRAM_Detect_5750( PLM_DEVICE_BLOCK pDevice )
903 {
904 LM_UINT32 value32;
905
906 value32 = REG_RD(pDevice, Nvram.Config1);
907
908 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
909 {
910 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
911 return;
912 }
913
914 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
915
916 switch( value32 & FLASH_PART_5750_TYPEMASK )
917 {
918 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
919 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
920 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
921 pDevice->flashinfo.buffered = TRUE;
922 break;
923 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
924 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
925 pDevice->flashinfo.pagesize = ATMEL_AT25F512_PAGE_SIZE;
926 pDevice->flashinfo.buffered = FALSE;
927 break;
928 case FLASH_VENDOR_ST:
929 pDevice->flashinfo.jedecnum = JEDEC_ST;
930 pDevice->flashinfo.pagesize = ST_M45PEX0_PAGE_SIZE;
931 pDevice->flashinfo.buffered = TRUE;
932 break;
933 case FLASH_VENDOR_SAIFUN:
934 pDevice->flashinfo.jedecnum = JEDEC_SAIFUN;
935 pDevice->flashinfo.pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
936 pDevice->flashinfo.buffered = FALSE;
937 break;
938 case FLASH_VENDOR_SST_SMALL:
939 case FLASH_VENDOR_SST_LARGE:
940 pDevice->flashinfo.jedecnum = JEDEC_SST;
941 pDevice->flashinfo.pagesize = SST_25VF0X0_PAGE_SIZE;
942 pDevice->flashinfo.buffered = FALSE;
943 break;
944 default:
945 B57_ERR(("bcm5700 : Unknown NVRAM type.\n"));
946 pDevice->flashinfo.jedecnum = 0;
947 pDevice->flashinfo.romtype = 0;
948 pDevice->flashinfo.buffered = FALSE;
949 pDevice->flashinfo.pagesize = 0;
950 }
951 } /* LM_NVRAM_Detect_5750 */
952
953 STATIC LM_VOID LM_NVRAM_Detect_5752( PLM_DEVICE_BLOCK pDevice )
954 {
955 LM_BOOL supported;
956 LM_UINT32 value32;
957
958 supported = FALSE;
959
960 value32 = REG_RD(pDevice, Nvram.Config1);
961
962 if(value32 & BIT_27)
963 pDevice->Flags |= PROTECTED_NVRAM_FLAG;
964
965 switch( value32 & FLASH_PART_5752_TYPEMASK )
966 {
967 case FLASH_PART_5752_EEPROM_ATMEL_64K:
968 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
969 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
970 pDevice->flashinfo.buffered = FALSE;
971 pDevice->flashinfo.chipsize = (64 * (1<<10)/8);
972 supported = TRUE;
973 break;
974
975 case FLASH_PART_5752_EEPROM_ATMEL_376K:
976 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
977 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
978 pDevice->flashinfo.buffered = FALSE;
979 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
980 supported = TRUE;
981 break;
982
983 case FLASH_PART_5752_FLASH_ATMEL_AT45DB041:
984 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
985 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
986 pDevice->flashinfo.buffered = TRUE;
987 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
988 supported = TRUE;
989 break;
990
991 case FLASH_PART_5752_FLASH_ATMEL_AT25F512:
992 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
993 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
994 pDevice->flashinfo.buffered = FALSE;
995 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
996 supported = TRUE;
997 break;
998
999 case FLASH_PART_5752_FLASH_ST_M25P10A:
1000 pDevice->flashinfo.jedecnum = JEDEC_ST;
1001 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1002 pDevice->flashinfo.buffered = TRUE;
1003 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1004 supported = TRUE;
1005 break;
1006 case FLASH_PART_5752_FLASH_ST_M25P05A:
1007 pDevice->flashinfo.jedecnum = JEDEC_ST;
1008 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1009 pDevice->flashinfo.buffered = TRUE;
1010 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1011 supported = TRUE;
1012 break;
1013
1014 case FLASH_PART_5752_FLASH_ST_M45PE10:
1015 pDevice->flashinfo.jedecnum = JEDEC_ST;
1016 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1017 pDevice->flashinfo.buffered = TRUE;
1018 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1019 supported = TRUE;
1020 break;
1021
1022 case FLASH_PART_5752_FLASH_ST_M45PE20:
1023 pDevice->flashinfo.jedecnum = JEDEC_ST;
1024 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1025 pDevice->flashinfo.buffered = TRUE;
1026 pDevice->flashinfo.chipsize = (2 * (1<<20)) / 8;
1027 supported = TRUE;
1028 break;
1029
1030 case FLASH_PART_5752_FLASH_ST_M45PE40:
1031 pDevice->flashinfo.jedecnum = JEDEC_ST;
1032 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1033 pDevice->flashinfo.buffered = TRUE;
1034 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
1035 supported = TRUE;
1036 break;
1037 default:
1038 B57_ERR(("bcm5700 : Unknown NVRAM type.\n"));
1039 }
1040
1041 if( pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1042 {
1043 switch( value32 & FLASH_PART_5752_PAGEMASK )
1044 {
1045 case FLASH_PART_5752_PAGE_SIZE_256B:
1046 pDevice->flashinfo.pagesize = 256;
1047 break;
1048 case FLASH_PART_5752_PAGE_SIZE_512B:
1049 pDevice->flashinfo.pagesize = 512;
1050 break;
1051 case FLASH_PART_5752_PAGE_SIZE_1K:
1052 pDevice->flashinfo.pagesize = 1024;
1053 break;
1054 case FLASH_PART_5752_PAGE_SIZE_2K:
1055 pDevice->flashinfo.pagesize = 2048;
1056 break;
1057 case FLASH_PART_5752_PAGE_SIZE_4K:
1058 pDevice->flashinfo.pagesize = 4096;
1059 break;
1060 case FLASH_PART_5752_PAGE_SIZE_264B:
1061 pDevice->flashinfo.pagesize = 264;
1062 break;
1063 default:
1064 B57_ERR(("bcm5700 : Unknown NVRAM page size.\n"));
1065 supported = FALSE;
1066 }
1067 }
1068
1069 if( supported != TRUE )
1070 {
1071 B57_ERR(("Flash type unsupported!!!\n"));
1072 pDevice->flashinfo.jedecnum = 0;
1073 pDevice->flashinfo.romtype = 0;
1074 pDevice->flashinfo.buffered = FALSE;
1075 pDevice->flashinfo.pagesize = 0;
1076 }
1077
1078
1079 } /* LM_NVRAM_Detect_5752 */
1080
1081
1082 /******************************************************************************/
1083 /* Description: */
1084 /* */
1085 /* Return: */
1086 /******************************************************************************/
1087 STATIC LM_VOID LM_NVRAM_Init( PLM_DEVICE_BLOCK pDevice )
1088 {
1089 LM_UINT32 Value32;
1090
1091 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1092 if (pDevice->Flags & SB_CORE_FLAG)
1093 return;
1094
1095 pDevice->NvramSize = 0;
1096
1097 /* Intialize clock period and state machine. */
1098 Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
1099 SEEPROM_ADDR_FSM_RESET;
1100 REG_WR(pDevice, Grc.EepromAddr, Value32);
1101 REG_RD_BACK(pDevice, Grc.EepromAddr);
1102
1103 MM_Wait(100);
1104
1105 /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
1106 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
1107 REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
1108
1109 switch( T3_ASIC_REV(pDevice->ChipRevId) )
1110 {
1111 case T3_ASIC_REV_5700:
1112 case T3_ASIC_REV_5701:
1113 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1114 break;
1115 case T3_ASIC_REV_5752:
1116 LM_NVRAM_Detect_5752(pDevice);
1117 break;
1118 case T3_ASIC_REV_5714_A0:
1119 case T3_ASIC_REV_5780:
1120 case T3_ASIC_REV_5714:
1121 case T3_ASIC_REV_5750:
1122 LM_NVRAM_Detect_5750(pDevice);
1123 break;
1124 default:
1125 LM_NVRAM_Detect_570X(pDevice);
1126 }
1127
1128 /* Set the 5701 compatibility mode if we are using EEPROM. */
1129 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1130 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 &&
1131 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1132 {
1133 Value32 = REG_RD(pDevice, Nvram.Config1);
1134
1135 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1136 {
1137 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1138 {
1139 REG_WR(pDevice, Nvram.NvmAccess,
1140 REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN);
1141 }
1142 }
1143
1144 /* Use the new interface to read EEPROM. */
1145 Value32 &= ~FLASH_COMPAT_BYPASS;
1146
1147 REG_WR(pDevice, Nvram.Config1, Value32);
1148
1149 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1150 {
1151 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1152 {
1153 REG_WR(pDevice, Nvram.NvmAccess,
1154 REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN);
1155 }
1156 }
1157 }
1158
1159 if( !(T3_ASIC_5752(pDevice->ChipRevId)) )
1160 {
1161 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1162 {
1163 /* The only EEPROM we support is an ATMEL */
1164 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1165 pDevice->flashinfo.pagesize = 0;
1166 pDevice->flashinfo.buffered = FALSE;
1167
1168 LM_EEPROM_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1169 }
1170 else
1171 {
1172 LM_FLASH_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1173 pDevice->Flags |= FLASH_DETECTED_FLAG;
1174 }
1175 }
1176
1177 pDevice->NvramSize = pDevice->flashinfo.chipsize;
1178
1179 B57_INFO(("*nvram:size=0x%x jnum=0x%x page=0x%x buff=0x%x \n",
1180 pDevice->NvramSize, pDevice->flashinfo.jedecnum,
1181 pDevice->flashinfo.pagesize, pDevice->flashinfo.buffered));
1182
1183 } /* LM_NVRAM_Init */
1184
1185
1186
1187 /******************************************************************************/
1188 /* Description: */
1189 /* */
1190 /* Return: */
1191 /******************************************************************************/
1192 LM_STATUS
1193 LM_NvramRead( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset, LM_UINT32 * data )
1194 {
1195 LM_UINT32 value32;
1196 LM_STATUS status;
1197
1198 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1199 if (pDevice->Flags & SB_CORE_FLAG) {
1200 *data = 0xffffffff;
1201 return LM_STATUS_FAILURE;
1202 }
1203
1204 if( offset >= pDevice->flashinfo.chipsize )
1205 {
1206 return LM_STATUS_FAILURE;
1207 }
1208
1209 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1210 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1211 {
1212 status = LM_EEPROM_Read_UINT32( pDevice, offset, data );
1213 }
1214 else
1215 {
1216 status = LM_NVRAM_AcquireLock( pDevice );
1217 if( status == LM_STATUS_FAILURE )
1218 {
1219 return status;
1220 }
1221
1222 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1223 {
1224 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1225 {
1226 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1227 value32 |= NVRAM_ACCESS_ENABLE;
1228 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1229 }
1230 }
1231
1232 status = LM_NVRAM_Read_UINT32(pDevice, offset, data);
1233
1234 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1235 {
1236 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1237 {
1238 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1239 value32 &= ~NVRAM_ACCESS_ENABLE;
1240 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1241 }
1242 }
1243
1244 LM_NVRAM_ReleaseLock( pDevice );
1245 }
1246
1247 return status;
1248 } /* LM_NvramRead */
1249
1250
1251
1252 #ifdef ETHTOOL_SEEPROM
1253
1254 /******************************************************************************/
1255 /* Description: */
1256 /* */
1257 /* Return: */
1258 /******************************************************************************/
1259 STATIC LM_STATUS
1260 LM_NVRAM_ReadBlock(PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1261 LM_UINT8 *data, LM_UINT32 size)
1262 {
1263 LM_STATUS status;
1264 LM_UINT32 value32;
1265 LM_UINT32 bytecnt;
1266 LM_UINT8 * srcptr;
1267
1268 status = LM_STATUS_SUCCESS;
1269
1270 while( size > 0 )
1271 {
1272 /* Make sure the read is word aligned. */
1273 value32 = offset & 0x3;
1274 if( value32 )
1275 {
1276 bytecnt = sizeof(LM_UINT32) - value32;
1277 offset -= value32;
1278 srcptr = (LM_UINT8 *)(&value32) + value32;
1279 }
1280 else
1281 {
1282 bytecnt = sizeof(LM_UINT32);
1283 srcptr = (LM_UINT8 *)(&value32);
1284 }
1285
1286 if( bytecnt > size )
1287 {
1288 bytecnt = size;
1289 }
1290
1291 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1292 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 )
1293 {
1294 status = LM_NVRAM_Read_UINT32( pDevice, offset, &value32 );
1295 }
1296 else
1297 {
1298 status = LM_EEPROM_Read_UINT32( pDevice, offset, &value32 );
1299 }
1300
1301 if( status != LM_STATUS_SUCCESS )
1302 {
1303 break;
1304 }
1305
1306 memcpy( data, srcptr, bytecnt );
1307
1308 offset += sizeof(LM_UINT32);
1309 data += bytecnt;
1310 size -= bytecnt;
1311 }
1312
1313 return status;
1314 } /* LM_NVRAM_ReadBlock */
1315
1316 /******************************************************************************/
1317 /* Description: */
1318 /* */
1319 /* Return: */
1320 /******************************************************************************/
1321 STATIC LM_STATUS
1322 LM_EEPROM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1323 LM_UINT8 * data, LM_UINT32 size )
1324 {
1325 LM_UINT8 * dstptr;
1326 LM_UINT32 value32;
1327 LM_UINT32 bytecnt;
1328 LM_UINT32 subword1;
1329 LM_UINT32 subword2;
1330 LM_UINT32 Addr;
1331 LM_UINT32 Dev;
1332 LM_STATUS status;
1333
1334 if( offset > pDevice->flashinfo.chipsize )
1335 {
1336 return LM_STATUS_FAILURE;
1337 }
1338
1339 status = LM_STATUS_SUCCESS;
1340
1341 if( size == 0 )
1342 {
1343 return status;
1344 }
1345
1346 if( offset & 0x3 )
1347 {
1348 /*
1349 * If our initial offset does not fall on a word boundary, we
1350 * have to do a read / modify / write to preserve the
1351 * preceding bits we are not interested in.
1352 */
1353 status = LM_EEPROM_Read_UINT32(pDevice, offset & ~0x3, &subword1);
1354 if( status == LM_STATUS_FAILURE )
1355 {
1356 return status;
1357 }
1358 }
1359
1360 if( (offset + size) & 0x3 )
1361 {
1362 /*
1363 * Likewise, if our ending offset does not fall on a word
1364 * boundary, we have to do a read / modify / write to
1365 * preserve the trailing bits we are not interested in.
1366 */
1367 status = LM_EEPROM_Read_UINT32( pDevice, (offset + size) & ~0x3,
1368 &subword2 );
1369 if( status == LM_STATUS_FAILURE )
1370 {
1371 return status;
1372 }
1373 }
1374
1375 /* Enable EEPROM write. */
1376 if( pDevice->Flags & EEPROM_WP_FLAG )
1377 {
1378 REG_WR( pDevice, Grc.LocalCtrl,
1379 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1 );
1380 REG_RD_BACK( pDevice, Grc.LocalCtrl );
1381 MM_Wait(40);
1382
1383 value32 = REG_RD( pDevice, Grc.LocalCtrl );
1384 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1385 {
1386 return LM_STATUS_FAILURE;
1387 }
1388 }
1389
1390 while( size > 0 )
1391 {
1392 value32 = offset & 0x3;
1393 if( value32 )
1394 {
1395 /*
1396 * We have to read / modify / write the data to
1397 * preserve the flash contents preceding the offset.
1398 */
1399 offset &= ~0x3;
1400
1401 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1402 bytecnt = sizeof(LM_UINT32) - value32;
1403 value32 = subword1;
1404 }
1405 else if( size < sizeof(LM_UINT32) )
1406 {
1407 dstptr = (LM_UINT8 *)(&value32);
1408 bytecnt = size;
1409 value32 = subword2;
1410 }
1411 else
1412 {
1413 dstptr = (LM_UINT8 *)(&value32);
1414 bytecnt = sizeof(LM_UINT32);
1415 }
1416
1417 if( size < bytecnt )
1418 {
1419 bytecnt = size;
1420 }
1421
1422 memcpy( dstptr, (void *)data, bytecnt );
1423
1424 data += bytecnt;
1425 size -= bytecnt;
1426
1427 /*
1428 * Swap the data so that the byte stream will be
1429 * written the same in little and big endian systems.
1430 */
1431 value32 = MM_SWAP_LE32(value32);
1432
1433 /* Set the write value to the eeprom */
1434 REG_WR( pDevice, Grc.EepromData, value32 );
1435
1436 Dev = offset / pDevice->flashinfo.chipsize;
1437 Addr = offset % pDevice->flashinfo.chipsize;
1438
1439 value32 = REG_RD( pDevice, Grc.EepromAddr );
1440 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
1441 SEEPROM_ADDR_RW_MASK);
1442 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
1443 SEEPROM_ADDR_START | SEEPROM_ADDR_WRITE;
1444
1445 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
1446 if( status != LM_STATUS_SUCCESS )
1447 {
1448 break;
1449 }
1450
1451 offset += sizeof(LM_UINT32);
1452 }
1453
1454 /* Write-protect EEPROM. */
1455 if( pDevice->Flags & EEPROM_WP_FLAG )
1456 {
1457 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1458 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1459 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1460 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1461 MM_Wait(40);
1462 }
1463
1464 return status;
1465 } /* LM_EEPROM_WriteBlock */
1466
1467
1468
1469 /******************************************************************************/
1470 /* Description: */
1471 /* */
1472 /* Return: */
1473 /******************************************************************************/
1474 STATIC LM_STATUS
1475 LM_NVRAM_WriteBlockUnBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1476 LM_UINT8 * data, LM_UINT32 size )
1477 {
1478 LM_UINT i;
1479 LM_STATUS status;
1480 LM_UINT32 tgtoff;
1481 LM_UINT32 value32;
1482 LM_UINT32 ctrlreg;
1483 LM_UINT32 pagesize;
1484 LM_UINT32 pagemask;
1485 LM_UINT32 physaddr;
1486
1487 /* Cache the pagesize. */
1488 pagesize = pDevice->flashinfo.pagesize;
1489
1490 if( pDevice->flashinfo.jedecnum == JEDEC_SAIFUN )
1491 {
1492 /* Config2 = 0x500d8 */
1493 /* Config3 = 0x3840253 */
1494 /* Write1 = 0xaf000400 */
1495
1496 /* Configure the erase command to be "page erase". */
1497 /* Configure the status command to be "read status register". */
1498 value32 = REG_RD( pDevice, Nvram.Config2 );
1499 value32 &= ~(NVRAM_STATUS_COMMAND( NVRAM_COMMAND_MASK ) |
1500 NVRAM_ERASE_COMMAND( NVRAM_COMMAND_MASK ));
1501 value32 |= NVRAM_STATUS_COMMAND( SAIFUN_SA25F0XX_READ_STATUS_CMD ) |
1502 NVRAM_ERASE_COMMAND( SAIFUN_SA25F0XX_PAGE_ERASE_CMD );
1503 REG_WR( pDevice, Nvram.Config2, value32 );
1504
1505 /* Configure the write command to be "page write". */
1506 value32 = REG_RD( pDevice, Nvram.Config3 );
1507 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1508 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( SAIFUN_SA25F0XX_PAGE_WRITE_CMD );
1509 REG_WR( pDevice, Nvram.Config3, value32 );
1510
1511 /* Make sure the "write enable" command is correct. */
1512 value32 = REG_RD( pDevice, Nvram.Write1 );
1513 value32 &= ~NVRAM_WRITE1_WRENA_CMD( NVRAM_COMMAND_MASK );
1514 value32 |= NVRAM_WRITE1_WRENA_CMD( SAIFUN_SA25F0XX_WRENA_CMD );
1515 REG_WR( pDevice, Nvram.Write1, value32 );
1516
1517 pagemask = SAIFUN_SA25F0XX_PAGE_MASK;
1518 }
1519 else
1520 {
1521 /* Unsupported flash type */
1522 return LM_STATUS_FAILURE;
1523 }
1524
1525 if( size == 0 )
1526 {
1527 status = LM_STATUS_SUCCESS;
1528 goto done;
1529 }
1530
1531 while( size > 0 )
1532 {
1533 /* Align the offset to a page boundary. */
1534 physaddr = offset & ~pagemask;
1535
1536 status = LM_NVRAM_ReadBlock( pDevice, physaddr,
1537 pDevice->flashbuffer,
1538 pagesize );
1539 if( status == LM_STATUS_FAILURE )
1540 {
1541 break;
1542 }
1543
1544 /* Calculate the target index. */
1545 tgtoff = offset & pagemask;
1546
1547 /* Copy the new data into the save buffer. */
1548 for( i = tgtoff; i < pagesize && size > 0; i++ )
1549 {
1550 pDevice->flashbuffer[i] = *data++;
1551 size--;
1552 }
1553
1554 /* Move the offset to the next page. */
1555 offset = offset + (pagesize - tgtoff);
1556
1557 /*
1558 * The LM_NVRAM_ReadBlock() function releases
1559 * the access enable bit. Reacquire it.
1560 */
1561 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1562 REG_WR(pDevice, Nvram.NvmAccess, NVRAM_ACCESS_ENABLE);
1563
1564
1565 /*
1566 * Before we can erase the flash page, we need
1567 * to issue a special "write enable" command.
1568 */
1569 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1570
1571 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1572 if( status == LM_STATUS_FAILURE )
1573 {
1574 break;
1575 }
1576
1577 /* Erase the target page */
1578 REG_WR(pDevice, Nvram.Addr, physaddr);
1579
1580 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR |
1581 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
1582
1583 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1584 if( status == LM_STATUS_FAILURE )
1585 {
1586 break;
1587 }
1588
1589 /* Issue another write enable to start the write. */
1590 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1591
1592 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1593 if( status == LM_STATUS_FAILURE )
1594 {
1595 break;
1596 }
1597
1598 /* Copy the data into our NIC's buffers. */
1599 for( i = 0; i < pagesize; i+= 4 )
1600 {
1601 value32 = *((LM_UINT32 *)(&pDevice->flashbuffer[i]));
1602 value32 = MM_SWAP_BE32( value32 );
1603
1604 /* Write the location we wish to write to. */
1605 REG_WR( pDevice, Nvram.Addr, physaddr );
1606
1607 /* Write the data we wish to write. */
1608 REG_WR( pDevice, Nvram.WriteData, value32 );
1609
1610 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR;
1611
1612 if( i == 0 )
1613 {
1614 ctrlreg |= NVRAM_CMD_FIRST;
1615 }
1616 else if( i == (pagesize - 4) )
1617 {
1618 ctrlreg |= NVRAM_CMD_LAST;
1619 }
1620
1621 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1622 if( status == LM_STATUS_FAILURE )
1623 {
1624 size = 0;
1625 break;
1626 }
1627
1628 physaddr += sizeof(LM_UINT32);
1629 }
1630 }
1631
1632 /* Paranoia. Turn off the "write enable" flag. */
1633 ctrlreg = NVRAM_CMD_WRITE_DISABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1634
1635 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1636
1637 done:
1638
1639 return status;
1640 } /* LM_NVRAM_WriteBlockUnBuffered */
1641
1642
1643
1644 /******************************************************************************/
1645 /* Description: */
1646 /* */
1647 /* Return: */
1648 /******************************************************************************/
1649 STATIC LM_STATUS
1650 LM_NVRAM_WriteBlockBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1651 LM_UINT8 * data, LM_UINT32 size )
1652 {
1653 LM_STATUS status;
1654 LM_UINT32 value32;
1655 LM_UINT32 bytecnt;
1656 LM_UINT32 ctrlreg;
1657 LM_UINT32 pageoff;
1658 LM_UINT32 physaddr;
1659 LM_UINT32 subword1;
1660 LM_UINT32 subword2;
1661 LM_UINT8 * dstptr;
1662
1663 if(T3_ASIC_5752(pDevice->ChipRevId) &&
1664 (pDevice->flashinfo.jedecnum == JEDEC_ST ||
1665 pDevice->flashinfo.jedecnum == JEDEC_ATMEL ))
1666 {
1667 /* Do nothing as the 5752 does will take care of it */
1668 }
1669 else if( pDevice->flashinfo.jedecnum == JEDEC_ST )
1670 {
1671 /*
1672 * Program our chip to look at bit0 of the NVRAM's status
1673 * register when polling the write or erase operation status.
1674 */
1675 value32 = REG_RD(pDevice, Nvram.Config1);
1676 value32 &= ~FLASH_STATUS_BITS_MASK;
1677 REG_WR( pDevice, Nvram.Config1, value32 );
1678
1679 /* Program the "read status" and "page erase" commands. */
1680 value32 = NVRAM_STATUS_COMMAND( ST_M45PEX0_READ_STATUS_CMD ) |
1681 NVRAM_ERASE_COMMAND( ST_M45PEX0_PAGE_ERASE_CMD );
1682 REG_WR( pDevice, Nvram.Config2, value32 );
1683
1684 /* Set the write command to be "page program". */
1685 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1686 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1687 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ST_M45PEX0_PAGE_PRGM_CMD );
1688 REG_WR( pDevice, Nvram.Config3, value32 );
1689
1690 /* Set the "write enable" and "write disable" commands. */
1691 value32 = NVRAM_WRITE1_WRENA_CMD( ST_M45PEX0_WRENA_CMD ) |
1692 NVRAM_WRITE1_WRDIS_CMD( ST_M45PEX0_WRDIS_CMD );
1693 REG_WR( pDevice, Nvram.Write1, value32 );
1694 }
1695 else if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL )
1696 {
1697 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1698 {
1699 }
1700 else if( pDevice->flashinfo.buffered == TRUE )
1701 {
1702 /*
1703 * Program our chip to look at bit7 of the NVRAM's status
1704 * register when polling the write operation status.
1705 */
1706 value32 = REG_RD(pDevice, Nvram.Config1);
1707 value32 |= FLASH_STATUS_BITS_MASK;
1708 REG_WR( pDevice, Nvram.Config1, value32 );
1709
1710 /* Set the write command to be "page program". */
1711 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1712 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1713 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD );
1714 REG_WR( pDevice, Nvram.Config3, value32 );
1715 /* Config1 = 0x2008273 */
1716 /* Config2 = 0x00570081 */
1717 /* Config3 = 0x68848353 */
1718 }
1719 else
1720 {
1721 /* NVRAM type unsupported. */
1722 return LM_STATUS_FAILURE;
1723 }
1724 }
1725 else
1726 {
1727 /* NVRAM type unsupported. */
1728 return LM_STATUS_FAILURE;
1729 }
1730
1731 status = LM_STATUS_SUCCESS;
1732
1733 if( offset & 0x3 )
1734 {
1735 /*
1736 * If our initial offset does not fall on a word boundary, we
1737 * have to do a read / modify / write to preserve the
1738 * preceding bits we are not interested in.
1739 */
1740 status = LM_NVRAM_ReadBlock( pDevice, offset & ~0x3,
1741 (LM_UINT8 *)&subword1,
1742 sizeof(subword1) );
1743 if( status == LM_STATUS_FAILURE )
1744 {
1745 return status;
1746 }
1747 }
1748
1749 if( (offset + size) & 0x3 )
1750 {
1751 /*
1752 * Likewise, if our ending offset does not fall on a word
1753 * boundary, we have to do a read / modify / write to
1754 * preserve the trailing bits we are not interested in.
1755 */
1756 status = LM_NVRAM_ReadBlock( pDevice, (offset + size) & ~0x3,
1757 (LM_UINT8 *)&subword2,
1758 sizeof(subword2) );
1759 if( status == LM_STATUS_FAILURE )
1760 {
1761 return status;
1762 }
1763 }
1764
1765 ctrlreg = NVRAM_CMD_FIRST;
1766
1767 while( size > 0 )
1768 {
1769 value32 = offset & 0x3;
1770 if( value32 )
1771 {
1772 /*
1773 * We have to read / modify / write the data to
1774 * preserve the flash contents preceding the offset.
1775 */
1776 offset &= ~0x3;
1777
1778 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1779 bytecnt = sizeof(LM_UINT32) - value32;
1780 value32 = subword1;
1781 }
1782 else if( size < sizeof(LM_UINT32) )
1783 {
1784 dstptr = (LM_UINT8 *)(&value32);
1785 bytecnt = size;
1786 value32 = subword2;
1787 }
1788 else
1789 {
1790 dstptr = (LM_UINT8 *)(&value32);
1791 bytecnt = sizeof(LM_UINT32);
1792 }
1793
1794 if( size < bytecnt )
1795 {
1796 bytecnt = size;
1797 }
1798
1799 memcpy( dstptr, (void *)data, bytecnt );
1800
1801 data += bytecnt;
1802 size -= bytecnt;
1803
1804 /*
1805 * Swap the data so that the byte stream will be
1806 * written the same in little and big endian systems.
1807 */
1808 value32 = MM_SWAP_BE32(value32);
1809
1810 /* Set the desired write data value to the flash. */
1811 REG_WR(pDevice, Nvram.WriteData, value32);
1812
1813 pageoff = offset % pDevice->flashinfo.pagesize;
1814
1815 /* Set the target address. */
1816 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
1817 pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1818 {
1819 /*
1820 * If we're dealing with the special ATMEL part, we need to
1821 * convert the submitted offset before it can be considered
1822 * a physical address.
1823 */
1824 LM_UINT32 pagenmbr;
1825
1826 pagenmbr = offset / pDevice->flashinfo.pagesize;
1827 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
1828
1829 physaddr = pagenmbr + pageoff;
1830 }
1831 else
1832 {
1833 physaddr = offset;
1834 }
1835
1836 REG_WR(pDevice, Nvram.Addr, physaddr);
1837
1838 ctrlreg |= (NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR);
1839
1840 if( pageoff == 0 )
1841 {
1842 /* Set CMD_FIRST when we are at the beginning of a page. */
1843 ctrlreg |= NVRAM_CMD_FIRST;
1844 }
1845 else if( pageoff == (pDevice->flashinfo.pagesize - 4) )
1846 {
1847 /*
1848 * Enable the write to the current page
1849 * before moving on to the next one.
1850 */
1851 ctrlreg |= NVRAM_CMD_LAST;
1852 }
1853
1854 if( size == 0 )
1855 {
1856 ctrlreg |= NVRAM_CMD_LAST;
1857 }
1858
1859 if( pDevice->flashinfo.jedecnum == JEDEC_ST &&
1860 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) ||
1861 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714)) &&
1862 (ctrlreg & NVRAM_CMD_FIRST) )
1863 {
1864 LM_UINT32 wrencmd;
1865
1866 REG_WR(pDevice, Nvram.Write1, ST_M45PEX0_WRENA_CMD);
1867
1868 /* We need to issue a special "write enable" command first. */
1869 wrencmd = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1870
1871 status = LM_NVRAM_ExecuteCommand( pDevice, wrencmd );
1872 if( status == LM_STATUS_FAILURE )
1873 {
1874 return status;
1875 }
1876 }
1877
1878 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1879 {
1880 /* We always do complete word writes to eeprom. */
1881 ctrlreg |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
1882 }
1883
1884 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1885 if( status == LM_STATUS_FAILURE )
1886 {
1887 break;
1888 }
1889
1890 offset += sizeof(LM_UINT32);
1891 ctrlreg = 0;
1892 }
1893
1894 return status;
1895 } /* LM_NVRAM_WriteBlockBuffered */
1896
1897
1898
1899 /******************************************************************************/
1900 /* Description: */
1901 /* */
1902 /* Return: */
1903 /******************************************************************************/
1904 LM_STATUS LM_NVRAM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1905 LM_UINT8 * data, LM_UINT32 size )
1906 {
1907 LM_UINT32 value32;
1908 LM_STATUS status;
1909
1910 if( offset > pDevice->flashinfo.chipsize ||
1911 (offset + size) > pDevice->flashinfo.chipsize )
1912 {
1913 return LM_STATUS_FAILURE;
1914 }
1915
1916 if( size == 0 )
1917 {
1918 return LM_STATUS_SUCCESS;
1919 }
1920
1921 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1922 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1923 {
1924 status = LM_EEPROM_WriteBlock( pDevice, offset, data, size );
1925 }
1926 else
1927 {
1928 status = LM_NVRAM_AcquireLock( pDevice );
1929 if( status == LM_STATUS_FAILURE )
1930 {
1931 return status;
1932 }
1933
1934 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1935 {
1936 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1937 {
1938 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1939 value32 |= (NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1940 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1941 }
1942 }
1943
1944 /* Enable EEPROM write. */
1945 if( pDevice->Flags & EEPROM_WP_FLAG )
1946 {
1947 REG_WR(pDevice, Grc.LocalCtrl,
1948 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1);
1949 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1950 MM_Wait(40);
1951
1952 value32 = REG_RD(pDevice, Grc.LocalCtrl);
1953 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1954 {
1955 status = LM_STATUS_FAILURE;
1956 goto error;
1957 }
1958 }
1959
1960 value32 = REG_RD(pDevice, Grc.Mode);
1961 value32 |= GRC_MODE_NVRAM_WRITE_ENABLE;
1962 REG_WR(pDevice, Grc.Mode, value32);
1963
1964 if( pDevice->flashinfo.buffered == TRUE ||
1965 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1966 {
1967 status = LM_NVRAM_WriteBlockBuffered(pDevice, offset, data, size);
1968 }
1969 else
1970 {
1971 status = LM_NVRAM_WriteBlockUnBuffered(pDevice, offset, data, size);
1972 }
1973
1974 value32 = REG_RD(pDevice, Grc.Mode);
1975 value32 &= ~GRC_MODE_NVRAM_WRITE_ENABLE;
1976 REG_WR(pDevice, Grc.Mode, value32);
1977
1978 if( pDevice->Flags & EEPROM_WP_FLAG )
1979 {
1980 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1981 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1982 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1983 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1984 MM_Wait(40);
1985 }
1986
1987 error:
1988
1989 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1990 {
1991 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1992 {
1993 value32 = REG_RD(pDevice, Nvram.NvmAccess);
1994 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1995 REG_WR(pDevice, Nvram.NvmAccess, value32);
1996 }
1997 }
1998
1999 LM_NVRAM_ReleaseLock( pDevice );
2000 }
2001
2002 return status;
2003 } /* LM_NVRAM_WriteBlock */
2004
2005
2006 LM_STATUS LM_NvramWriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
2007 LM_UINT32 * data, LM_UINT32 size )
2008 {
2009 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
2010 if (pDevice->Flags & SB_CORE_FLAG)
2011 return LM_STATUS_FAILURE;
2012
2013 return LM_NVRAM_WriteBlock( pDevice, offset, (LM_UINT8 *)data, size * 4 );
2014 }
2015
2016 #endif /* ETHTOOL_SEEPROM */
2017
2018
2019 STATIC void
2020 LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
2021 {
2022 #ifdef BCM_PROC_FS
2023 LM_UINT32 Vpd_arr[256/4];
2024 LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
2025 LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
2026 LM_UINT32 Value32;
2027 unsigned int j;
2028
2029 /* Read PN from VPD */
2030 for (j = 0; j < 256; j += 4, Vpd_dptr++ )
2031 {
2032 if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
2033 B57_ERR(("VPD read failed\n"));
2034 return;
2035 }
2036 *Vpd_dptr = Value32;
2037 }
2038 for (j = 0; j < 256; )
2039 {
2040 unsigned int Vpd_r_len;
2041 unsigned int Vpd_r_end;
2042
2043 if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
2044 {
2045 j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
2046 }
2047 else if (Vpd[j] == 0x90)
2048 {
2049 Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
2050 j += 3;
2051 Vpd_r_end = Vpd_r_len + j;
2052 while (j < Vpd_r_end)
2053 {
2054 if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
2055 {
2056 unsigned int len = Vpd[j + 2];
2057
2058 if (len <= 24)
2059 {
2060 memcpy(pDevice->PartNo, &Vpd[j + 3], len);
2061 }
2062 break;
2063 }
2064 else
2065 {
2066 if (Vpd[j + 2] == 0)
2067 {
2068 break;
2069 }
2070 j = j + Vpd[j + 2];
2071 }
2072 }
2073 break;
2074 }
2075 else {
2076 break;
2077 }
2078 }
2079 #endif
2080 }
2081
2082 STATIC void
2083 LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
2084 {
2085 #ifdef BCM_PROC_FS
2086 LM_UINT32 Value32, offset, ver_offset, start_addr;
2087 int i;
2088
2089 if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
2090 return;
2091 Value32 = MM_SWAP_BE32(Value32);
2092 if (Value32 != 0x669955aa)
2093 return;
2094 if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
2095 return;
2096
2097 offset = MM_SWAP_BE32(offset);
2098
2099 if( (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2100 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2101 pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
2102 pDevice->flashinfo.buffered == TRUE )
2103 {
2104 LM_UINT32 highaddr;
2105
2106 highaddr = offset >> ATMEL_AT45DB0X1B_PAGE_POS;
2107 highaddr = highaddr * ATMEL_AT45DB0X1B_PAGE_SIZE;
2108
2109 offset = highaddr + (offset & ATMEL_AT45DB0X1B_PAGE_MASK);
2110 }
2111 if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
2112 return;
2113
2114 Value32 = MM_SWAP_BE32(Value32);
2115 Value32 &= 0xfc000000;
2116 if ((Value32 == 0x0c000000) &&
2117 (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
2118 (Value32 == 0)) {
2119
2120 if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2121 return;
2122 if (LM_NvramRead(pDevice, 4, &start_addr) != LM_STATUS_SUCCESS)
2123 return;
2124 ver_offset = MM_SWAP_BE32(ver_offset);
2125 start_addr = MM_SWAP_BE32(start_addr);
2126 offset += ver_offset - start_addr;
2127 for (i = 0; i < 16; i += 4) {
2128 if (LM_NvramRead(pDevice, offset + i, &Value32) !=
2129 LM_STATUS_SUCCESS)
2130 {
2131 return;
2132 }
2133 memcpy(&(pDevice->BootCodeVer[i]), &Value32, sizeof(Value32));
2134 }
2135 }
2136 else {
2137 char c;
2138
2139 if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
2140 return;
2141
2142 Value32 = MM_SWAP_BE32(Value32);
2143 i = 0;
2144 c = ((Value32 & 0xff00) >> 8);
2145
2146 if (c < 10) {
2147 pDevice->BootCodeVer[i++] = c + '0';
2148 }
2149 else {
2150 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2151 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2152 }
2153 pDevice->BootCodeVer[i++] = '.';
2154 c = Value32 & 0xff;
2155 if (c < 10) {
2156 pDevice->BootCodeVer[i++] = '0';
2157 pDevice->BootCodeVer[i++] = c + '0';
2158 }
2159 else {
2160 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2161 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2162 }
2163 pDevice->BootCodeVer[i] = 0;
2164 }
2165 #endif
2166 }
2167
2168 STATIC void
2169 LM_ReadIPMICodeVersion(PLM_DEVICE_BLOCK pDevice)
2170 {
2171 #ifdef BCM_PROC_FS
2172 static char * present = "BRCM ASF present";
2173 LM_UINT32 sig1, sig2;
2174 LM_UINT32 value32, offset, asf_offset, ver_offset, start_addr;
2175 int i;
2176
2177 if (LM_NvramRead(pDevice, 0x0, &value32) != LM_STATUS_SUCCESS)
2178 return;
2179 value32 = MM_SWAP_BE32(value32);
2180 if (value32 != 0x669955aa)
2181 return;
2182
2183 offset = 0x14 + 4;
2184 for (i = 0; i < 8; i++) {
2185 if (LM_NvramRead(pDevice, offset, &value32) != LM_STATUS_SUCCESS)
2186 return;
2187 value32 = MM_SWAP_BE32(value32) & 0xff000000;
2188 if (value32 == 0x1000000)
2189 break;
2190 offset += 12;
2191 }
2192
2193 if (i == 8)
2194 return;
2195
2196 if (LM_NvramRead(pDevice, 0x14 + i * 12, &start_addr) != LM_STATUS_SUCCESS)
2197 return;
2198
2199 start_addr = MM_SWAP_BE32(start_addr);
2200
2201 if (start_addr == 0xc0034000)
2202 start_addr = 0x08000000;
2203
2204 if (LM_NvramRead(pDevice, 0x14 + i * 12 + 8, &asf_offset) != LM_STATUS_SUCCESS)
2205 return;
2206
2207 asf_offset = MM_SWAP_BE32(asf_offset);
2208
2209 if (LM_NvramRead(pDevice, asf_offset, &sig1) != LM_STATUS_SUCCESS ||
2210 LM_NvramRead(pDevice, asf_offset + 4, &sig2) != LM_STATUS_SUCCESS )
2211 return;
2212
2213 sig1 = MM_SWAP_BE32(sig1);
2214
2215 if ((sig1 & 0xfc000000) != 0x0c000000 || sig2 != 0 ) {
2216 memcpy(pDevice->IPMICodeVer, present, 17);
2217 return;
2218 }
2219
2220 if (LM_NvramRead(pDevice, asf_offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2221 return;
2222
2223 ver_offset = MM_SWAP_BE32(ver_offset);
2224
2225 ver_offset -= start_addr;
2226 ver_offset += asf_offset;
2227
2228 for (i = 0; i < 16; i += 4) {
2229 if (LM_NvramRead(pDevice, ver_offset + i, &value32) != LM_STATUS_SUCCESS)
2230 return;
2231 memcpy(&(pDevice->IPMICodeVer[i]), &value32, sizeof(value32));
2232 }
2233 #endif
2234 }
2235
2236 STATIC void
2237 LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
2238 {
2239 #ifdef BCM_PROC_FS
2240 LM_UINT32 PciState = pDevice->PciState;
2241 LM_UINT32 ClockCtrl;
2242 char *SpeedStr = "";
2243
2244 if (pDevice->Flags & PCI_EXPRESS_FLAG)
2245 {
2246 strcpy(pDevice->BusSpeedStr, "PCI Express");
2247 return;
2248 }
2249 if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
2250 {
2251 strcpy(pDevice->BusSpeedStr, "32-bit ");
2252 }
2253 else
2254 {
2255 strcpy(pDevice->BusSpeedStr, "64-bit ");
2256 }
2257 if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
2258 {
2259 strcat(pDevice->BusSpeedStr, "PCI ");
2260 if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
2261 {
2262 SpeedStr = "66MHz";
2263 }
2264 else
2265 {
2266 SpeedStr = "33MHz";
2267 }
2268 }
2269 else
2270 {
2271 strcat(pDevice->BusSpeedStr, "PCIX ");
2272
2273 // Theses devices have internal PCI-X buses. The driver
2274 // is unable to use the ClockCtrl register to determine the
2275 // bus speed, so we just hardcode the bus speed to 133MHz.
2276
2277 if ( ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
2278 (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) ||
2279 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)))
2280 {
2281 SpeedStr = "133MHz";
2282 }
2283 else
2284 {
2285 ClockCtrl = pDevice->ClockCtrl & 0x1f;
2286 switch (ClockCtrl)
2287 {
2288 case 0:
2289 SpeedStr = "33MHz";
2290 break;
2291
2292 case 2:
2293 SpeedStr = "50MHz";
2294 break;
2295
2296 case 4:
2297 SpeedStr = "66MHz";
2298 break;
2299
2300 case 6:
2301 SpeedStr = "100MHz";
2302 break;
2303
2304 case 7:
2305 SpeedStr = "133MHz";
2306 break;
2307 }
2308 }
2309 }
2310 strcat(pDevice->BusSpeedStr, SpeedStr);
2311 #endif
2312 }
2313
2314 /******************************************************************************/
2315 /* Description: */
2316 /* This routine initializes default parameters and reads the PCI */
2317 /* configurations. */
2318 /* */
2319 /* Return: */
2320 /* LM_STATUS_SUCCESS */
2321 /******************************************************************************/
2322 LM_STATUS
2323 LM_GetAdapterInfo(
2324 PLM_DEVICE_BLOCK pDevice)
2325 {
2326 PLM_ADAPTER_INFO pAdapterInfo;
2327 LM_UINT32 Value32, LedCfg, Ver;
2328 LM_STATUS Status;
2329 LM_UINT32 EeSigFound;
2330 LM_UINT32 EePhyTypeSerdes = 0;
2331 LM_UINT32 EePhyId = 0;
2332
2333 /* Get Device Id and Vendor Id */
2334 Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
2335 if(Status != LM_STATUS_SUCCESS)
2336 {
2337 return Status;
2338 }
2339 pDevice->PciVendorId = (LM_UINT16) Value32;
2340 pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
2341
2342 Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
2343 if(Status != LM_STATUS_SUCCESS)
2344 {
2345 return Status;
2346 }
2347 pDevice->PciRevId = (LM_UINT8) Value32;
2348
2349 /* Get chip revision id. */
2350 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2351 pDevice->ChipRevId = Value32 >> 16;
2352
2353 /* determine if it is PCIE system */
2354 if( (Value32 = MM_FindCapability(pDevice, T3_PCIE_CAPABILITY_ID)) != 0)
2355 {
2356 pDevice->Flags |= PCI_EXPRESS_FLAG;
2357 }
2358
2359 /* Get subsystem vendor. */
2360 Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
2361 if(Status != LM_STATUS_SUCCESS)
2362 {
2363 return Status;
2364 }
2365 pDevice->SubsystemVendorId = (LM_UINT16) Value32;
2366
2367 /* Get PCI subsystem id. */
2368 pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
2369
2370 /* Read bond id for baxter A0 since it has same rev id as hamilton A0*/
2371
2372 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714_A0) {
2373 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 | MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2374
2375 Value32 = LM_RegRdInd(pDevice, 0x6804);
2376 Value32 &= GRC_MISC_BD_ID_MASK;
2377
2378 if((Value32 == 0)||(Value32 == 0x8000)) {
2379 pDevice->ChipRevId = T3_CHIP_ID_5752_A0;
2380 }else{
2381 pDevice->ChipRevId = T3_CHIP_ID_5714_A0;
2382 }
2383
2384 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2385 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 & ~ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2386 }
2387
2388
2389 /* Get the cache line size. */
2390 MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
2391 pDevice->CacheLineSize = (LM_UINT8) Value32;
2392 pDevice->SavedCacheLineReg = Value32;
2393
2394 if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
2395 pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
2396 pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
2397 {
2398 pDevice->Flags &= ~UNDI_FIX_FLAG;
2399 }
2400 #ifndef PCIX_TARGET_WORKAROUND
2401 pDevice->Flags &= ~UNDI_FIX_FLAG;
2402 #endif
2403 /* Map the memory base to system address space. */
2404 if (!(pDevice->Flags & UNDI_FIX_FLAG))
2405 {
2406 Status = MM_MapMemBase(pDevice);
2407 if(Status != LM_STATUS_SUCCESS)
2408 {
2409 return Status;
2410 }
2411 /* Initialize the memory view pointer. */
2412 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
2413 }
2414
2415 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) ||
2416 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2417 {
2418 pDevice->Flags |= TX_4G_WORKAROUND_FLAG;
2419 }
2420 if ( (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
2421 (pDevice->Flags == PCI_EXPRESS_FLAG))
2422 {
2423 pDevice->Flags |= REG_RD_BACK_FLAG;
2424 }
2425
2426 if(pDevice->ChipRevId==T3_CHIP_ID_5750_A0)
2427 return LM_STATUS_UNKNOWN_ADAPTER;
2428
2429 #ifdef PCIX_TARGET_WORKAROUND
2430 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2431 if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
2432 {
2433 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
2434 {
2435 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2436 }
2437 }
2438 if (pDevice->Flags & UNDI_FIX_FLAG)
2439 {
2440 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2441 }
2442 #endif
2443 /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
2444 /* management register may be clobbered which may cause the */
2445 /* BCM5700 to go into D3 state. While in this state, we will */
2446 /* need to restore the device to D0 state. */
2447 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
2448 Value32 |= T3_PM_PME_ASSERTED;
2449 Value32 &= ~T3_PM_POWER_STATE_MASK;
2450 Value32 |= T3_PM_POWER_STATE_D0;
2451 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
2452
2453 /* read the current PCI command word */
2454 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
2455
2456 /* Make sure bus-mastering is enabled. */
2457 Value32 |= PCI_BUSMASTER_ENABLE;
2458
2459 #ifdef PCIX_TARGET_WORKAROUND
2460 /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
2461 are enabled */
2462 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) {
2463 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
2464 PCI_PARITY_ERROR_ENABLE);
2465 }
2466 if (pDevice->Flags & UNDI_FIX_FLAG)
2467 {
2468 Value32 &= ~PCI_MEM_SPACE_ENABLE;
2469 }
2470
2471 #endif
2472
2473 if (pDevice->Flags & ENABLE_MWI_FLAG)
2474 {
2475 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
2476 }
2477 else {
2478 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
2479 }
2480
2481 /* save the value we are going to write into the PCI command word */
2482 pDevice->PciCommandStatusWords = Value32;
2483
2484 Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
2485 if(Status != LM_STATUS_SUCCESS)
2486 {
2487 return Status;
2488 }
2489
2490 /* Setup the mode registers. */
2491 pDevice->MiscHostCtrl =
2492 MISC_HOST_CTRL_MASK_PCI_INT |
2493 MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
2494 #ifdef BIG_ENDIAN_HOST
2495 MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
2496 #endif /* BIG_ENDIAN_HOST */
2497 MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
2498 MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
2499 /* write to PCI misc host ctr first in order to enable indirect accesses */
2500 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
2501
2502 /* Set power state to D0. */
2503 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
2504
2505 /* Preserve HOST_STACK_UP bit in case ASF firmware is running */
2506 Value32 = REG_RD(pDevice, Grc.Mode) & GRC_MODE_HOST_STACK_UP;
2507 #ifdef BIG_ENDIAN_HOST
2508 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2509 GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
2510 #else
2511 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
2512 #endif
2513 REG_WR(pDevice, Grc.Mode, Value32);
2514
2515 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
2516 {
2517 REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
2518 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
2519 REG_RD_BACK(pDevice, Grc.LocalCtrl);
2520 }
2521 MM_Wait(40);
2522
2523 /* Enable memory arbiter*/
2524 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
2525 {
2526 Value32 = REG_RD(pDevice,MemArbiter.Mode);
2527 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
2528 }
2529 else
2530 {
2531 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
2532 }
2533
2534
2535 LM_SwitchClocks(pDevice);
2536
2537 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
2538
2539 /* Check to see if PXE ran and did not shutdown properly */
2540 if ((REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE) ||
2541 !(REG_RD(pDevice, PciCfg.MiscHostCtrl) & MISC_HOST_CTRL_MASK_PCI_INT))
2542 {
2543 LM_DisableInterrupt(pDevice);
2544 /* assume ASF is enabled */
2545 pDevice->AsfFlags = ASF_ENABLED;
2546 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2547 {
2548 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2549 }
2550 LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET);
2551 pDevice->AsfFlags = 0;
2552 }
2553 #ifdef PCIX_TARGET_WORKAROUND
2554 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2555 if (!(pDevice->Flags & ENABLE_PCIX_FIX_FLAG) &&
2556 ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
2557 {
2558 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
2559 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
2560 pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
2561 pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
2562 {
2563 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]), 0);
2564 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), 0);
2565 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]),
2566 0xffffffff);
2567 if (MM_MEMREADL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
2568 {
2569 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2570 }
2571 }
2572 }
2573 #endif
2574
2575 LM_NVRAM_Init(pDevice);
2576
2577 Status = LM_STATUS_FAILURE;
2578
2579 /* BCM4785: Use the MAC address stored in the main flash. */
2580 if (pDevice->Flags & SB_CORE_FLAG) {
2581 bcm_ether_atoe(getvar(NULL, "et0macaddr"), (struct ether_addr *)pDevice->NodeAddress);
2582 Status = LM_STATUS_SUCCESS;
2583 } else {
2584 /* Get the node address. First try to get in from the shared memory. */
2585 /* If the signature is not present, then get it from the NVRAM. */
2586 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
2587 if((Value32 >> 16) == 0x484b)
2588 {
2589 int i;
2590
2591 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
2592 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
2593
2594 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
2595
2596 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
2597 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
2598 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
2599 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
2600
2601 /* Check for null MAC address which can happen with older boot code */
2602 for (i = 0; i < 6; i++)
2603 {
2604 if (pDevice->NodeAddress[i] != 0)
2605 {
2606 Status = LM_STATUS_SUCCESS;
2607 break;
2608 }
2609 }
2610 }
2611 }
2612
2613 if (Status != LM_STATUS_SUCCESS)
2614 {
2615 int MacOffset;
2616
2617 MacOffset = 0x7c;
2618 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
2619 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)) )
2620 {
2621 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
2622 {
2623 MacOffset = 0xcc;
2624 }
2625 /* the boot code is not running */
2626 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS)
2627 {
2628 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
2629 }
2630 else
2631 {
2632 LM_NVRAM_ReleaseLock(pDevice);
2633 }
2634 }
2635
2636 Status = LM_NvramRead(pDevice, MacOffset, &Value32);
2637 if(Status == LM_STATUS_SUCCESS)
2638 {
2639 LM_UINT8 *c = (LM_UINT8 *) &Value32;
2640
2641 pDevice->NodeAddress[0] = c[2];
2642 pDevice->NodeAddress[1] = c[3];
2643
2644 Status = LM_NvramRead(pDevice, MacOffset + 4, &Value32);
2645
2646 c = (LM_UINT8 *) &Value32;
2647 pDevice->NodeAddress[2] = c[0];
2648 pDevice->NodeAddress[3] = c[1];
2649 pDevice->NodeAddress[4] = c[2];
2650 pDevice->NodeAddress[5] = c[3];
2651 }
2652 }
2653
2654 if(Status != LM_STATUS_SUCCESS)
2655 {
2656 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].High);
2657 pDevice->NodeAddress[0] = (Value32 >> 8) & 0xff;
2658 pDevice->NodeAddress[1] = Value32 & 0xff;
2659 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].Low);
2660 pDevice->NodeAddress[2] = (Value32 >> 24) & 0xff;
2661 pDevice->NodeAddress[3] = (Value32 >> 16) & 0xff;
2662 pDevice->NodeAddress[4] = (Value32 >> 8) & 0xff;
2663 pDevice->NodeAddress[5] = Value32 & 0xff;
2664 B57_ERR(("WARNING: Cannot get MAC addr from NVRAM, using %2.2x%2.2x%2.2x%2.2x%2.2x%2.2x\n",
2665 pDevice->NodeAddress[0], pDevice->NodeAddress[1],
2666 pDevice->NodeAddress[2], pDevice->NodeAddress[3],
2667 pDevice->NodeAddress[4], pDevice->NodeAddress[5]));
2668 }
2669
2670 memcpy(pDevice->PermanentNodeAddress, pDevice->NodeAddress, 6);
2671
2672 /* Initialize the default values. */
2673 pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
2674 pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
2675 pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
2676 pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
2677 pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
2678 pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
2679 pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2680 pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2681 pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2682 pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2683 pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
2684 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2685 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2686 pDevice->DisableAutoNeg = FALSE;
2687 pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
2688 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
2689
2690 pDevice->PhyFlags = 0;
2691
2692 if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
2693 pDevice->Flags |= DELAY_PCI_GRANT_FLAG;
2694
2695 pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO;
2696 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
2697 pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
2698 pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
2699 #ifdef INCLUDE_TBI_SUPPORT
2700 pDevice->TbiFlags = 0;
2701 pDevice->IgnoreTbiLinkChange = FALSE;
2702 #endif
2703 #ifdef INCLUDE_TCP_SEG_SUPPORT
2704 pDevice->LargeSendMaxSize = T3_TCP_SEG_MAX_OFFLOAD_SIZE;
2705 pDevice->LargeSendMinNumSeg = T3_TCP_SEG_MIN_NUM_SEG;
2706 #endif
2707
2708 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2709 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2710 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
2711 {
2712 pDevice->PhyFlags |= PHY_RESET_ON_LINKDOWN;
2713 pDevice->PhyFlags |= PHY_CHECK_TAPS_AFTER_RESET;
2714 }
2715 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5703_AX) ||
2716 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2717 {
2718 pDevice->PhyFlags |= PHY_ADC_FIX;
2719 }
2720 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
2721 {
2722 pDevice->PhyFlags |= PHY_5704_A0_FIX;
2723 }
2724 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
2725 {
2726 pDevice->PhyFlags |= PHY_5705_5750_FIX;
2727 }
2728 /* Ethernet@Wirespeed is supported on 5701,5702,5703,5704,5705a0,5705a1 */
2729 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2730 !((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
2731 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0) &&
2732 (pDevice->ChipRevId != T3_CHIP_ID_5705_A1)))
2733 {
2734 pDevice->PhyFlags |= PHY_ETHERNET_WIRESPEED;
2735 }
2736
2737 switch (T3_ASIC_REV(pDevice->ChipRevId))
2738 {
2739 case T3_ASIC_REV_5704:
2740 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2741 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
2742 break;
2743 default:
2744 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2745 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
2746 break;
2747 }
2748
2749 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
2750 pDevice->QueueRxPackets = TRUE;
2751
2752 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2753
2754 if(T3_ASIC_IS_JUMBO_CAPABLE(pDevice->ChipRevId)){
2755 if( ! T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
2756 pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
2757 pDevice->Flags |= JUMBO_CAPABLE_FLAG;
2758 }
2759
2760 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2761
2762 pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
2763
2764 if(((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
2765 ((pDevice->BondId == 0x10000) || (pDevice->BondId == 0x18000))) ||
2766 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) &&
2767 ((pDevice->BondId == 0x14000) || (pDevice->BondId == 0x1c000))))
2768 {
2769 return LM_STATUS_UNKNOWN_ADAPTER;
2770 }
2771 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
2772 {
2773 if ((pDevice->BondId == 0x8000) || (pDevice->BondId == 0x4000))
2774 {
2775 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2776 }
2777 }
2778 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
2779 {
2780 if ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
2781 (pDevice->BondId == GRC_MISC_BD_ID_5788M))
2782 {
2783 pDevice->Flags |= BCM5788_FLAG;
2784 }
2785
2786 if ((pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901)) ||
2787 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901A2)) ||
2788 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5705F)))
2789 {
2790 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2791 }
2792 }
2793
2794 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750)
2795 {
2796 if ( (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5751F))||
2797 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5753F)))
2798 {
2799 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2800 }
2801 }
2802
2803 /* CIOBE multisplit has a bug */
2804
2805 /* Get Eeprom info. */
2806 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
2807 if (Value32 == T3_NIC_DATA_SIG)
2808 {
2809 EeSigFound = TRUE;
2810 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
2811
2812 /* For now the 5753 cannot drive gpio2 or ASF will blow */
2813 if(Value32 & T3_NIC_GPIO2_NOT_AVAILABLE)
2814 {
2815 pDevice->Flags |= GPIO2_DONOT_OUTPUT;
2816 }
2817
2818 if (Value32 & T3_NIC_MINI_PCI)
2819 {
2820 pDevice->Flags |= MINI_PCI_FLAG;
2821 }
2822 /* Determine PHY type. */
2823 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
2824 {
2825 case T3_NIC_CFG_PHY_TYPE_COPPER:
2826 EePhyTypeSerdes = FALSE;
2827 break;
2828
2829 case T3_NIC_CFG_PHY_TYPE_FIBER:
2830 EePhyTypeSerdes = TRUE;
2831 break;
2832
2833 default:
2834 EePhyTypeSerdes = FALSE;
2835 break;
2836 }
2837
2838 if ( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2839 {
2840 LedCfg = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2841 LedCfg = LedCfg & (T3_NIC_CFG_LED_MODE_MASK |
2842 T3_SHASTA_EXT_LED_MODE_MASK);
2843 }
2844 else
2845 {
2846 /* Determine PHY led mode. for legacy devices */
2847 LedCfg = Value32 & T3_NIC_CFG_LED_MODE_MASK;
2848 }
2849
2850 switch (LedCfg)
2851 {
2852 default:
2853 case T3_NIC_CFG_LED_PHY_MODE_1:
2854 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
2855 break;
2856
2857 case T3_NIC_CFG_LED_PHY_MODE_2:
2858 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2859 break;
2860
2861 case T3_NIC_CFG_LED_MAC_MODE:
2862 pDevice->LedCtrl = LED_CTRL_MAC_MODE;
2863 break;
2864
2865 case T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE:
2866 pDevice->LedCtrl = LED_CTRL_SHARED_TRAFFIC_LINK;
2867 if ((pDevice->ChipRevId != T3_CHIP_ID_5750_A0) &&
2868 (pDevice->ChipRevId != T3_CHIP_ID_5750_A1))
2869 {
2870 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2871 LED_CTRL_PHY_MODE_2;
2872 }
2873 break;
2874
2875 case T3_SHASTA_EXT_LED_MAC_MODE:
2876 pDevice->LedCtrl = LED_CTRL_SHASTA_MAC_MODE;
2877 break;
2878
2879 case T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE:
2880 pDevice->LedCtrl = LED_CTRL_WIRELESS_COMBO;
2881 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
2882 {
2883 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2884 LED_CTRL_PHY_MODE_2;
2885 }
2886 break;
2887
2888 }
2889
2890 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2891 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)) &&
2892 (pDevice->SubsystemVendorId == T3_SVID_DELL))
2893 {
2894 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2895 }
2896
2897 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2898 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2899 (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId)) )
2900 {
2901 /* Enable EEPROM write protection. */
2902 if(Value32 & T3_NIC_EEPROM_WP)
2903 {
2904 pDevice->Flags |= EEPROM_WP_FLAG;
2905 }
2906 }
2907 pDevice->AsfFlags = 0;
2908 #ifdef BCM_ASF
2909 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
2910 {
2911 pDevice->AsfFlags |= ASF_ENABLED;
2912 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2913 {
2914 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2915 }
2916 }
2917 #endif
2918 if (Value32 & T3_NIC_FIBER_WOL_CAPABLE)
2919 {
2920 pDevice->Flags |= FIBER_WOL_CAPABLE_FLAG;
2921 }
2922 if (Value32 & T3_NIC_WOL_LIMIT_10)
2923 {
2924 pDevice->Flags |= WOL_LIMIT_10MBPS_FLAG;
2925 }
2926
2927 /* Get the PHY Id. */
2928 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
2929 if (Value32)
2930 {
2931 EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
2932 PHY_ID1_OUI_MASK) << 10;
2933
2934 Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
2935
2936 EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
2937 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
2938 }
2939 else
2940 {
2941 EePhyId = 0;
2942 if (!EePhyTypeSerdes && !(pDevice->AsfFlags & ASF_ENABLED))
2943 {
2944 /* reset PHY if boot code couldn't read the PHY ID */
2945 LM_ResetPhy(pDevice);
2946 }
2947 }
2948
2949 Ver = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_VER);
2950 Ver >>= T3_NIC_DATA_VER_SHIFT;
2951
2952 Value32 = 0;
2953 if((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2954 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2955 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703) &&
2956 (Ver > 0) && (Ver < 0x100)){
2957
2958 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2959
2960 if (Value32 & T3_NIC_CFG_CAPACITIVE_COUPLING)
2961 {
2962 pDevice->PhyFlags |= PHY_CAPACITIVE_COUPLING;
2963 }
2964
2965 if (Value32 & T3_NIC_CFG_PRESERVE_PREEMPHASIS)
2966 {
2967 pDevice->TbiFlags |= TBI_DO_PREEMPHASIS;
2968 }
2969
2970 }
2971
2972 }
2973 else
2974 {
2975 EeSigFound = FALSE;
2976 }
2977
2978 /* Set the PHY address. */
2979 pDevice->PhyAddr = PHY_DEVICE_ID;
2980
2981 /* Disable auto polling. */
2982 pDevice->MiMode = 0xc0000;
2983 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
2984 REG_RD_BACK(pDevice, MacCtrl.MiMode);
2985 MM_Wait(80);
2986
2987 if (pDevice->AsfFlags & ASF_ENABLED)
2988 {
2989 /* Reading PHY registers will contend with ASF */
2990 pDevice->PhyId = 0;
2991 }
2992 else
2993 {
2994 /* Get the PHY id. */
2995 LM_GetPhyId(pDevice);
2996 }
2997
2998 /* Set the EnableTbi flag to false if we have a copper PHY. */
2999 switch(pDevice->PhyId & PHY_ID_MASK)
3000 {
3001 case PHY_BCM5400_PHY_ID:
3002 case PHY_BCM5401_PHY_ID:
3003 case PHY_BCM5411_PHY_ID:
3004 case PHY_BCM5461_PHY_ID:
3005 case PHY_BCM5701_PHY_ID:
3006 case PHY_BCM5703_PHY_ID:
3007 case PHY_BCM5704_PHY_ID:
3008 case PHY_BCM5705_PHY_ID:
3009 case PHY_BCM5750_PHY_ID:
3010 break;
3011 case PHY_BCM5714_PHY_ID:
3012 case PHY_BCM5780_PHY_ID:
3013 if(EePhyTypeSerdes == TRUE)
3014 {
3015 pDevice->PhyFlags |= PHY_IS_FIBER;
3016 }
3017 break;
3018 case PHY_BCM5752_PHY_ID:
3019 break;
3020
3021 case PHY_BCM8002_PHY_ID:
3022 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3023 break;
3024
3025 default:
3026
3027 if (EeSigFound)
3028 {
3029 pDevice->PhyId = EePhyId;
3030
3031 if (EePhyTypeSerdes && ((pDevice->PhyId == PHY_BCM5780_PHY_ID)) )
3032 {
3033 pDevice->PhyFlags |= PHY_IS_FIBER;
3034 }
3035 else if (EePhyTypeSerdes)
3036 {
3037 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3038 }
3039 }
3040 else if ((pAdapterInfo = LM_GetAdapterInfoBySsid(
3041 pDevice->SubsystemVendorId,
3042 pDevice->SubsystemId)))
3043 {
3044 pDevice->PhyId = pAdapterInfo->PhyId;
3045 if (pAdapterInfo->Serdes)
3046 {
3047 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3048 }
3049 }
3050 else
3051 {
3052 if (UNKNOWN_PHY_ID(pDevice->PhyId))
3053 {
3054 LM_ResetPhy(pDevice);
3055 LM_GetPhyId(pDevice);
3056 }
3057 }
3058 break;
3059 }
3060
3061 if(UNKNOWN_PHY_ID(pDevice->PhyId) &&
3062 !(pDevice->TbiFlags & ENABLE_TBI_FLAG))
3063 {
3064 if (pDevice->Flags & ROBO_SWITCH_FLAG) {
3065 B57_ERR(("PHY ID unknown, assume it is a copper PHY.\n"));
3066 } else {
3067 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3068 B57_ERR(("PHY ID unknown, assume it is SerDes\n"));
3069 }
3070 }
3071
3072 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3073 {
3074 if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
3075 {
3076 pDevice->SavedCacheLineReg &= 0xffff00ff;
3077 pDevice->SavedCacheLineReg |= 0x4000;
3078 }
3079 }
3080
3081 pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3082 LM_ACCEPT_UNICAST;
3083
3084 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3085 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM | LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
3086 LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
3087
3088 if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
3089 {
3090 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3091 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
3092 }
3093
3094 #ifdef INCLUDE_TCP_SEG_SUPPORT
3095 pDevice->TaskOffloadCap |= LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3096
3097 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3098 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3099 (pDevice->ChipRevId == T3_CHIP_ID_5705_A0))
3100 {
3101 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3102 }
3103 #endif
3104
3105 #ifdef BCM_ASF
3106 if (pDevice->AsfFlags & ASF_ENABLED)
3107 {
3108 if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
3109 {
3110 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3111 }
3112 }
3113 #endif
3114
3115 /* Change driver parameters. */
3116 Status = MM_GetConfig(pDevice);
3117 if(Status != LM_STATUS_SUCCESS)
3118 {
3119 return Status;
3120 }
3121
3122 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3123 {
3124 pDevice->Flags &= ~NIC_SEND_BD_FLAG;
3125 }
3126
3127 /* Save the current phy link status. */
3128 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3129 !(pDevice->AsfFlags & ASF_ENABLED))
3130 {
3131 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3132 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3133
3134 /* If we don't have link reset the PHY. */
3135 if(!(Value32 & PHY_STATUS_LINK_PASS) ||
3136 (pDevice->PhyFlags & PHY_RESET_ON_INIT))
3137 {
3138
3139 LM_ResetPhy(pDevice);
3140
3141 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
3142 {
3143 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
3144 PHY_AN_AD_ALL_SPEEDS;
3145 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
3146 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
3147
3148 if(!(pDevice->PhyFlags & PHY_NO_GIGABIT))
3149 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS ;
3150 else
3151 Value32 =0;
3152
3153 #ifdef INCLUDE_5701_AX_FIX
3154 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3155 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
3156 {
3157 Value32 |= BCM540X_CONFIG_AS_MASTER |
3158 BCM540X_ENABLE_CONFIG_AS_MASTER;
3159 }
3160 #endif
3161 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
3162
3163 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
3164 PHY_CTRL_RESTART_AUTO_NEG);
3165 }
3166
3167 }
3168 LM_SetEthWireSpeed(pDevice);
3169
3170 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &pDevice->advertising);
3171 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG,
3172 &pDevice->advertising1000);
3173
3174 }
3175 /* Currently 5401 phy only */
3176 LM_PhyTapPowerMgmt(pDevice);
3177
3178 #ifdef INCLUDE_TBI_SUPPORT
3179 if(pDevice->TbiFlags & ENABLE_TBI_FLAG)
3180 {
3181 if (!(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG))
3182 {
3183 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
3184 }
3185 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3186 if (pDevice->TbiFlags & TBI_PURE_POLLING_FLAG)
3187 {
3188 pDevice->IgnoreTbiLinkChange = TRUE;
3189 }
3190 }
3191 else
3192 {
3193 pDevice->TbiFlags = 0;
3194 }
3195
3196 #endif /* INCLUDE_TBI_SUPPORT */
3197
3198 /* UseTaggedStatus is only valid for 5701 and later. */
3199 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3200 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3201 ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
3202 (pDevice->BondId == GRC_MISC_BD_ID_5788M))))
3203 {
3204 pDevice->Flags &= ~USE_TAGGED_STATUS_FLAG;
3205 pDevice->CoalesceMode = 0;
3206 }
3207 else
3208 {
3209 pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
3210 HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
3211 }
3212
3213 /* Set the status block size. */
3214 if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
3215 T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
3216 {
3217 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
3218 }
3219
3220 /* Check the DURING_INT coalescing ticks parameters. */
3221 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
3222 {
3223 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3224 {
3225 pDevice->RxCoalescingTicksDuringInt =
3226 DEFAULT_RX_COALESCING_TICKS_DURING_INT;
3227 }
3228
3229 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3230 {
3231 pDevice->TxCoalescingTicksDuringInt =
3232 DEFAULT_TX_COALESCING_TICKS_DURING_INT;
3233 }
3234
3235 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3236 {
3237 pDevice->RxMaxCoalescedFramesDuringInt =
3238 DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
3239 }
3240
3241 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3242 {
3243 pDevice->TxMaxCoalescedFramesDuringInt =
3244 DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
3245 }
3246 }
3247 else
3248 {
3249 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3250 {
3251 pDevice->RxCoalescingTicksDuringInt = 0;
3252 }
3253
3254 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3255 {
3256 pDevice->TxCoalescingTicksDuringInt = 0;
3257 }
3258
3259 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3260 {
3261 pDevice->RxMaxCoalescedFramesDuringInt = 0;
3262 }
3263
3264 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3265 {
3266 pDevice->TxMaxCoalescedFramesDuringInt = 0;
3267 }
3268 }
3269
3270 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3271 if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
3272 {
3273 pDevice->RxJumboDescCnt = 0;
3274 if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3275 {
3276 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3277 }
3278 }
3279 else if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
3280 {
3281 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3282 pDevice->RxJumboDescCnt = 0;
3283 }
3284 else
3285 {
3286 pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
3287 COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
3288
3289 if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
3290 {
3291 pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
3292 pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
3293 }
3294 pDevice->TxMtu = pDevice->RxMtu;
3295 }
3296 #else
3297 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3298 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3299
3300 pDevice->RxPacketDescCnt =
3301 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3302 pDevice->RxJumboDescCnt +
3303 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3304 pDevice->RxStdDescCnt;
3305
3306 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3307 {
3308 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3309 }
3310
3311 if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
3312 {
3313 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
3314 }
3315
3316 /* Configure the proper ways to get link change interrupt. */
3317 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
3318 {
3319 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3320 {
3321 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3322 }
3323 else
3324 {
3325 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3326 }
3327 }
3328 else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
3329 {
3330 /* Auto-polling does not work on 5700_AX and 5700_BX. */
3331 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3332 {
3333 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3334 }
3335 }
3336
3337 /* Determine the method to get link change status. */
3338 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
3339 {
3340 /* The link status bit in the status block does not work on 5700_AX */
3341 /* and 5700_BX chips. */
3342 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3343 {
3344 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3345 }
3346 else
3347 {
3348 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
3349 }
3350 }
3351
3352 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
3353 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3354 {
3355 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3356 }
3357
3358 if (!EeSigFound)
3359 {
3360 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3361 }
3362
3363 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3364 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
3365 {
3366 /* bug? 5701 in LINK10 mode does not seem to work when */
3367 /* PhyIntMode is LINK_READY. */
3368 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
3369 #ifdef INCLUDE_TBI_SUPPORT
3370 !(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3371 #endif
3372 pDevice->LedCtrl == LED_CTRL_PHY_MODE_2)
3373 {
3374 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3375 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3376 }
3377 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
3378 {
3379 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3380 }
3381 }
3382
3383 #ifdef BCM_WOL
3384 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3385 pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3386 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
3387 pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
3388 {
3389 pDevice->WolSpeed = WOL_SPEED_10MB;
3390 }
3391 else
3392 {
3393 if (pDevice->Flags & WOL_LIMIT_10MBPS_FLAG)
3394 {
3395 pDevice->WolSpeed = WOL_SPEED_10MB;
3396 }
3397 else
3398 {
3399 pDevice->WolSpeed = WOL_SPEED_100MB;
3400 }
3401 }
3402 #endif
3403
3404 pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
3405
3406 pDevice->DmaReadFifoSize = 0;
3407 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3408 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0)) ||
3409 T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) )
3410 {
3411 #ifdef INCLUDE_TCP_SEG_SUPPORT
3412 if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) &&
3413 ((pDevice->ChipRevId == T3_CHIP_ID_5705_A1) ||
3414 (pDevice->ChipRevId == T3_CHIP_ID_5705_A2)))
3415 {
3416 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_SIZE_128;
3417 }
3418 else
3419 #endif
3420 {
3421 if (!(pDevice->PciState & T3_PCI_STATE_HIGH_BUS_SPEED) &&
3422 !(pDevice->Flags & BCM5788_FLAG) &&
3423 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3424 {
3425 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3426 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A1)
3427 {
3428 pDevice->Flags |= RX_BD_LIMIT_64_FLAG;
3429 }
3430 pDevice->Flags |= DMA_WR_MODE_RX_ACCELERATE_FLAG;
3431 }
3432 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3433 {
3434 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3435 }
3436 }
3437 }
3438
3439 pDevice->Flags &= ~T3_HAS_TWO_CPUS;
3440 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3441 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
3442 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
3443 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3444 {
3445 pDevice->Flags |= T3_HAS_TWO_CPUS;
3446 }
3447
3448 /*
3449 * BCM4785: In general, various information is read from NVRAM,
3450 * including vital product data, version info, and other goodies.
3451 *
3452 * In the case of the BCM4785, access to external EEPROM is
3453 * avoided, so these calls are skipped.
3454 */
3455 if (!pDevice->Flags & SB_CORE_FLAG) {
3456 LM_ReadVPD(pDevice);
3457 LM_ReadBootCodeVersion(pDevice);
3458 LM_ReadIPMICodeVersion(pDevice);
3459 LM_GetBusSpeed(pDevice);
3460 }
3461
3462 return LM_STATUS_SUCCESS;
3463 } /* LM_GetAdapterInfo */
3464
3465 STATIC PLM_ADAPTER_INFO
3466 LM_GetAdapterInfoBySsid(
3467 LM_UINT16 Svid,
3468 LM_UINT16 Ssid)
3469 {
3470 static LM_ADAPTER_INFO AdapterArr[] =
3471 {
3472 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
3473 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
3474 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
3475 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
3476 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
3477 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
3478 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
3479 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
3480 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
3481 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5703_PHY_ID, 0},
3482 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5703_PHY_ID, 0},
3483
3484 { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
3485 { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
3486 { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
3487 { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
3488 { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
3489
3490 { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
3491 { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
3492 { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3493 { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3494
3495 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
3496 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
3497 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
3498 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
3499 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
3500
3501 { 0x1014, 0x0281, 0, 1 },
3502 };
3503 LM_UINT32 j;
3504
3505 for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
3506 {
3507 if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
3508 {
3509 return &AdapterArr[j];
3510 }
3511 }
3512
3513 return NULL;
3514 }
3515
3516
3517
3518 /******************************************************************************/
3519 /* Description: */
3520 /* This routine sets up receive/transmit buffer descriptions queues. */
3521 /* */
3522 /* Return: */
3523 /* LM_STATUS_SUCCESS */
3524 /******************************************************************************/
3525 LM_STATUS
3526 LM_InitializeAdapter(
3527 PLM_DEVICE_BLOCK pDevice)
3528 {
3529 LM_PHYSICAL_ADDRESS MemPhy;
3530 PLM_UINT8 pMemVirt;
3531 PLM_PACKET pPacket;
3532 LM_STATUS Status;
3533 LM_UINT32 Size;
3534 LM_UINT32 Value32, j;
3535 LM_UINT32 DmaWrCmd, DmaRdCmd, DmaWrBdry, DmaRdBdry;
3536
3537 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3538 j = 0;
3539 while (((Value32 & 0x3ff) != (pDevice->PciCommandStatusWords & 0x3ff)) &&
3540 (j < 1000))
3541 {
3542 /* On PCIE devices, there are some rare cases where the device */
3543 /* is in the process of link-training at this point */
3544 MM_Wait(200);
3545 MM_WriteConfig32(pDevice, PCI_COMMAND_REG, pDevice->PciCommandStatusWords);
3546 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3547 j++;
3548 }
3549 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
3550 /* Set power state to D0. */
3551 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
3552
3553 /* Intialize the queues. */
3554 QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
3555 MAX_RX_PACKET_DESC_COUNT);
3556 QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
3557 MAX_RX_PACKET_DESC_COUNT);
3558
3559 QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
3560 QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
3561
3562 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
3563 {
3564 pDevice->RcvRetRcbEntryCount = 512;
3565 pDevice->RcvRetRcbEntryCountMask = 511;
3566 }
3567 else
3568 {
3569 pDevice->RcvRetRcbEntryCount = T3_RCV_RETURN_RCB_ENTRY_COUNT;
3570 pDevice->RcvRetRcbEntryCountMask = T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
3571 }
3572
3573 /* Allocate shared memory for: status block, the buffers for receive */
3574 /* rings -- standard, mini, jumbo, and return rings. */
3575 Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
3576 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3577 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3578 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3579 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3580 (pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3581
3582 /* Memory for host based Send BD. */
3583 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3584 {
3585 Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3586 }
3587
3588 /* Allocate the memory block. */
3589 Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
3590 if(Status != LM_STATUS_SUCCESS)
3591 {
3592 return Status;
3593 }
3594
3595 DmaWrCmd = DMA_CTRL_WRITE_CMD;
3596 DmaRdCmd = DMA_CTRL_READ_CMD;
3597 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_DISABLE;
3598 DmaRdBdry = DMA_CTRL_READ_BOUNDARY_DISABLE;
3599 #ifdef BCM_DISCONNECT_AT_CACHELINE
3600 /* This code is intended for PPC64 and other similar architectures */
3601 /* Only the following chips support this */
3602 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3603 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3604 (pDevice->Flags & PCI_EXPRESS_FLAG))
3605 {
3606 switch(pDevice->CacheLineSize * 4)
3607 {
3608 case 16:
3609 case 32:
3610 case 64:
3611 case 128:
3612 if (!(pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3613 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3614 {
3615 /* PCI-X */
3616 /* use 384 which is a multiple of 16,32,64,128 */
3617 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_384_PCIX;
3618 break;
3619 }
3620 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3621 {
3622 /* PCI Express */
3623 /* use 128 which is a multiple of 16,32,64,128 */
3624 DmaWrCmd = DMA_CTRL_WRITE_BOUNDARY_128_PCIE;
3625 break;
3626 }
3627 /* fall through */
3628 case 256:
3629 /* use 256 which is a multiple of 16,32,64,128,256 */
3630 if ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3631 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3632 {
3633 /* PCI */
3634 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256;
3635 }
3636 else if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
3637 {
3638 /* PCI-X */
3639 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256_PCIX;
3640 }
3641 break;
3642 }
3643 }
3644 #endif
3645 pDevice->DmaReadWriteCtrl = DmaWrCmd | DmaRdCmd | DmaWrBdry | DmaRdBdry;
3646 /* Program DMA Read/Write */
3647 if (pDevice->Flags & PCI_EXPRESS_FLAG)
3648 {
3649
3650 /* !=0 is 256 max or greater payload size so set water mark accordingly*/
3651 Value32 = (REG_RD(pDevice, PciCfg.DeviceCtrl) & MAX_PAYLOAD_SIZE_MASK);
3652 if (Value32)
3653 {
3654 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_256;
3655 }else
3656 {
3657 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_128;
3658 }
3659
3660 }
3661 else if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
3662 {
3663 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3664 {
3665 pDevice->DmaReadWriteCtrl |= 0x003f0000;
3666 }
3667 else
3668 {
3669 pDevice->DmaReadWriteCtrl |= 0x003f000f;
3670 }
3671 }
3672 else /* pci-x */
3673 {
3674 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3675 {
3676 pDevice->DmaReadWriteCtrl |= 0x009f0000;
3677 }
3678
3679 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3680 {
3681 pDevice->DmaReadWriteCtrl |= 0x009C0000;
3682 }
3683
3684 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
3685 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 )
3686 {
3687 Value32 = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
3688 if ((Value32 == 0x6) || (Value32 == 0x7))
3689 {
3690 pDevice->Flags |= ONE_DMA_AT_ONCE_FLAG;
3691 }
3692 }
3693 else if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
3694 {
3695 pDevice->DmaReadWriteCtrl &= ~DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3696 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
3697 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | DMA_CTRL_WRITE_ONE_DMA_AT_ONCE);
3698 else
3699 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | BIT_15);
3700 /* bit 15 is the current CQ 13140 Fix */
3701 }
3702 else
3703 {
3704 pDevice->DmaReadWriteCtrl |= 0x001b000f;
3705 }
3706 }
3707 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
3708 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
3709 {
3710 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
3711 }
3712
3713 if (pDevice->Flags & ONE_DMA_AT_ONCE_FLAG)
3714 {
3715 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3716 }
3717
3718 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
3719
3720 LM_SwitchClocks(pDevice);
3721
3722 if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
3723 {
3724 return LM_STATUS_FAILURE;
3725 }
3726
3727 /* Status block. */
3728 pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
3729 pDevice->StatusBlkPhy = MemPhy;
3730 pMemVirt += T3_STATUS_BLOCK_SIZE;
3731 LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
3732
3733 /* Statistics block. */
3734 pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
3735 pDevice->StatsBlkPhy = MemPhy;
3736 pMemVirt += sizeof(T3_STATS_BLOCK);
3737 LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
3738
3739 /* Receive standard BD buffer. */
3740 pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
3741 pDevice->RxStdBdPhy = MemPhy;
3742
3743 pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3744 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3745 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3746
3747 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3748 /* Receive jumbo BD buffer. */
3749 pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
3750 pDevice->RxJumboBdPhy = MemPhy;
3751
3752 pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3753 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3754 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3755 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3756
3757 /* Receive return BD buffer. */
3758 pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
3759 pDevice->RcvRetBdPhy = MemPhy;
3760
3761 pMemVirt += pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD);
3762 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3763 pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3764
3765 /* Set up Send BD. */
3766 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3767 {
3768 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
3769 pDevice->SendBdPhy = MemPhy;
3770
3771 pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3772 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3773 sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
3774 }
3775 #ifdef BCM_NIC_SEND_BD
3776 else
3777 {
3778 pDevice->pSendBdVirt = (PT3_SND_BD)
3779 pDevice->pMemView->uIntMem.First32k.BufferDesc;
3780 pDevice->SendBdPhy.High = 0;
3781 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
3782 }
3783 #endif
3784
3785 /* Allocate memory for packet descriptors. */
3786 Size = (pDevice->RxPacketDescCnt +
3787 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
3788 Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
3789 if(Status != LM_STATUS_SUCCESS)
3790 {
3791 return Status;
3792 }
3793 pDevice->pPacketDescBase = (PLM_VOID) pPacket;
3794
3795 /* Create transmit packet descriptors from the memory block and add them */
3796 /* to the TxPacketFreeQ for each send ring. */
3797 for(j = 0; j < pDevice->TxPacketDescCnt; j++)
3798 {
3799 /* Ring index. */
3800 pPacket->Flags = 0;
3801
3802 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
3803 QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
3804
3805 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3806 /* is the total size of the packet descriptor including the */
3807 /* os-specific extensions in the UM_PACKET structure. */
3808 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3809 } /* for(j.. */
3810
3811 /* Create receive packet descriptors from the memory block and add them */
3812 /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
3813 for(j = 0; j < pDevice->RxStdDescCnt; j++)
3814 {
3815 /* Receive producer ring. */
3816 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
3817
3818 /* Receive buffer size. */
3819 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
3820 (pDevice->RxJumboBufferSize) )
3821 {
3822 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3823 }else{
3824 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
3825 }
3826
3827 /* Add the descriptor to RxPacketFreeQ. */
3828 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3829
3830 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3831 /* is the total size of the packet descriptor including the */
3832 /* os-specific extensions in the UM_PACKET structure. */
3833 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3834 } /* for */
3835
3836
3837 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3838 /* Create the Jumbo packet descriptors. */
3839 for(j = 0; j < pDevice->RxJumboDescCnt; j++)
3840 {
3841 /* Receive producer ring. */
3842 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
3843
3844 /* Receive buffer size. */
3845 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3846
3847 /* Add the descriptor to RxPacketFreeQ. */
3848 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3849
3850 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3851 /* is the total size of the packet descriptor including the */
3852 /* os-specific extensions in the UM_PACKET structure. */
3853 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3854 } /* for */
3855 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3856
3857 /* Initialize the rest of the packet descriptors. */
3858 Status = MM_InitializeUmPackets(pDevice);
3859 if(Status != LM_STATUS_SUCCESS)
3860 {
3861 return Status;
3862 } /* if */
3863
3864 /* Default receive mask. */
3865 pDevice->ReceiveMask &= LM_KEEP_VLAN_TAG;
3866 pDevice->ReceiveMask |= LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3867 LM_ACCEPT_UNICAST;
3868
3869 /* Make sure we are in the first 32k memory window or NicSendBd. */
3870 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
3871
3872 /* Initialize the hardware. */
3873 Status = LM_ResetAdapter(pDevice);
3874 if(Status != LM_STATUS_SUCCESS)
3875 {
3876 return Status;
3877 }
3878
3879 /* We are done with initialization. */
3880 pDevice->InitDone = TRUE;
3881
3882 return LM_STATUS_SUCCESS;
3883 } /* LM_InitializeAdapter */
3884
3885
3886 LM_STATUS
3887 LM_DisableChip(PLM_DEVICE_BLOCK pDevice)
3888 {
3889 LM_UINT32 data;
3890
3891 pDevice->RxMode &= ~RX_MODE_ENABLE;
3892 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
3893 if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
3894 {
3895 MM_Wait(20);
3896 }
3897 data = REG_RD(pDevice, RcvBdIn.Mode);
3898 data &= ~RCV_BD_IN_MODE_ENABLE;
3899 REG_WR(pDevice, RcvBdIn.Mode,data);
3900 if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
3901 {
3902 MM_Wait(20);
3903 }
3904 data = REG_RD(pDevice, RcvListPlmt.Mode);
3905 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
3906 REG_WR(pDevice, RcvListPlmt.Mode,data);
3907 if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
3908 {
3909 MM_Wait(20);
3910 }
3911 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3912 {
3913 data = REG_RD(pDevice, RcvListSel.Mode);
3914 data &= ~RCV_LIST_SEL_MODE_ENABLE;
3915 REG_WR(pDevice, RcvListSel.Mode,data);
3916 if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
3917 {
3918 MM_Wait(20);
3919 }
3920 }
3921 data = REG_RD(pDevice, RcvDataBdIn.Mode);
3922 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
3923 REG_WR(pDevice, RcvDataBdIn.Mode,data);
3924 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
3925 {
3926 MM_Wait(20);
3927 }
3928 data = REG_RD(pDevice, RcvDataComp.Mode);
3929 data &= ~RCV_DATA_COMP_MODE_ENABLE;
3930 REG_WR(pDevice, RcvDataComp.Mode,data);
3931 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
3932 {
3933 MM_Wait(20);
3934 }
3935 data = REG_RD(pDevice, RcvBdComp.Mode);
3936 data &= ~RCV_BD_COMP_MODE_ENABLE;
3937 REG_WR(pDevice, RcvBdComp.Mode,data);
3938 if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
3939 {
3940 MM_Wait(20);
3941 }
3942 data = REG_RD(pDevice, SndBdSel.Mode);
3943 data &= ~SND_BD_SEL_MODE_ENABLE;
3944 REG_WR(pDevice, SndBdSel.Mode, data);
3945 if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
3946 {
3947 MM_Wait(20);
3948 }
3949 data = REG_RD(pDevice, SndBdIn.Mode);
3950 data &= ~SND_BD_IN_MODE_ENABLE;
3951 REG_WR(pDevice, SndBdIn.Mode, data);
3952 if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
3953 {
3954 MM_Wait(20);
3955 }
3956 data = REG_RD(pDevice, SndDataIn.Mode);
3957 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
3958 REG_WR(pDevice, SndDataIn.Mode,data);
3959 if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
3960 {
3961 MM_Wait(20);
3962 }
3963 data = REG_RD(pDevice, DmaRead.Mode);
3964 data &= ~DMA_READ_MODE_ENABLE;
3965 REG_WR(pDevice, DmaRead.Mode, data);
3966 if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
3967 {
3968 MM_Wait(20);
3969 }
3970 data = REG_RD(pDevice, SndDataComp.Mode);
3971 data &= ~SND_DATA_COMP_MODE_ENABLE;
3972 REG_WR(pDevice, SndDataComp.Mode, data);
3973 if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
3974 {
3975 MM_Wait(20);
3976 }
3977
3978 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3979 {
3980 data = REG_RD(pDevice,DmaComp.Mode);
3981 data &= ~DMA_COMP_MODE_ENABLE;
3982 REG_WR(pDevice, DmaComp.Mode, data);
3983 if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
3984 {
3985 MM_Wait(20);
3986 }
3987 }
3988 data = REG_RD(pDevice, SndBdComp.Mode);
3989 data &= ~SND_BD_COMP_MODE_ENABLE;
3990 REG_WR(pDevice, SndBdComp.Mode, data);
3991 if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
3992 {
3993 MM_Wait(20);
3994 }
3995 /* Clear TDE bit */
3996 pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
3997 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
3998 pDevice->TxMode &= ~TX_MODE_ENABLE;
3999 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4000 if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
4001 {
4002 MM_Wait(20);
4003 }
4004 data = REG_RD(pDevice, HostCoalesce.Mode);
4005 data &= ~HOST_COALESCE_ENABLE;
4006 REG_WR(pDevice, HostCoalesce.Mode, data);
4007 if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
4008 {
4009 MM_Wait(20);
4010 }
4011 data = REG_RD(pDevice, DmaWrite.Mode);
4012 data &= ~DMA_WRITE_MODE_ENABLE;
4013 REG_WR(pDevice, DmaWrite.Mode,data);
4014 if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
4015 {
4016 MM_Wait(20);
4017 }
4018
4019 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4020 {
4021 data = REG_RD(pDevice, MbufClusterFree.Mode);
4022 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
4023 REG_WR(pDevice, MbufClusterFree.Mode,data);
4024 if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
4025 {
4026 MM_Wait(20);
4027 }
4028 }
4029 /* Reset all FTQs */
4030 REG_WR(pDevice, Ftq.Reset, 0xffffffff);
4031 REG_WR(pDevice, Ftq.Reset, 0x0);
4032
4033 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4034 {
4035 data = REG_RD(pDevice, BufMgr.Mode);
4036 data &= ~BUFMGR_MODE_ENABLE;
4037 REG_WR(pDevice, BufMgr.Mode,data);
4038 if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
4039 {
4040 MM_Wait(20);
4041 }
4042 data = REG_RD(pDevice, MemArbiter.Mode);
4043 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
4044 REG_WR(pDevice, MemArbiter.Mode, data);
4045 if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
4046 {
4047 MM_Wait(20);
4048 }
4049 }
4050 return LM_STATUS_SUCCESS;
4051 }
4052
4053 LM_STATUS
4054 LM_DisableFW(PLM_DEVICE_BLOCK pDevice)
4055 {
4056 #ifdef BCM_ASF
4057 int j;
4058 LM_UINT32 Value32;
4059
4060 if (pDevice->AsfFlags & ASF_ENABLED)
4061 {
4062 MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, T3_CMD_NICDRV_PAUSE_FW);
4063 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4064 REG_WR(pDevice, Grc.RxCpuEvent, Value32 | BIT_14);
4065 for (j = 0; j < 100; j++)
4066 {
4067 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4068 if (!(Value32 & BIT_14))
4069 {
4070 break;
4071 }
4072 MM_Wait(1);
4073 }
4074 }
4075 #endif
4076 return LM_STATUS_SUCCESS;
4077 }
4078
4079 /******************************************************************************/
4080 /* Description: */
4081 /* This function reinitializes the adapter. */
4082 /* */
4083 /* Return: */
4084 /* LM_STATUS_SUCCESS */
4085 /******************************************************************************/
4086 LM_STATUS
4087 LM_ResetAdapter(
4088 PLM_DEVICE_BLOCK pDevice)
4089 {
4090 LM_UINT32 Value32;
4091 LM_UINT32 j, k;
4092 int reset_count = 0;
4093
4094 /* Disable interrupt. */
4095 LM_DisableInterrupt(pDevice);
4096
4097 restart_reset:
4098 LM_DisableFW(pDevice);
4099
4100 /* May get a spurious interrupt */
4101 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
4102
4103 LM_WritePreResetSignatures(pDevice, LM_INIT_RESET);
4104 /* Disable transmit and receive DMA engines. Abort all pending requests. */
4105 if(pDevice->InitDone)
4106 {
4107 LM_Abort(pDevice);
4108 }
4109
4110 pDevice->ShuttingDown = FALSE;
4111
4112 LM_ResetChip(pDevice);
4113
4114 LM_WriteLegacySignatures(pDevice, LM_INIT_RESET);
4115
4116 /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
4117 /* in other chip revisions except 5750 */
4118 if ((pDevice->Flags & DELAY_PCI_GRANT_FLAG) &&
4119 !(pDevice->Flags & PCI_EXPRESS_FLAG))
4120 {
4121 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | BIT_31);
4122 }
4123
4124 if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
4125 {
4126 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4127 {
4128 Value32 = REG_RD(pDevice, PciCfg.PciState);
4129 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
4130 REG_WR(pDevice, PciCfg.PciState, Value32);
4131 }
4132 }
4133 if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_BX)
4134 {
4135 /* New bits defined in register 0x64 to enable some h/w fixes */
4136 /* These new bits are 'write-only' */
4137 Value32 = REG_RD(pDevice, PciCfg.MsiData);
4138 REG_WR(pDevice, PciCfg.MsiData, Value32 | BIT_26 | BIT_28 | BIT_29);
4139 }
4140
4141 /* Enable TaggedStatus mode. */
4142 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
4143 {
4144 pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
4145 }
4146
4147 /* Restore PCI configuration registers. */
4148 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
4149 pDevice->SavedCacheLineReg);
4150 MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
4151 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
4152
4153 /* Initialize the statistis Block */
4154 pDevice->pStatusBlkVirt->Status = 0;
4155 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
4156 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
4157 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
4158
4159 for(j = 0; j < 16; j++)
4160 {
4161 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
4162 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
4163 }
4164
4165 for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
4166 {
4167 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
4168 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
4169 pDevice->pRxStdBdVirt[k].Flags = RCV_BD_FLAG_END;
4170 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
4171 (pDevice->RxJumboBufferSize) )
4172 pDevice->pRxStdBdVirt[k].Len = pDevice->RxJumboBufferSize;
4173 else
4174 pDevice->pRxStdBdVirt[k].Len = MAX_STD_RCV_BUFFER_SIZE;
4175 }
4176
4177 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4178 /* Receive jumbo BD buffer. */
4179 for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
4180 {
4181 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
4182 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
4183 pDevice->pRxJumboBdVirt[k].Flags = RCV_BD_FLAG_END |
4184 RCV_BD_FLAG_JUMBO_RING;
4185 pDevice->pRxJumboBdVirt[k].Len = (LM_UINT16) pDevice->RxJumboBufferSize;
4186 }
4187 #endif
4188
4189 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
4190
4191 /* GRC mode control register. */
4192 Value32 =
4193 #ifdef BIG_ENDIAN_HOST
4194 GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
4195 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4196 GRC_MODE_BYTE_SWAP_DATA |
4197 GRC_MODE_WORD_SWAP_DATA |
4198 #else
4199 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4200 GRC_MODE_BYTE_SWAP_DATA |
4201 GRC_MODE_WORD_SWAP_DATA |
4202 #endif
4203 GRC_MODE_INT_ON_MAC_ATTN |
4204 GRC_MODE_HOST_STACK_UP;
4205
4206 /* Configure send BD mode. */
4207 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4208 {
4209 Value32 |= GRC_MODE_HOST_SEND_BDS;
4210 }
4211 #ifdef BCM_NIC_SEND_BD
4212 else
4213 {
4214 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
4215 }
4216 #endif
4217
4218 /* Configure pseudo checksum mode. */
4219 if (pDevice->Flags & NO_TX_PSEUDO_HDR_CSUM_FLAG)
4220 {
4221 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
4222 }
4223
4224 if (pDevice->Flags & NO_RX_PSEUDO_HDR_CSUM_FLAG)
4225 {
4226 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
4227 }
4228
4229 pDevice->GrcMode = Value32;
4230 REG_WR(pDevice, Grc.Mode, Value32);
4231
4232 /* Setup the timer prescalar register. */
4233 Value32 = REG_RD(pDevice, Grc.MiscCfg) & ~0xff;
4234 /* Clock is always 66Mhz. */
4235 REG_WR(pDevice, Grc.MiscCfg, Value32 | (65 << 1));
4236
4237 /* Set up the MBUF pool base address and size. */
4238 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
4239 {
4240 #ifdef INCLUDE_TCP_SEG_SUPPORT
4241 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4242 {
4243 Value32 = LM_GetStkOffLdFirmwareSize(pDevice);
4244 Value32 = (Value32 + 0x7f) & ~0x7f;
4245 pDevice->MbufBase = T3_NIC_BCM5705_MBUF_POOL_ADDR + Value32;
4246 pDevice->MbufSize = T3_NIC_BCM5705_MBUF_POOL_SIZE - Value32 - 0xa00;
4247 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4248 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4249 }
4250 #endif
4251 }
4252 else if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4253 {
4254 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4255 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4256
4257 /* Set up the DMA descriptor pool base address and size. */
4258 REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
4259 REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
4260
4261 }
4262
4263 /* Configure MBUF and Threshold watermarks */
4264 /* Configure the DMA read MBUF low water mark. */
4265 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
4266 {
4267 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4268 {
4269 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4270 T3_DEF_DMA_MBUF_LOW_WMARK_5705);
4271 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4272 T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705);
4273 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4274 T3_DEF_MBUF_HIGH_WMARK_5705);
4275 }
4276 else
4277 {
4278 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4279 T3_DEF_DMA_MBUF_LOW_WMARK);
4280 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4281 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
4282 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4283 T3_DEF_MBUF_HIGH_WMARK);
4284 }
4285 }else if( T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
4286
4287 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,0);
4288 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,0x4b);
4289 REG_WR(pDevice, BufMgr.MbufHighWaterMark,0x96);
4290 }
4291 else
4292 {
4293 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4294 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
4295 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4296 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
4297 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4298 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
4299 }
4300
4301 REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
4302 REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
4303
4304 /* Enable buffer manager. */
4305 REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
4306
4307 for(j = 0 ;j < 2000; j++)
4308 {
4309 if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
4310 break;
4311 MM_Wait(10);
4312 }
4313
4314 if(j >= 2000)
4315 {
4316 return LM_STATUS_FAILURE;
4317 }
4318
4319 /* GRC reset will reset FTQ */
4320
4321 /* Receive BD Ring replenish threshold. */
4322 REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
4323
4324 /* Initialize the Standard Receive RCB. */
4325 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
4326 pDevice->RxStdBdPhy.High);
4327 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
4328 pDevice->RxStdBdPhy.Low);
4329 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
4330 (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
4331
4332 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4333 {
4334 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4335 512 << 16);
4336 }
4337 else
4338 {
4339 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4340 MAX_STD_RCV_BUFFER_SIZE << 16);
4341
4342 /* Initialize the Jumbo Receive RCB. */
4343 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
4344 T3_RCB_FLAG_RING_DISABLED);
4345 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4346 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
4347 pDevice->RxJumboBdPhy.High);
4348 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
4349 pDevice->RxJumboBdPhy.Low);
4350 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
4351 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
4352 (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
4353
4354 REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
4355
4356 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
4357
4358 /* Initialize the Mini Receive RCB. */
4359 REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
4360 T3_RCB_FLAG_RING_DISABLED);
4361
4362 /* Disable all the unused rings. */
4363 for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
4364 MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags,
4365 T3_RCB_FLAG_RING_DISABLED);
4366 } /* for */
4367
4368 }
4369
4370 /* Initialize the indices. */
4371 pDevice->SendProdIdx = 0;
4372 pDevice->SendConIdx = 0;
4373
4374 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
4375 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
4376 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
4377 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
4378
4379 /* Set up host or NIC based send RCB. */
4380 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4381 {
4382 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
4383 pDevice->SendBdPhy.High);
4384 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
4385 pDevice->SendBdPhy.Low);
4386
4387 /* Setup the RCB. */
4388 MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
4389 T3_SEND_RCB_ENTRY_COUNT << 16);
4390
4391 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4392 {
4393 /* Set up the NIC ring address in the RCB. */
4394 MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
4395 }
4396 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4397 {
4398 pDevice->pSendBdVirt[k].HostAddr.High = 0;
4399 pDevice->pSendBdVirt[k].HostAddr.Low = 0;
4400 }
4401 }
4402 #ifdef BCM_NIC_SEND_BD
4403 else
4404 {
4405 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
4406 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
4407 MEM_WR(pDevice, SendRcb[0].NicRingAddr,
4408 pDevice->SendBdPhy.Low);
4409
4410 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4411 {
4412 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.High), 0);
4413 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.Low), 0);
4414 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].u1.Len_Flags), 0);
4415 pDevice->ShadowSendBd[k].HostAddr.High = 0;
4416 pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
4417 }
4418 }
4419 #endif
4420 MM_ATOMIC_SET(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
4421
4422 /* Configure the receive return rings. */
4423 for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
4424 {
4425 MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
4426 }
4427
4428 pDevice->RcvRetConIdx = 0;
4429
4430 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
4431 pDevice->RcvRetBdPhy.High);
4432 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
4433 pDevice->RcvRetBdPhy.Low);
4434
4435 MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
4436
4437 /* Setup the RCB. */
4438 MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
4439 pDevice->RcvRetRcbEntryCount << 16);
4440
4441 /* Reinitialize RX ring producer index */
4442 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
4443 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
4444 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
4445 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
4446 MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
4447 MB_REG_RD(pDevice, Mailbox.RcvMiniProdIdx.Low);
4448
4449 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4450 pDevice->RxJumboProdIdx = 0;
4451 pDevice->RxJumboQueuedCnt = 0;
4452 #endif
4453
4454 /* Reinitialize our copy of the indices. */
4455 pDevice->RxStdProdIdx = 0;
4456 pDevice->RxStdQueuedCnt = 0;
4457
4458 #if T3_JUMBO_RCV_ENTRY_COUNT
4459 pDevice->RxJumboProdIdx = 0;
4460 #endif /* T3_JUMBO_RCV_ENTRY_COUNT */
4461
4462 /* Configure the MAC address. */
4463 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
4464
4465 /* Initialize the transmit random backoff seed. */
4466 Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
4467 pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
4468 pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
4469 MAC_TX_BACKOFF_SEED_MASK;
4470 REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
4471
4472 /* Receive MTU. Frames larger than the MTU is marked as oversized. */
4473 REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
4474
4475 /* Configure Time slot/IPG per 802.3 */
4476 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
4477
4478 /*
4479 * Configure Receive Rules so that packets don't match
4480 * Programmble rule will be queued to Return Ring 1
4481 */
4482 REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
4483
4484 /*
4485 * Configure to have 16 Classes of Services (COS) and one
4486 * queue per class. Bad frames are queued to RRR#1.
4487 * And frames don't match rules are also queued to COS#1.
4488 */
4489 REG_WR(pDevice, RcvListPlmt.Config, 0x181);
4490
4491 /* Enable Receive Placement Statistics */
4492 if ((pDevice->DmaReadFifoSize == DMA_READ_MODE_FIFO_LONG_BURST) &&
4493 (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION))
4494 {
4495 Value32 = REG_RD(pDevice, RcvListPlmt.StatsEnableMask);
4496 Value32 &= ~T3_DISABLE_LONG_BURST_READ_DYN_FIX;
4497 REG_WR(pDevice, RcvListPlmt.StatsEnableMask, Value32);
4498 }
4499 else
4500 {
4501 REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
4502 }
4503 REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
4504
4505 /* Enable Send Data Initator Statistics */
4506 REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
4507 REG_WR(pDevice, SndDataIn.StatsCtrl,
4508 T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
4509 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
4510
4511 /* Disable the host coalescing state machine before configuring it's */
4512 /* parameters. */
4513 REG_WR(pDevice, HostCoalesce.Mode, 0);
4514 for(j = 0; j < 2000; j++)
4515 {
4516 Value32 = REG_RD(pDevice, HostCoalesce.Mode);
4517 if(!(Value32 & HOST_COALESCE_ENABLE))
4518 {
4519 break;
4520 }
4521 MM_Wait(10);
4522 }
4523
4524 /* Host coalescing configurations. */
4525 REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
4526 REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
4527 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
4528 pDevice->RxMaxCoalescedFrames);
4529 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
4530 pDevice->TxMaxCoalescedFrames);
4531
4532 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4533 {
4534 REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
4535 pDevice->RxCoalescingTicksDuringInt);
4536 REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
4537 pDevice->TxCoalescingTicksDuringInt);
4538 }
4539 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
4540 pDevice->RxMaxCoalescedFramesDuringInt);
4541 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
4542 pDevice->TxMaxCoalescedFramesDuringInt);
4543
4544 /* Initialize the address of the status block. The NIC will DMA */
4545 /* the status block to this memory which resides on the host. */
4546 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
4547 pDevice->StatusBlkPhy.High);
4548 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
4549 pDevice->StatusBlkPhy.Low);
4550
4551 /* Initialize the address of the statistics block. The NIC will DMA */
4552 /* the statistics to this block of memory. */
4553 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4554 {
4555 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
4556 pDevice->StatsBlkPhy.High);
4557 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
4558 pDevice->StatsBlkPhy.Low);
4559
4560 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
4561 pDevice->StatsCoalescingTicks);
4562
4563 REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
4564 REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
4565 }
4566
4567 /* Enable Host Coalesing state machine */
4568 REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
4569 pDevice->CoalesceMode);
4570
4571 /* Enable the Receive BD Completion state machine. */
4572 REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
4573 RCV_BD_COMP_MODE_ATTN_ENABLE);
4574
4575 /* Enable the Receive List Placement state machine. */
4576 REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
4577
4578 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4579 {
4580 /* Enable the Receive List Selector state machine. */
4581 REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
4582 RCV_LIST_SEL_MODE_ATTN_ENABLE);
4583 }
4584
4585 /* Reset the Rx MAC State Machine.
4586 *
4587 * The Rx MAC State Machine must be reset when using fiber to prevent the
4588 * first packet being lost. This is needed primarily so that the loopback
4589 * test (which currently only sends one packet) doesn't fail.
4590 *
4591 * Also note that the Rx MAC State Machine (0x468) should be reset _before_
4592 * writting to the MAC Mode register (0x400). Failures have been seen on
4593 * 5780/5714's using fiber where they stopped receiving packets in a simple
4594 * ping test when the Rx MAC State Machine was reset _after_ the MAC Mode
4595 * register was set.
4596 */
4597
4598 if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) ||
4599 (pDevice->PhyFlags & PHY_IS_FIBER))
4600 {
4601 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
4602 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4603 MM_Wait(10);
4604 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4605 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4606 }
4607
4608 /* Clear the statistics block. */
4609 for(j = 0x0300; j < 0x0b00; j = j + 4)
4610 {
4611 MEM_WR_OFFSET(pDevice, j, 0);
4612 }
4613
4614 /* Set Mac Mode */
4615 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4616 {
4617 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
4618 }
4619 else if(pDevice->PhyFlags & PHY_IS_FIBER)
4620 {
4621 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
4622 }
4623 else
4624 {
4625 pDevice->MacMode = 0;
4626 }
4627
4628 /* Enable transmit DMA, clear statistics. */
4629 pDevice->MacMode |= MAC_MODE_ENABLE_TX_STATISTICS |
4630 MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
4631 MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
4632 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
4633 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
4634
4635 /* GRC miscellaneous local control register. */
4636 pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
4637 GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
4638
4639 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
4640 {
4641 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
4642 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
4643 }
4644 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
4645 !(pDevice->Flags & EEPROM_WP_FLAG))
4646 {
4647 /* Make sure we're on Vmain */
4648 /* The other port may cause us to be on Vaux */
4649 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
4650 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2;
4651 }
4652
4653 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4654 MM_Wait(40);
4655
4656 /* Reset RX counters. */
4657 for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
4658 {
4659 ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
4660 }
4661
4662 /* Reset TX counters. */
4663 for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
4664 {
4665 ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
4666 }
4667
4668 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
4669 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4670 pDevice->LastTag = 0;
4671
4672 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4673 {
4674 /* Enable the DMA Completion state machine. */
4675 REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
4676 }
4677
4678 /* Enable the DMA Write state machine. */
4679 Value32 = DMA_WRITE_MODE_ENABLE |
4680 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
4681 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
4682 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
4683 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4684 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4685 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4686 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4687 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
4688
4689 if (pDevice->Flags & DMA_WR_MODE_RX_ACCELERATE_FLAG)
4690 {
4691 Value32 |= DMA_WRITE_MODE_RECEIVE_ACCELERATE;
4692 }
4693
4694 if (pDevice->Flags & HOST_COALESCING_BUG_FIX)
4695 {
4696 Value32 |= (1 << 29);
4697 }
4698
4699 REG_WR(pDevice, DmaWrite.Mode, Value32);
4700
4701 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4702 {
4703 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
4704 {
4705 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4706 Value32 &= ~PCIX_CMD_MAX_BURST_MASK;
4707 Value32 |= PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL;
4708 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4709 }
4710 else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4711 {
4712 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4713 Value32 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
4714 Value32 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
4715 PCIX_CMD_MAX_BURST_MASK);
4716 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4717 {
4718 Value32 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
4719 & PCIX_CMD_MAX_SPLIT_MASK;
4720 }
4721 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4722 }
4723 }
4724
4725 /* Enable the Read DMA state machine. */
4726 Value32 = DMA_READ_MODE_ENABLE |
4727 DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
4728 DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
4729 DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
4730 DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4731 DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4732 DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4733 DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4734 DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
4735
4736 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4737 {
4738 Value32 |= DMA_READ_MODE_MULTI_SPLIT_ENABLE;
4739 }
4740
4741 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4742 {
4743 Value32 |= pDevice->DmaReadFifoSize;
4744 }
4745 #ifdef INCLUDE_TCP_SEG_SUPPORT
4746 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4747 {
4748 Value32 |= BIT_27;
4749 }
4750 #endif
4751
4752
4753 REG_WR(pDevice, DmaRead.Mode, Value32);
4754
4755 /* Enable the Receive Data Completion state machine. */
4756 REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
4757 RCV_DATA_COMP_MODE_ATTN_ENABLE);
4758
4759 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4760 {
4761 /* Enable the Mbuf Cluster Free state machine. */
4762 REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
4763 }
4764
4765 /* Enable the Send Data Completion state machine. */
4766 REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
4767
4768 /* Enable the Send BD Completion state machine. */
4769 REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
4770 SND_BD_COMP_MODE_ATTN_ENABLE);
4771
4772 /* Enable the Receive BD Initiator state machine. */
4773 REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
4774 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
4775
4776 /* Enable the Receive Data and Receive BD Initiator state machine. */
4777 REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
4778 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
4779
4780 /* Enable the Send Data Initiator state machine. */
4781 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
4782
4783 #ifdef INCLUDE_TCP_SEG_SUPPORT
4784 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4785 {
4786 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE | 0x8);
4787 }
4788 #endif
4789
4790 /* Enable the Send BD Initiator state machine. */
4791 REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
4792 SND_BD_IN_MODE_ATTN_ENABLE);
4793
4794 /* Enable the Send BD Selector state machine. */
4795 REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
4796 SND_BD_SEL_MODE_ATTN_ENABLE);
4797
4798 #ifdef INCLUDE_5701_AX_FIX
4799 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
4800 {
4801 LM_LoadRlsFirmware(pDevice);
4802 }
4803 #endif
4804
4805 /* Queue Rx packet buffers. */
4806 if(pDevice->QueueRxPackets)
4807 {
4808 LM_QueueRxPackets(pDevice);
4809 }
4810
4811 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
4812 {
4813 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4814 j = 0;
4815 while ((Value32 != MAX_STD_RCV_BUFFER_SIZE) && (j < 10))
4816 {
4817 MM_Wait(20);
4818 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4819 j++;
4820 }
4821 if (j >= 10)
4822 {
4823 reset_count++;
4824 LM_Abort(pDevice);
4825 if (reset_count > 5)
4826 return LM_STATUS_FAILURE;
4827 goto restart_reset;
4828 }
4829 }
4830
4831 /* Enable the transmitter. */
4832 pDevice->TxMode = TX_MODE_ENABLE;
4833 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4834
4835 /* Enable the receiver. */
4836 pDevice->RxMode = (pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) |
4837 RX_MODE_ENABLE;
4838 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4839
4840 #ifdef BCM_WOL
4841 if (pDevice->RestoreOnWakeUp)
4842 {
4843 pDevice->RestoreOnWakeUp = FALSE;
4844 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
4845 pDevice->RequestedLineSpeed = pDevice->WakeUpRequestedLineSpeed;
4846 pDevice->RequestedDuplexMode = pDevice->WakeUpRequestedDuplexMode;
4847 }
4848 #endif
4849
4850 /* Disable auto polling. */
4851 pDevice->MiMode = 0xc0000;
4852 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
4853
4854 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
4855
4856 /* Activate Link to enable MAC state machine */
4857 REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
4858
4859 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4860 {
4861 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
4862 {
4863 REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
4864 }
4865 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4866 {
4867
4868 if(!(pDevice->TbiFlags & TBI_DO_PREEMPHASIS))
4869 {
4870 /* Set SerDes drive transmission level to 1.2V */
4871 Value32 = REG_RD(pDevice, MacCtrl.SerdesCfg) & 0xfffff000;
4872 REG_WR(pDevice, MacCtrl.SerdesCfg, Value32 | 0x880);
4873 }
4874 }
4875 }
4876
4877 REG_WR(pDevice, MacCtrl.LowWaterMarkMaxRxFrame, 2);
4878
4879 if(pDevice->PhyFlags & PHY_IS_FIBER)
4880 {
4881 Value32 = REG_RD_OFFSET(pDevice, 0x5b0);
4882 REG_WR_OFFSET(pDevice, 0x5b0, Value32 | BIT_10 );
4883
4884 pDevice->GrcLocalCtrl |= BIT_4 ;
4885 pDevice->GrcLocalCtrl &= ~BIT_5 ;
4886
4887 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4888 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
4889 MM_Wait(40);
4890 }
4891
4892 if (!pDevice->InitDone)
4893 {
4894 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
4895 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
4896 } else {
4897 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
4898 }
4899 }
4900
4901 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
4902 ( ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5401_PHY_ID)&&
4903 ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) ))
4904 {
4905 /* 5401/5411 PHY needs a delay of about 1 second after PHY reset */
4906 /* Without the delay, it has problem linking at forced 10 half */
4907 /* So skip the reset... */
4908 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
4909 for(j =0; j<0x5000; j++)
4910 MM_Wait(1);
4911
4912 LM_ResetPhy(pDevice);
4913 }
4914
4915 /* Setup the phy chip. */
4916 LM_SetupPhy(pDevice);
4917
4918 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)){
4919 /* Clear CRC stats */
4920 LM_ReadPhy(pDevice, 0x1e, &Value32);
4921 LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
4922 LM_ReadPhy(pDevice, 0x14, &Value32);
4923 }
4924
4925 /* Set up the receive mask. */
4926 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
4927
4928 #ifdef INCLUDE_TCP_SEG_SUPPORT
4929 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4930 {
4931 if (LM_LoadStkOffLdFirmware(pDevice) == LM_STATUS_FAILURE)
4932 {
4933 return LM_STATUS_FAILURE;
4934 }
4935 }
4936 #endif
4937 LM_WritePostResetSignatures(pDevice, LM_INIT_RESET);
4938
4939 return LM_STATUS_SUCCESS;
4940 } /* LM_ResetAdapter */
4941
4942
4943 /******************************************************************************/
4944 /* Description: */
4945 /* This routine disables the adapter from generating interrupts. */
4946 /* */
4947 /* Return: */
4948 /* LM_STATUS_SUCCESS */
4949 /******************************************************************************/
4950 LM_STATUS
4951 LM_DisableInterrupt(
4952 PLM_DEVICE_BLOCK pDevice)
4953 {
4954 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
4955 MISC_HOST_CTRL_MASK_PCI_INT);
4956 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
4957 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4958 {
4959 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4960 }
4961
4962 return LM_STATUS_SUCCESS;
4963 }
4964
4965
4966
4967 /******************************************************************************/
4968 /* Description: */
4969 /* This routine enables the adapter to generate interrupts. */
4970 /* */
4971 /* Return: */
4972 /* LM_STATUS_SUCCESS */
4973 /******************************************************************************/
4974 LM_STATUS
4975 LM_EnableInterrupt(
4976 PLM_DEVICE_BLOCK pDevice)
4977 {
4978 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, pDevice->LastTag << 24);
4979 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4980 {
4981 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4982 }
4983
4984 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
4985 ~MISC_HOST_CTRL_MASK_PCI_INT);
4986
4987 REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode |
4988 HOST_COALESCE_ENABLE | HOST_COALESCE_NOW);
4989
4990 return LM_STATUS_SUCCESS;
4991 }
4992
4993
4994
4995 /******************************************************************************/
4996 /* Description: */
4997 /* This routine puts a packet on the wire if there is a transmit DMA */
4998 /* descriptor available; otherwise the packet is queued for later */
4999 /* transmission. If the second argue is NULL, this routine will put */
5000 /* the queued packet on the wire if possible. */
5001 /* */
5002 /* Return: */
5003 /* LM_STATUS_SUCCESS */
5004 /******************************************************************************/
5005 LM_STATUS
5006 LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
5007 {
5008 LM_UINT32 FragCount;
5009 PT3_SND_BD pSendBd, pTmpSendBd;
5010 #ifdef BCM_NIC_SEND_BD
5011 PT3_SND_BD pShadowSendBd;
5012 T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
5013 #endif
5014 LM_UINT32 StartIdx, Idx;
5015
5016 while (1)
5017 {
5018 /* Initalize the send buffer descriptors. */
5019 StartIdx = Idx = pDevice->SendProdIdx;
5020
5021 #ifdef BCM_NIC_SEND_BD
5022 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5023 {
5024 pTmpSendBd = pSendBd = &NicSendBdArr[0];
5025 }
5026 else
5027 #endif
5028 {
5029 pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
5030 }
5031
5032 /* Next producer index. */
5033 for(FragCount = 0; ; )
5034 {
5035 LM_UINT32 Value32, Len;
5036
5037 /* Initialize the pointer to the send buffer fragment. */
5038 MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
5039
5040 pSendBd->u2.VlanTag = pPacket->VlanTag;
5041
5042 /* Setup the control flags and send buffer size. */
5043 Value32 = (Len << 16) | pPacket->Flags;
5044
5045 #ifdef INCLUDE_TCP_SEG_SUPPORT
5046 if (Value32 & (SND_BD_FLAG_CPU_PRE_DMA | SND_BD_FLAG_CPU_POST_DMA))
5047 {
5048 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5049 {
5050 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5051 }
5052 else if (FragCount == 0)
5053 {
5054 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5055 }
5056 else
5057 {
5058 pSendBd->u2.s2.Reserved = 0;
5059 Value32 &= 0xffff0fff;
5060 }
5061 }
5062 #endif
5063 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5064
5065 FragCount++;
5066 if (FragCount >= pPacket->u.Tx.FragCount)
5067 {
5068 pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
5069 break;
5070 }
5071 else
5072 {
5073 pSendBd->u1.Len_Flags = Value32;
5074 }
5075
5076 pSendBd++;
5077 if ((Idx == 0) &&
5078 !(pDevice->Flags & NIC_SEND_BD_FLAG))
5079 {
5080 pSendBd = &pDevice->pSendBdVirt[0];
5081 }
5082
5083 pDevice->SendRing[Idx] = 0;
5084
5085 } /* for */
5086 if (pDevice->Flags & TX_4G_WORKAROUND_FLAG)
5087 {
5088 if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
5089 LM_STATUS_SUCCESS)
5090 {
5091 if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
5092 {
5093 QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
5094 return LM_STATUS_FAILURE;
5095 }
5096 continue;
5097 }
5098 }
5099 break;
5100 }
5101 /* Put the packet descriptor in the ActiveQ. */
5102 pDevice->SendRing[StartIdx] = pPacket;
5103
5104 #ifdef BCM_NIC_SEND_BD
5105 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5106 {
5107 pSendBd = &pDevice->pSendBdVirt[StartIdx];
5108 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
5109
5110 while (StartIdx != Idx)
5111 {
5112 LM_UINT32 Value32;
5113
5114 if ((Value32 = pTmpSendBd->HostAddr.High) !=
5115 pShadowSendBd->HostAddr.High)
5116 {
5117 MM_MEMWRITEL(&(pSendBd->HostAddr.High), Value32);
5118 pShadowSendBd->HostAddr.High = Value32;
5119 }
5120
5121 MM_MEMWRITEL(&(pSendBd->HostAddr.Low), pTmpSendBd->HostAddr.Low);
5122
5123 if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
5124 pShadowSendBd->u1.Len_Flags)
5125 {
5126 MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), Value32);
5127 pShadowSendBd->u1.Len_Flags = Value32;
5128 }
5129
5130 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
5131 {
5132 MM_MEMWRITEL(&(pSendBd->u2.VlanTag), pTmpSendBd->u2.VlanTag);
5133 }
5134
5135 StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5136 if (StartIdx == 0)
5137 {
5138 pSendBd = &pDevice->pSendBdVirt[0];
5139 pShadowSendBd = &pDevice->ShadowSendBd[0];
5140 }
5141 else
5142 {
5143 pSendBd++;
5144 pShadowSendBd++;
5145 }
5146 pTmpSendBd++;
5147 }
5148 MM_WMB();
5149 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5150
5151 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5152 {
5153 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5154 }
5155 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5156 {
5157 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
5158 }
5159 else
5160 {
5161 MM_MMIOWB();
5162 }
5163 }
5164 else
5165 #endif
5166 {
5167 MM_WMB();
5168 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5169
5170 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5171 {
5172 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5173 }
5174 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5175 {
5176 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
5177 }
5178 else
5179 {
5180 MM_MMIOWB();
5181 }
5182 }
5183
5184 /* Update the SendBdLeft count. */
5185 MM_ATOMIC_SUB(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5186
5187 /* Update the producer index. */
5188 pDevice->SendProdIdx = Idx;
5189
5190 return LM_STATUS_SUCCESS;
5191 }
5192
5193 STATIC LM_STATUS
5194 LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
5195 PT3_SND_BD pSendBd)
5196 {
5197 int FragCount;
5198 LM_UINT32 Idx, Base, Len;
5199
5200 Idx = pDevice->SendProdIdx;
5201 for(FragCount = 0; ; )
5202 {
5203 Len = pSendBd->u1.Len_Flags >> 16;
5204 if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
5205 ((Base + 8 + Len) < Base))
5206 {
5207 return LM_STATUS_SUCCESS;
5208 }
5209 FragCount++;
5210 if (FragCount >= pPacket->u.Tx.FragCount)
5211 {
5212 break;
5213 }
5214 pSendBd++;
5215 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
5216 {
5217 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5218 if (Idx == 0)
5219 {
5220 pSendBd = &pDevice->pSendBdVirt[0];
5221 }
5222 }
5223 }
5224 return LM_STATUS_FAILURE;
5225 }
5226
5227 /******************************************************************************/
5228 /* Description: */
5229 /* */
5230 /* Return: */
5231 /******************************************************************************/
5232 LM_UINT32
5233 ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize)
5234 {
5235 LM_UINT32 Reg;
5236 LM_UINT32 Tmp;
5237 int j, k;
5238
5239 Reg = 0xffffffff;
5240
5241 for(j = 0; j < BufferSize; j++)
5242 {
5243 Reg ^= pBuffer[j];
5244
5245 for(k = 0; k < 8; k++)
5246 {
5247 Tmp = Reg & 0x01;
5248
5249 Reg >>= 1;
5250
5251 if(Tmp)
5252 {
5253 Reg ^= 0xedb88320;
5254 }
5255 }
5256 }
5257
5258 return ~Reg;
5259 } /* ComputeCrc32 */
5260
5261
5262
5263 /******************************************************************************/
5264 /* Description: */
5265 /* This routine sets the receive control register according to ReceiveMask */
5266 /* */
5267 /* Return: */
5268 /* LM_STATUS_SUCCESS */
5269 /******************************************************************************/
5270 LM_STATUS
5271 LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
5272 {
5273 LM_UINT32 ReceiveMask;
5274 LM_UINT32 RxMode;
5275 LM_UINT32 j, k;
5276
5277 ReceiveMask = Mask;
5278
5279 RxMode = pDevice->RxMode;
5280
5281 if(Mask & LM_ACCEPT_UNICAST)
5282 {
5283 Mask &= ~LM_ACCEPT_UNICAST;
5284 }
5285
5286 if(Mask & LM_ACCEPT_MULTICAST)
5287 {
5288 Mask &= ~LM_ACCEPT_MULTICAST;
5289 }
5290
5291 if(Mask & LM_ACCEPT_ALL_MULTICAST)
5292 {
5293 Mask &= ~LM_ACCEPT_ALL_MULTICAST;
5294 }
5295
5296 if(Mask & LM_ACCEPT_BROADCAST)
5297 {
5298 Mask &= ~LM_ACCEPT_BROADCAST;
5299 }
5300
5301 RxMode &= ~RX_MODE_KEEP_VLAN_TAG;
5302 if (Mask & LM_KEEP_VLAN_TAG)
5303 {
5304 RxMode |= RX_MODE_KEEP_VLAN_TAG;
5305 Mask &= ~LM_KEEP_VLAN_TAG;
5306 }
5307
5308 RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
5309 if(Mask & LM_PROMISCUOUS_MODE)
5310 {
5311 RxMode |= RX_MODE_PROMISCUOUS_MODE;
5312 Mask &= ~LM_PROMISCUOUS_MODE;
5313 }
5314
5315 RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
5316 if(Mask & LM_ACCEPT_ERROR_PACKET)
5317 {
5318 RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
5319 Mask &= ~LM_ACCEPT_ERROR_PACKET;
5320 }
5321
5322 /* Make sure all the bits are valid before committing changes. */
5323 if(Mask)
5324 {
5325 return LM_STATUS_FAILURE;
5326 }
5327
5328 /* Commit the new filter. */
5329 pDevice->ReceiveMask = ReceiveMask;
5330
5331 pDevice->RxMode = RxMode;
5332
5333 if (pDevice->PowerLevel != LM_POWER_STATE_D0)
5334 {
5335 return LM_STATUS_SUCCESS;
5336 }
5337
5338 REG_WR(pDevice, MacCtrl.RxMode, RxMode);
5339
5340 /* Set up the MC hash table. */
5341 if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
5342 {
5343 for(k = 0; k < 4; k++)
5344 {
5345 REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
5346 }
5347 }
5348 else if(ReceiveMask & LM_ACCEPT_MULTICAST)
5349 {
5350 for(k = 0; k < 4; k++)
5351 {
5352 REG_WR(pDevice, MacCtrl.HashReg[k], pDevice->MulticastHash[k]);
5353 }
5354 }
5355 else
5356 {
5357 /* Reject all multicast frames. */
5358 for(j = 0; j < 4; j++)
5359 {
5360 REG_WR(pDevice, MacCtrl.HashReg[j], 0);
5361 }
5362 }
5363
5364 /* By default, Tigon3 will accept broadcast frames. We need to setup */
5365 if(ReceiveMask & LM_ACCEPT_BROADCAST)
5366 {
5367 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5368 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5369 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5370 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5371 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5372 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5373 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5374 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5375 }
5376 else
5377 {
5378 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5379 REJECT_BROADCAST_RULE1_RULE);
5380 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5381 REJECT_BROADCAST_RULE1_VALUE);
5382 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5383 REJECT_BROADCAST_RULE2_RULE);
5384 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5385 REJECT_BROADCAST_RULE2_VALUE);
5386 }
5387
5388 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5389 {
5390 k = 16;
5391 }
5392 else if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5393 {
5394 k = 16;
5395 }
5396 else
5397 {
5398 k = 8;
5399 }
5400 #ifdef BCM_ASF
5401 if (pDevice->AsfFlags & ASF_ENABLED)
5402 {
5403 k -= 4;
5404 }
5405 #endif
5406
5407 /* disable the rest of the rules. */
5408 for(j = RCV_LAST_RULE_IDX; j < k; j++)
5409 {
5410 REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
5411 REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
5412 }
5413
5414 return LM_STATUS_SUCCESS;
5415 } /* LM_SetReceiveMask */
5416
5417
5418
5419 /******************************************************************************/
5420 /* Description: */
5421 /* Disable the interrupt and put the transmitter and receiver engines in */
5422 /* an idle state. Also aborts all pending send requests and receive */
5423 /* buffers. */
5424 /* */
5425 /* Return: */
5426 /* LM_STATUS_SUCCESS */
5427 /******************************************************************************/
5428 LM_STATUS
5429 LM_Abort(
5430 PLM_DEVICE_BLOCK pDevice)
5431 {
5432 PLM_PACKET pPacket;
5433 LM_UINT Idx;
5434
5435 LM_DisableInterrupt(pDevice);
5436
5437 LM_DisableChip(pDevice);
5438
5439 /*
5440 * If we do not have a status block pointer, then
5441 * the device hasn't really been opened. Do not
5442 * attempt to clean up packets.
5443 */
5444 if (pDevice->pStatusBlkVirt == NULL)
5445 return LM_STATUS_SUCCESS;
5446
5447 /* Abort packets that have already queued to go out. */
5448 Idx = pDevice->SendConIdx;
5449 for ( ; ; )
5450 {
5451 if ((pPacket = pDevice->SendRing[Idx]))
5452 {
5453 pDevice->SendRing[Idx] = 0;
5454 pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
5455 pDevice->TxCounters.TxPacketAbortedCnt++;
5456
5457 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5458 Idx = (Idx + pPacket->u.Tx.FragCount) &
5459 T3_SEND_RCB_ENTRY_COUNT_MASK;
5460
5461 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5462 }
5463 else
5464 {
5465 break;
5466 }
5467 }
5468
5469 /* Cleanup the receive return rings. */
5470 #ifdef BCM_NAPI_RXPOLL
5471 LM_ServiceRxPoll(pDevice, T3_RCV_RETURN_RCB_ENTRY_COUNT);
5472 #else
5473 LM_ServiceRxInterrupt(pDevice);
5474 #endif
5475
5476 /* Indicate packets to the protocol. */
5477 MM_IndicateTxPackets(pDevice);
5478
5479 #ifdef BCM_NAPI_RXPOLL
5480
5481 /* Move the receive packet descriptors in the ReceivedQ to the */
5482 /* free queue. */
5483 for(; ;)
5484 {
5485 pPacket = (PLM_PACKET) QQ_PopHead(
5486 &pDevice->RxPacketReceivedQ.Container);
5487 if(pPacket == NULL)
5488 {
5489 break;
5490 }
5491 MM_UnmapRxDma(pDevice, pPacket);
5492 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5493 }
5494 #else
5495 /* Indicate received packets to the protocols. */
5496 MM_IndicateRxPackets(pDevice);
5497 #endif
5498
5499 /* Clean up the Std Receive Producer ring. */
5500 /* Don't always trust the consumer idx in the status block in case of */
5501 /* hw failure */
5502 Idx = 0;
5503
5504 while(Idx < T3_STD_RCV_RCB_ENTRY_COUNT)
5505 {
5506 if ((pPacket = pDevice->RxStdRing[Idx]))
5507 {
5508 MM_UnmapRxDma(pDevice, pPacket);
5509 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5510 pDevice->RxStdRing[Idx] = 0;
5511 }
5512
5513 Idx++;
5514 } /* while */
5515
5516 /* Reinitialize our copy of the indices. */
5517 pDevice->RxStdProdIdx = 0;
5518
5519 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5520 /* Clean up the Jumbo Receive Producer ring. */
5521 Idx = 0;
5522
5523 while(Idx < T3_JUMBO_RCV_RCB_ENTRY_COUNT)
5524 {
5525 if ((pPacket = pDevice->RxJumboRing[Idx]))
5526 {
5527 MM_UnmapRxDma(pDevice, pPacket);
5528 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5529 pDevice->RxJumboRing[Idx] = 0;
5530 }
5531 Idx++;
5532 } /* while */
5533
5534 /* Reinitialize our copy of the indices. */
5535 pDevice->RxJumboProdIdx = 0;
5536 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
5537
5538 /* Initialize the statistis Block */
5539 pDevice->pStatusBlkVirt->Status = 0;
5540 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
5541 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
5542 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
5543
5544 return LM_STATUS_SUCCESS;
5545 } /* LM_Abort */
5546
5547
5548
5549 /******************************************************************************/
5550 /* Description: */
5551 /* Disable the interrupt and put the transmitter and receiver engines in */
5552 /* an idle state. Aborts all pending send requests and receive buffers. */
5553 /* Also free all the receive buffers. */
5554 /* */
5555 /* Return: */
5556 /* LM_STATUS_SUCCESS */
5557 /******************************************************************************/
5558 LM_STATUS
5559 LM_DoHalt(LM_DEVICE_BLOCK *pDevice)
5560 {
5561 PLM_PACKET pPacket;
5562 LM_UINT32 EntryCnt;
5563
5564 LM_DisableFW(pDevice);
5565
5566 LM_WritePreResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5567 LM_Abort(pDevice);
5568
5569 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
5570 LM_WritePhy(pDevice, BCM546X_1c_SHADOW_REG,
5571 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN));
5572
5573 /* Get the number of entries in the queue. */
5574 EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
5575
5576 /* Make sure all the packets have been accounted for. */
5577 for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
5578 {
5579 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
5580 if (pPacket == 0)
5581 break;
5582
5583 MM_FreeRxBuffer(pDevice, pPacket);
5584
5585 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5586 }
5587
5588 LM_ResetChip(pDevice);
5589 LM_WriteLegacySignatures(pDevice, LM_SHUTDOWN_RESET);
5590
5591 /* Restore PCI configuration registers. */
5592 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
5593 pDevice->SavedCacheLineReg);
5594 LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
5595 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
5596
5597 /* Reprogram the MAC address. */
5598 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
5599
5600 return LM_STATUS_SUCCESS;
5601 } /* LM_DoHalt */
5602
5603
5604 LM_STATUS
5605 LM_Halt(LM_DEVICE_BLOCK *pDevice)
5606 {
5607 LM_STATUS status;
5608
5609 status = LM_DoHalt(pDevice);
5610 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5611 return status;
5612 }
5613
5614
5615 STATIC LM_VOID
5616 LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5617 {
5618 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,T3_MAGIC_NUM_FIRMWARE_INIT_DONE);
5619 #ifdef BCM_ASF
5620 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5621 {
5622 if (Mode == LM_INIT_RESET)
5623 {
5624 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5625 }
5626 else if (Mode == LM_SHUTDOWN_RESET)
5627 {
5628 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5629 }
5630 else if (Mode == LM_SUSPEND_RESET)
5631 {
5632 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5633 }
5634 }
5635 #endif
5636 }
5637
5638 STATIC LM_VOID
5639 LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5640 {
5641 #ifdef BCM_ASF
5642 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5643 {
5644 if (Mode == LM_INIT_RESET)
5645 {
5646 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5647 T3_DRV_STATE_START_DONE);
5648 }
5649 else if (Mode == LM_SHUTDOWN_RESET)
5650 {
5651 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5652 T3_DRV_STATE_UNLOAD_DONE);
5653 }
5654 }
5655 #endif
5656 }
5657
5658 STATIC LM_VOID
5659 LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5660 {
5661 #ifdef BCM_ASF
5662 if (pDevice->AsfFlags & ASF_ENABLED)
5663 {
5664 if (Mode == LM_INIT_RESET)
5665 {
5666 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5667 }
5668 else if (Mode == LM_SHUTDOWN_RESET)
5669 {
5670 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5671 }
5672 else if (Mode == LM_SUSPEND_RESET)
5673 {
5674 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5675 }
5676 }
5677 #endif
5678 }
5679
5680 STATIC LM_STATUS
5681 LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
5682 {
5683 LM_UINT32 Value32;
5684 LM_UINT32 j, tmp1 = 0, tmp2 = 0;
5685
5686 /* Wait for access to the nvram interface before resetting. This is */
5687 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
5688 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
5689 {
5690 /* Request access to the flash interface. */
5691 LM_NVRAM_AcquireLock(pDevice);
5692 }
5693
5694 Value32 = GRC_MISC_CFG_CORE_CLOCK_RESET;
5695 if (pDevice->Flags & PCI_EXPRESS_FLAG)
5696 {
5697 if (REG_RD_OFFSET(pDevice, 0x7e2c) == 0x60) /* PCIE 1.0 system */
5698 {
5699 REG_WR_OFFSET(pDevice, 0x7e2c, 0x20);
5700 }
5701 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
5702 {
5703 /* This bit prevents PCIE link training during GRC reset */
5704 REG_WR(pDevice, Grc.MiscCfg, BIT_29); /* Write bit 29 first */
5705 Value32 |= BIT_29; /* and keep bit 29 set during GRC reset */
5706 }
5707 }
5708 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5709 {
5710 Value32 |= GRC_MISC_GPHY_KEEP_POWER_DURING_RESET;
5711 }
5712
5713 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5714 {
5715 /* Save the MSI ENABLE bit (may need to save the message as well) */
5716 tmp1 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5717 }
5718
5719 /* Global reset. */
5720 RAW_REG_WR(pDevice, Grc.MiscCfg, Value32);
5721 MM_Wait(120);
5722
5723 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
5724
5725 MM_Wait(120);
5726
5727 /* make sure we re-enable indirect accesses */
5728 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
5729 pDevice->MiscHostCtrl);
5730
5731 /* Set MAX PCI retry to zero. */
5732 Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
5733 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
5734 {
5735 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
5736 {
5737 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
5738 }
5739 }
5740 MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
5741
5742 /* Restore PCI command register. */
5743 MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
5744 pDevice->PciCommandStatusWords);
5745
5746 /* Disable PCI-X relaxed ordering bit. */
5747 MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
5748 Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
5749 MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
5750
5751 /* Enable memory arbiter */
5752 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5753 {
5754 Value32 = REG_RD(pDevice,MemArbiter.Mode);
5755 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
5756 }
5757 else
5758 {
5759 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
5760 }
5761
5762 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5763 {
5764 /* restore the MSI ENABLE bit (may need to restore the message also) */
5765 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5766 tmp2 |= (tmp1 & (1 << 16));
5767 LM_RegWr( pDevice, T3_PCI_MSI_ENABLE, tmp2, TRUE );
5768 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5769 }
5770
5771
5772 if (pDevice->ChipRevId == T3_CHIP_ID_5750_A3)
5773 {
5774 /* Because of chip bug on A3, we need to kill the CPU */
5775 LM_DisableFW(pDevice);
5776 REG_WR_OFFSET(pDevice, 0x5000, 0x400);
5777 }
5778
5779 /*
5780 * BCM4785: In order to avoid repercussions from using potentially
5781 * defective internal ROM, stop the Rx RISC CPU, which is not
5782 * required.
5783 */
5784 if (pDevice->Flags & SB_CORE_FLAG) {
5785 LM_DisableFW(pDevice);
5786 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
5787 }
5788
5789 #ifdef BIG_ENDIAN_HOST
5790 /* Reconfigure the mode register. */
5791 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
5792 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
5793 GRC_MODE_BYTE_SWAP_DATA |
5794 GRC_MODE_WORD_SWAP_DATA;
5795 #else
5796 /* Reconfigure the mode register. */
5797 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
5798 #endif
5799 REG_WR(pDevice, Grc.Mode, Value32);
5800
5801 if ((pDevice->Flags & MINI_PCI_FLAG) &&
5802 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
5803 {
5804 pDevice->ClockCtrl |= T3_PCI_CLKRUN_OUTPUT_EN;
5805 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
5806 {
5807 pDevice->ClockCtrl |= T3_PCI_FORCE_CLKRUN;
5808 }
5809 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
5810 }
5811
5812 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
5813 {
5814 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
5815 }
5816 else if(pDevice->PhyFlags & PHY_IS_FIBER)
5817 {
5818 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
5819 }
5820 else
5821 {
5822 pDevice->MacMode = 0;
5823 }
5824
5825 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
5826 REG_RD_BACK(pDevice, MacCtrl.Mode);
5827 MM_Wait(40);
5828
5829 /* BCM4785: Don't use any firmware, so don't wait */
5830 if (!pDevice->Flags & SB_CORE_FLAG) {
5831 /* Wait for the firmware to finish initialization. */
5832 for(j = 0; j < 100000; j++) {
5833 MM_Wait(10);
5834
5835 if (j < 100)
5836 continue;
5837
5838 Value32 = MEM_RD_OFFSET(pDevice, T3_FIRMWARE_MAILBOX);
5839 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE) {
5840 break;
5841 }
5842 }
5843 if ((j >= 0x100000) && (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) {
5844 /* if the boot code is not running */
5845 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS) {
5846 LM_DEVICE_BLOCK *pDevice2;
5847
5848 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
5849 pDevice2 = MM_FindPeerDev(pDevice);
5850 if (pDevice2 && !pDevice2->InitDone)
5851 REG_WR(pDevice2, Nvram.Cmd, NVRAM_CMD_RESET);
5852 } else {
5853 LM_NVRAM_ReleaseLock(pDevice);
5854 }
5855 }
5856 }
5857
5858 if ((pDevice->Flags & PCI_EXPRESS_FLAG) &&
5859 (pDevice->ChipRevId != T3_CHIP_ID_5750_A0))
5860 {
5861 /* Enable PCIE bug fix */
5862 Value32 = REG_RD_OFFSET(pDevice, 0x7c00);
5863 REG_WR_OFFSET(pDevice, 0x7c00, Value32 | BIT_25 | BIT_29);
5864 }
5865
5866 #ifdef BCM_ASF
5867 pDevice->AsfFlags = 0;
5868 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
5869
5870 if (Value32 == T3_NIC_DATA_SIG)
5871 {
5872 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
5873 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
5874 {
5875 pDevice->AsfFlags = ASF_ENABLED;
5876 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5877 {
5878 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
5879 }
5880 }
5881 }
5882 #endif
5883
5884 return LM_STATUS_SUCCESS;
5885 }
5886
5887
5888 LM_STATUS
5889 LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode)
5890 {
5891 LM_DisableFW(pDevice);
5892 LM_WritePreResetSignatures(pDevice, Mode);
5893 if (pDevice->InitDone)
5894 {
5895 LM_Abort(pDevice);
5896 }
5897 else
5898 {
5899 LM_DisableChip(pDevice);
5900 }
5901 LM_ResetChip(pDevice);
5902 LM_WriteLegacySignatures(pDevice, Mode);
5903 LM_WritePostResetSignatures(pDevice, Mode);
5904 return LM_STATUS_SUCCESS;
5905 }
5906
5907 /******************************************************************************/
5908 /* Description: */
5909 /* */
5910 /* Return: */
5911 /******************************************************************************/
5912 void
5913 LM_ServiceTxInterrupt(
5914 PLM_DEVICE_BLOCK pDevice) {
5915 PLM_PACKET pPacket;
5916 LM_UINT32 HwConIdx;
5917 LM_UINT32 SwConIdx;
5918
5919 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5920
5921 /* Get our copy of the consumer index. The buffer descriptors */
5922 /* that are in between the consumer indices are freed. */
5923 SwConIdx = pDevice->SendConIdx;
5924
5925 /* Move the packets from the TxPacketActiveQ that are sent out to */
5926 /* the TxPacketXmittedQ. Packets that are sent use the */
5927 /* descriptors that are between SwConIdx and HwConIdx. */
5928 while(SwConIdx != HwConIdx)
5929 {
5930 pPacket = pDevice->SendRing[SwConIdx];
5931 pDevice->SendRing[SwConIdx] = 0;
5932
5933 /* Set the return status. */
5934 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5935
5936 /* Put the packet in the TxPacketXmittedQ for indication later. */
5937 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5938
5939 /* Move to the next packet's BD. */
5940 SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
5941 T3_SEND_RCB_ENTRY_COUNT_MASK;
5942
5943 /* Update the number of unused BDs. */
5944 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5945
5946 /* Get the new updated HwConIdx. */
5947 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5948 } /* while */
5949
5950 /* Save the new SwConIdx. */
5951 pDevice->SendConIdx = SwConIdx;
5952
5953 } /* LM_ServiceTxInterrupt */
5954
5955
5956 #ifdef BCM_NAPI_RXPOLL
5957 /******************************************************************************/
5958 /* Description: */
5959 /* */
5960 /* Return: */
5961 /******************************************************************************/
5962 int
5963 LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit)
5964 {
5965 PLM_PACKET pPacket=NULL;
5966 PT3_RCV_BD pRcvBd;
5967 LM_UINT32 HwRcvRetProdIdx;
5968 LM_UINT32 SwRcvRetConIdx;
5969 int received = 0;
5970
5971 /* Loop thru the receive return rings for received packets. */
5972 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
5973
5974 SwRcvRetConIdx = pDevice->RcvRetConIdx;
5975 MM_RMB();
5976 while (SwRcvRetConIdx != HwRcvRetProdIdx)
5977 {
5978 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
5979
5980 /* Get the received packet descriptor. */
5981 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
5982 MM_UINT_PTR(pRcvBd->Opaque));
5983
5984 switch(pPacket->u.Rx.RcvProdRing) {
5985 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5986 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
5987 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5988 break;
5989 #endif
5990 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
5991 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5992 break;
5993 }
5994
5995 /* Check the error flag. */
5996 if(pRcvBd->ErrorFlag &&
5997 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
5998 {
5999 pPacket->PacketStatus = LM_STATUS_FAILURE;
6000
6001 pDevice->RxCounters.RxPacketErrCnt++;
6002
6003 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
6004 {
6005 pDevice->RxCounters.RxErrCrcCnt++;
6006 }
6007
6008 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
6009 {
6010 pDevice->RxCounters.RxErrCollCnt++;
6011 }
6012
6013 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
6014 {
6015 pDevice->RxCounters.RxErrLinkLostCnt++;
6016 }
6017
6018 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6019 {
6020 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6021 }
6022
6023 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6024 {
6025 pDevice->RxCounters.RxErrOddNibbleCnt++;
6026 }
6027
6028 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6029 {
6030 pDevice->RxCounters.RxErrMacAbortCnt++;
6031 }
6032
6033 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6034 {
6035 pDevice->RxCounters.RxErrShortPacketCnt++;
6036 }
6037
6038 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6039 {
6040 pDevice->RxCounters.RxErrNoResourceCnt++;
6041 }
6042
6043 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6044 {
6045 pDevice->RxCounters.RxErrLargePacketCnt++;
6046 }
6047 }
6048 else
6049 {
6050 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6051 pPacket->PacketSize = pRcvBd->Len - 4;
6052
6053 pPacket->Flags = pRcvBd->Flags;
6054 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6055 {
6056 pPacket->VlanTag = pRcvBd->VlanTag;
6057 }
6058
6059 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6060 }
6061
6062 /* Put the packet descriptor containing the received packet */
6063 /* buffer in the RxPacketReceivedQ for indication later. */
6064 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6065
6066 /* Go to the next buffer descriptor. */
6067 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6068 pDevice->RcvRetRcbEntryCountMask;
6069
6070 if (++received >= limit)
6071 {
6072 break;
6073 }
6074 } /* while */
6075
6076 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6077
6078 /* Update the receive return ring consumer index. */
6079 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6080 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6081 {
6082 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6083 }
6084 else
6085 {
6086 MM_MMIOWB();
6087 }
6088 return received;
6089 } /* LM_ServiceRxPoll */
6090 #endif /* BCM_NAPI_RXPOLL */
6091
6092
6093 /******************************************************************************/
6094 /* Description: */
6095 /* */
6096 /* Return: */
6097 /******************************************************************************/
6098 void
6099 LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice)
6100 {
6101 #ifndef BCM_NAPI_RXPOLL
6102 PLM_PACKET pPacket;
6103 PT3_RCV_BD pRcvBd;
6104 #endif
6105 LM_UINT32 HwRcvRetProdIdx;
6106 LM_UINT32 SwRcvRetConIdx;
6107
6108 /* Loop thru the receive return rings for received packets. */
6109 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
6110
6111 SwRcvRetConIdx = pDevice->RcvRetConIdx;
6112 #ifdef BCM_NAPI_RXPOLL
6113 if (!pDevice->RxPoll)
6114 {
6115 if (SwRcvRetConIdx != HwRcvRetProdIdx)
6116 {
6117 if (MM_ScheduleRxPoll(pDevice) == LM_STATUS_SUCCESS)
6118 {
6119 pDevice->RxPoll = TRUE;
6120 REG_WR(pDevice, Grc.Mode,
6121 pDevice->GrcMode | GRC_MODE_NO_INTERRUPT_ON_RECEIVE);
6122 }
6123 }
6124 }
6125 #else
6126 MM_RMB();
6127 while(SwRcvRetConIdx != HwRcvRetProdIdx)
6128 {
6129 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
6130
6131 /* Get the received packet descriptor. */
6132 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
6133 MM_UINT_PTR(pRcvBd->Opaque));
6134
6135 switch(pPacket->u.Rx.RcvProdRing) {
6136 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
6137 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
6138 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6139 break;
6140 #endif
6141 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
6142 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6143 break;
6144 }
6145
6146 /* Check the error flag. */
6147 if(pRcvBd->ErrorFlag &&
6148 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6149 {
6150 pPacket->PacketStatus = LM_STATUS_FAILURE;
6151
6152 pDevice->RxCounters.RxPacketErrCnt++;
6153
6154 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
6155 {
6156 pDevice->RxCounters.RxErrCrcCnt++;
6157 }
6158
6159 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
6160 {
6161 pDevice->RxCounters.RxErrCollCnt++;
6162 }
6163
6164 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
6165 {
6166 pDevice->RxCounters.RxErrLinkLostCnt++;
6167 }
6168
6169 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6170 {
6171 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6172 }
6173
6174 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6175 {
6176 pDevice->RxCounters.RxErrOddNibbleCnt++;
6177 }
6178
6179 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6180 {
6181 pDevice->RxCounters.RxErrMacAbortCnt++;
6182 }
6183
6184 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6185 {
6186 pDevice->RxCounters.RxErrShortPacketCnt++;
6187 }
6188
6189 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6190 {
6191 pDevice->RxCounters.RxErrNoResourceCnt++;
6192 }
6193
6194 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6195 {
6196 pDevice->RxCounters.RxErrLargePacketCnt++;
6197 }
6198 }
6199 else
6200 {
6201 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6202 pPacket->PacketSize = pRcvBd->Len - 4;
6203
6204 pPacket->Flags = pRcvBd->Flags;
6205 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6206 {
6207 pPacket->VlanTag = pRcvBd->VlanTag;
6208 }
6209
6210 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6211 }
6212
6213 /* Put the packet descriptor containing the received packet */
6214 /* buffer in the RxPacketReceivedQ for indication later. */
6215 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6216
6217 /* Go to the next buffer descriptor. */
6218 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6219 pDevice->RcvRetRcbEntryCountMask;
6220
6221 } /* while */
6222
6223 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6224
6225 /* Update the receive return ring consumer index. */
6226 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6227 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6228 {
6229 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6230 }
6231 else
6232 {
6233 MM_MMIOWB();
6234 }
6235
6236 #endif
6237 } /* LM_ServiceRxInterrupt */
6238
6239
6240
6241 /******************************************************************************/
6242 /* Description: */
6243 /* This is the interrupt event handler routine. It acknowledges all */
6244 /* pending interrupts and process all pending events. */
6245 /* */
6246 /* Return: */
6247 /* LM_STATUS_SUCCESS */
6248 /******************************************************************************/
6249 LM_STATUS
6250 LM_ServiceInterrupts(
6251 PLM_DEVICE_BLOCK pDevice)
6252 {
6253 LM_UINT32 Value32;
6254 int ServicePhyInt = FALSE;
6255
6256 /* Setup the phy chip whenever the link status changes. */
6257 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
6258 {
6259 Value32 = REG_RD(pDevice, MacCtrl.Status);
6260 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6261 {
6262 if (Value32 & MAC_STATUS_MI_INTERRUPT)
6263 {
6264 ServicePhyInt = TRUE;
6265 }
6266 }
6267 else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
6268 {
6269 ServicePhyInt = TRUE;
6270 }
6271 }
6272 else
6273 {
6274 if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
6275 {
6276 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
6277 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
6278 ServicePhyInt = TRUE;
6279 }
6280 }
6281 #ifdef INCLUDE_TBI_SUPPORT
6282 if (pDevice->IgnoreTbiLinkChange == TRUE)
6283 {
6284 ServicePhyInt = FALSE;
6285 }
6286 #endif
6287 if (ServicePhyInt == TRUE)
6288 {
6289 MM_ACQUIRE_PHY_LOCK_IN_IRQ(pDevice);
6290 LM_SetupPhy(pDevice);
6291 MM_RELEASE_PHY_LOCK_IN_IRQ(pDevice);
6292 }
6293
6294 /* Service receive and transmit interrupts. */
6295 LM_ServiceRxInterrupt(pDevice);
6296 LM_ServiceTxInterrupt(pDevice);
6297
6298 #ifndef BCM_NAPI_RXPOLL
6299 /* No spinlock for this queue since this routine is serialized. */
6300 if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
6301 {
6302 /* Indicate receive packets. */
6303 MM_IndicateRxPackets(pDevice);
6304 }
6305 #endif
6306
6307 /* No spinlock for this queue since this routine is serialized. */
6308 if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
6309 {
6310 MM_IndicateTxPackets(pDevice);
6311 }
6312
6313 return LM_STATUS_SUCCESS;
6314 } /* LM_ServiceInterrupts */
6315
6316
6317 /******************************************************************************/
6318 /* Description: Add a Multicast address. Note that MC addresses, once added, */
6319 /* cannot be individually deleted. All addresses must be */
6320 /* cleared. */
6321 /* */
6322 /* Return: */
6323 /******************************************************************************/
6324 LM_STATUS
6325 LM_MulticastAdd(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6326 {
6327
6328 LM_UINT32 RegIndex;
6329 LM_UINT32 Bitpos;
6330 LM_UINT32 Crc32;
6331
6332 Crc32 = ComputeCrc32(pMcAddress, ETHERNET_ADDRESS_SIZE);
6333
6334 /* The most significant 7 bits of the CRC32 (no inversion), */
6335 /* are used to index into one of the possible 128 bit positions. */
6336 Bitpos = ~Crc32 & 0x7f;
6337
6338 /* Hash register index. */
6339 RegIndex = (Bitpos & 0x60) >> 5;
6340
6341 /* Bit to turn on within a hash register. */
6342 Bitpos &= 0x1f;
6343
6344 /* Enable the multicast bit. */
6345 pDevice->MulticastHash[RegIndex] |= (1 << Bitpos);
6346
6347 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
6348
6349 return LM_STATUS_SUCCESS;
6350 }
6351
6352
6353 /******************************************************************************/
6354 /* Description: */
6355 /* */
6356 /* Return: */
6357 /******************************************************************************/
6358 LM_STATUS
6359 LM_MulticastDel(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6360 {
6361 return LM_STATUS_FAILURE;
6362 } /* LM_MulticastDel */
6363
6364
6365
6366 /******************************************************************************/
6367 /* Description: */
6368 /* */
6369 /* Return: */
6370 /******************************************************************************/
6371 LM_STATUS
6372 LM_MulticastClear(LM_DEVICE_BLOCK *pDevice)
6373 {
6374 int i;
6375
6376 for (i = 0; i < 4; i++)
6377 {
6378 pDevice->MulticastHash[i] = 0;
6379 }
6380 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
6381
6382 return LM_STATUS_SUCCESS;
6383 } /* LM_MulticastClear */
6384
6385
6386
6387 /******************************************************************************/
6388 /* Description: */
6389 /* */
6390 /* Return: */
6391 /******************************************************************************/
6392 LM_STATUS
6393 LM_SetMacAddress(
6394 PLM_DEVICE_BLOCK pDevice,
6395 PLM_UINT8 pMacAddress)
6396 {
6397 LM_UINT32 j;
6398
6399 for(j = 0; j < 4; j++)
6400 {
6401 REG_WR(pDevice, MacCtrl.MacAddr[j].High,
6402 (pMacAddress[0] << 8) | pMacAddress[1]);
6403 REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
6404 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6405 (pMacAddress[4] << 8) | pMacAddress[5]);
6406 }
6407
6408 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
6409 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
6410 {
6411 for (j = 0; j < 12; j++)
6412 {
6413 REG_WR(pDevice, MacCtrl.MacAddrExt[j].High,
6414 (pMacAddress[0] << 8) | pMacAddress[1]);
6415 REG_WR(pDevice, MacCtrl.MacAddrExt[j].Low,
6416 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6417 (pMacAddress[4] << 8) | pMacAddress[5]);
6418 }
6419 }
6420 return LM_STATUS_SUCCESS;
6421 }
6422
6423 LM_VOID
6424 LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice)
6425 {
6426 /* Turn off tap power management. */
6427 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6428 {
6429 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
6430 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
6431 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
6432 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
6433 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
6434 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6435 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
6436 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6437 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
6438 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
6439 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
6440
6441 MM_Wait(40);
6442 }
6443 }
6444
6445 /******************************************************************************/
6446 /* Description: */
6447 /* */
6448 /* Return: */
6449 /* LM_STATUS_LINK_ACTIVE */
6450 /* LM_STATUS_LINK_DOWN */
6451 /******************************************************************************/
6452 static LM_STATUS
6453 LM_InitBcm540xPhy(
6454 PLM_DEVICE_BLOCK pDevice)
6455 {
6456 LM_LINE_SPEED CurrentLineSpeed;
6457 LM_DUPLEX_MODE CurrentDuplexMode;
6458 LM_STATUS CurrentLinkStatus;
6459 LM_UINT32 Value32;
6460 LM_UINT32 j;
6461 robo_info_t *robo;
6462
6463 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
6464
6465 if ((pDevice->PhyFlags & PHY_RESET_ON_LINKDOWN) &&
6466 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE))
6467 {
6468 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6469 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6470 if(!(Value32 & PHY_STATUS_LINK_PASS))
6471 {
6472 LM_ResetPhy(pDevice);
6473 }
6474 }
6475 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6476 {
6477 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6478 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6479
6480 if(!pDevice->InitDone)
6481 {
6482 Value32 = 0;
6483 }
6484
6485 if(!(Value32 & PHY_STATUS_LINK_PASS))
6486 {
6487 LM_PhyTapPowerMgmt(pDevice);
6488
6489 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6490 for(j = 0; j < 1000; j++)
6491 {
6492 MM_Wait(10);
6493
6494 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6495 if(Value32 & PHY_STATUS_LINK_PASS)
6496 {
6497 MM_Wait(40);
6498 break;
6499 }
6500 }
6501
6502 if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
6503 {
6504 if(!(Value32 & PHY_STATUS_LINK_PASS) &&
6505 (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
6506 {
6507 LM_ResetPhy(pDevice);
6508 }
6509 }
6510 }
6511 }
6512 else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
6513 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
6514 {
6515 LM_WritePhy(pDevice, 0x15, 0x0a75);
6516 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6517 LM_WritePhy(pDevice, 0x1c, 0x8d68);
6518 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6519 }
6520
6521 /* Acknowledge interrupts. */
6522 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6523 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6524
6525 /* Configure the interrupt mask. */
6526 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6527 {
6528 LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
6529 }
6530
6531 /* Configure PHY led mode. */
6532 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
6533 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
6534 {
6535 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_1)
6536 {
6537 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
6538 BCM540X_EXT_CTRL_LINK3_LED_MODE);
6539 }
6540 else
6541 {
6542 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
6543 }
6544 }
6545 else if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
6546 {
6547 /*
6548 ** Set up the 'link' LED for the 4785+5461 combo,
6549 ** using the INTR/ENERGYDET pin (on the BCM4785 bringup board).
6550 */
6551 LM_WritePhy( pDevice,
6552 BCM546X_1c_SHADOW_REG,
6553 (BCM546X_1c_SPR_CTRL_2 | BCM546X_1c_WR_EN | BCM546X_1c_SP2_NRG_DET) );
6554
6555 /*
6556 ** Set up the LINK LED mode for the 4785+5461 combo,
6557 ** using the 5461 SLAVE/ANEN pin (on the BCM4785 bringup board) as
6558 ** active low link status (phy ready) feedback to the 4785
6559 */
6560 LM_WritePhy( pDevice,
6561 BCM546X_1c_SHADOW_REG,
6562 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN | BCM546X_1c_SP1_LINK_LED) );
6563 }
6564
6565 if (pDevice->PhyFlags & PHY_CAPACITIVE_COUPLING)
6566 {
6567 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4007);
6568 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &Value32);
6569 if (!(Value32 & BIT_10))
6570 {
6571 /* set the bit and re-link */
6572 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, Value32 | BIT_10);
6573 return LM_STATUS_LINK_SETTING_MISMATCH;
6574 }
6575 }
6576
6577 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6578
6579 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
6580 B57_INFO(("Force to active link of 1000 MBPS and full duplex mod.\n"));
6581 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6582
6583 /* Set the line speed based on the robo switch type */
6584 robo = ((PUM_DEVICE_BLOCK)pDevice)->robo;
6585 if (robo->devid == DEVID5325)
6586 {
6587 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6588 }
6589 else
6590 {
6591 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6592 }
6593 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6594
6595 /* Save line settings. */
6596 pDevice->LineSpeed = CurrentLineSpeed;
6597 pDevice->DuplexMode = CurrentDuplexMode;
6598 } else {
6599
6600 /* Get current link and duplex mode. */
6601 for(j = 0; j < 100; j++)
6602 {
6603 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6604 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6605
6606 if(Value32 & PHY_STATUS_LINK_PASS)
6607 {
6608 break;
6609 }
6610 MM_Wait(40);
6611 }
6612
6613 if(Value32 & PHY_STATUS_LINK_PASS)
6614 {
6615
6616 /* Determine the current line and duplex settings. */
6617 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6618 for(j = 0; j < 2000; j++)
6619 {
6620 MM_Wait(10);
6621
6622 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6623 if(Value32)
6624 {
6625 break;
6626 }
6627 }
6628
6629 switch(Value32 & BCM540X_AUX_SPEED_MASK)
6630 {
6631 case BCM540X_AUX_10BASET_HD:
6632 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6633 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6634 break;
6635
6636 case BCM540X_AUX_10BASET_FD:
6637 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6638 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6639 break;
6640
6641 case BCM540X_AUX_100BASETX_HD:
6642 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6643 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6644 break;
6645
6646 case BCM540X_AUX_100BASETX_FD:
6647 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6648 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6649 break;
6650
6651 case BCM540X_AUX_100BASET_HD:
6652 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6653 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6654 break;
6655
6656 case BCM540X_AUX_100BASET_FD:
6657 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6658 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6659 break;
6660
6661 default:
6662
6663 CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
6664 CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
6665 break;
6666 }
6667
6668 /* Make sure we are in auto-neg mode. */
6669 for (j = 0; j < 200; j++)
6670 {
6671 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6672 if(Value32 && Value32 != 0x7fff)
6673 {
6674 break;
6675 }
6676
6677 if(Value32 == 0 &&
6678 pDevice->RequestedLineSpeed == LM_LINE_SPEED_10MBPS &&
6679 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_HALF)
6680 {
6681 break;
6682 }
6683
6684 MM_Wait(10);
6685 }
6686
6687 /* Use the current line settings for "auto" mode. */
6688 if(pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
6689 {
6690 if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
6691 {
6692 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6693
6694 /* We may be exiting low power mode and the link is in */
6695 /* 10mb. In this case, we need to restart autoneg. */
6696
6697 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
6698 {
6699 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6700 }
6701 }
6702 else
6703 {
6704 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6705 }
6706 }
6707 else
6708 {
6709 /* Force line settings. */
6710 /* Use the current setting if it matches the user's requested */
6711 /* setting. */
6712 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6713 if((pDevice->LineSpeed == CurrentLineSpeed) &&
6714 (pDevice->DuplexMode == CurrentDuplexMode))
6715 {
6716 if ((pDevice->DisableAutoNeg &&
6717 !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
6718 (!pDevice->DisableAutoNeg &&
6719 (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
6720 {
6721 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6722 }
6723 else
6724 {
6725 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6726 }
6727 }
6728 else
6729 {
6730 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6731 }
6732 }
6733
6734 /* Save line settings. */
6735 pDevice->LineSpeed = CurrentLineSpeed;
6736 pDevice->DuplexMode = CurrentDuplexMode;
6737 }
6738 }
6739
6740 return CurrentLinkStatus;
6741 } /* LM_InitBcm540xPhy */
6742
6743 /******************************************************************************/
6744 /* Description: */
6745 /* */
6746 /* Return: */
6747 /******************************************************************************/
6748 LM_STATUS
6749 LM_SetFlowControl(
6750 PLM_DEVICE_BLOCK pDevice,
6751 LM_UINT32 LocalPhyAd,
6752 LM_UINT32 RemotePhyAd)
6753 {
6754 LM_FLOW_CONTROL FlowCap;
6755
6756 /* Resolve flow control. */
6757 FlowCap = LM_FLOW_CONTROL_NONE;
6758
6759 /* See Table 28B-3 of 802.3ab-1999 spec. */
6760 if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
6761 {
6762 if(pDevice->PhyFlags & PHY_IS_FIBER){
6763 LocalPhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6764 PHY_AN_AD_PAUSE_CAPABLE);
6765 RemotePhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6766 PHY_AN_AD_PAUSE_CAPABLE);
6767
6768 if (LocalPhyAd & PHY_AN_AD_1000XPAUSE)
6769 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
6770 if (LocalPhyAd & PHY_AN_AD_1000XPSE_ASYM)
6771 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
6772 if (RemotePhyAd & PHY_AN_AD_1000XPAUSE)
6773 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6774 if (RemotePhyAd & PHY_AN_AD_1000XPSE_ASYM)
6775 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6776 }
6777
6778 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6779 {
6780 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6781 {
6782 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6783 {
6784 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6785 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6786 }
6787 else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
6788 {
6789 FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
6790 }
6791 }
6792 else
6793 {
6794 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6795 {
6796 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6797 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6798 }
6799 }
6800 }
6801 else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6802 {
6803 if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
6804 (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
6805 {
6806 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6807 }
6808 }
6809 }
6810 else
6811 {
6812 FlowCap = pDevice->FlowControlCap;
6813 }
6814
6815 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
6816
6817 /* Enable/disable rx PAUSE. */
6818 pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
6819 if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
6820 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6821 pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
6822 {
6823 pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
6824 pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
6825
6826 }
6827 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
6828
6829 /* Enable/disable tx PAUSE. */
6830 pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
6831 if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
6832 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6833 pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
6834 {
6835 pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6836 pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
6837
6838 }
6839 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
6840
6841 return LM_STATUS_SUCCESS;
6842 }
6843
6844
6845 #ifdef INCLUDE_TBI_SUPPORT
6846 /******************************************************************************/
6847 /* Description: */
6848 /* */
6849 /* Return: */
6850 /******************************************************************************/
6851 STATIC LM_STATUS
6852 LM_InitBcm800xPhy(
6853 PLM_DEVICE_BLOCK pDevice)
6854 {
6855 LM_UINT32 Value32;
6856 LM_UINT32 j;
6857
6858
6859 Value32 = REG_RD(pDevice, MacCtrl.Status);
6860
6861 /* Reset the SERDES during init and when we have link. */
6862 if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
6863 {
6864 /* Set PLL lock range. */
6865 LM_WritePhy(pDevice, 0x16, 0x8007);
6866
6867 /* Software reset. */
6868 LM_WritePhy(pDevice, 0x00, 0x8000);
6869
6870 /* Wait for reset to complete. */
6871 for(j = 0; j < 500; j++)
6872 {
6873 MM_Wait(10);
6874 }
6875
6876 /* Config mode; seletct PMA/Ch 1 regs. */
6877 LM_WritePhy(pDevice, 0x10, 0x8411);
6878
6879 /* Enable auto-lock and comdet, select txclk for tx. */
6880 LM_WritePhy(pDevice, 0x11, 0x0a10);
6881
6882 LM_WritePhy(pDevice, 0x18, 0x00a0);
6883 LM_WritePhy(pDevice, 0x16, 0x41ff);
6884
6885 /* Assert and deassert POR. */
6886 LM_WritePhy(pDevice, 0x13, 0x0400);
6887 MM_Wait(40);
6888 LM_WritePhy(pDevice, 0x13, 0x0000);
6889
6890 LM_WritePhy(pDevice, 0x11, 0x0a50);
6891 MM_Wait(40);
6892 LM_WritePhy(pDevice, 0x11, 0x0a10);
6893
6894 /* Delay for signal to stabilize. */
6895 for(j = 0; j < 15000; j++)
6896 {
6897 MM_Wait(10);
6898 }
6899
6900 /* Deselect the channel register so we can read the PHY id later. */
6901 LM_WritePhy(pDevice, 0x10, 0x8011);
6902 }
6903
6904 return LM_STATUS_SUCCESS;
6905 }
6906
6907
6908
6909 /******************************************************************************/
6910 /* Description: */
6911 /* */
6912 /* Return: */
6913 /******************************************************************************/
6914 STATIC LM_STATUS
6915 LM_SetupFiberPhy(
6916 PLM_DEVICE_BLOCK pDevice)
6917 {
6918 LM_STATUS CurrentLinkStatus;
6919 AUTONEG_STATUS AnStatus = 0;
6920 LM_UINT32 Value32;
6921 LM_UINT32 Cnt;
6922 LM_UINT32 j, k;
6923 LM_UINT32 MacStatus, RemotePhyAd, LocalPhyAd;
6924 LM_FLOW_CONTROL PreviousFlowControl = pDevice->FlowControl;
6925
6926
6927 if (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE)
6928 {
6929 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
6930 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
6931 return LM_STATUS_SUCCESS;
6932 }
6933
6934
6935 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
6936 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && pDevice->InitDone)
6937 {
6938 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6939 if ((MacStatus & (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED |
6940 MAC_STATUS_CFG_CHANGED | MAC_STATUS_RECEIVING_CFG))
6941 == (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED))
6942 {
6943
6944 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
6945 MAC_STATUS_CFG_CHANGED);
6946 return LM_STATUS_SUCCESS;
6947 }
6948 }
6949 pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
6950
6951 /* Initialize the send_config register. */
6952 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
6953
6954 pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
6955 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
6956 MM_Wait(10);
6957
6958 /* Initialize the BCM8002 SERDES PHY. */
6959 switch(pDevice->PhyId & PHY_ID_MASK)
6960 {
6961 case PHY_BCM8002_PHY_ID:
6962 LM_InitBcm800xPhy(pDevice);
6963 break;
6964
6965 default:
6966 break;
6967 }
6968
6969 /* Enable link change interrupt. */
6970 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
6971
6972 /* Default to link down. */
6973 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6974
6975 /* Get the link status. */
6976 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6977
6978 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
6979 {
6980 LM_UINT32 SgDigCtrl, SgDigStatus;
6981 LM_UINT32 SerdesCfg = 0;
6982 LM_UINT32 ExpectedSgDigCtrl = 0;
6983 LM_UINT32 WorkAround = 0;
6984 LM_UINT32 PortA = 1;
6985
6986 if ((pDevice->ChipRevId != T3_CHIP_ID_5704_A0) &&
6987 (pDevice->ChipRevId != T3_CHIP_ID_5704_A1))
6988 {
6989 WorkAround = 1;
6990 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
6991 {
6992 PortA = 0;
6993 }
6994
6995 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
6996 {
6997 /* Save voltage reg bits & bits 14:0 */
6998 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
6999 (BIT_23 | BIT_22 | BIT_21 | BIT_20 | 0x7fff );
7000
7001 }
7002 else
7003 {
7004 /* preserve the voltage regulator bits */
7005 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
7006 (BIT_23 | BIT_22 | BIT_21 | BIT_20);
7007 }
7008 }
7009 SgDigCtrl = REG_RD(pDevice, MacCtrl.SgDigControl);
7010 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
7011 (pDevice->DisableAutoNeg == FALSE))
7012 {
7013
7014 ExpectedSgDigCtrl = 0x81388400;
7015 LocalPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7016 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
7017 {
7018 ExpectedSgDigCtrl |= BIT_11;
7019 }
7020 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
7021 {
7022 ExpectedSgDigCtrl |= BIT_12;
7023 }
7024 if (SgDigCtrl != ExpectedSgDigCtrl)
7025 {
7026 if (WorkAround)
7027 {
7028 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7029 {
7030 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011000 | SerdesCfg);
7031 }
7032 else
7033 {
7034 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011880 | SerdesCfg);
7035 }
7036 }
7037 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl |
7038 BIT_30);
7039 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
7040 MM_Wait(5);
7041 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl);
7042 pDevice->AutoNegJustInited = TRUE;
7043 }
7044 /* If autoneg is off, you only get SD when link is up */
7045 else if(MacStatus & (MAC_STATUS_PCS_SYNCED |
7046 MAC_STATUS_SIGNAL_DETECTED))
7047 {
7048 SgDigStatus = REG_RD(pDevice, MacCtrl.SgDigStatus);
7049 if ((SgDigStatus & BIT_1) &&
7050 (MacStatus & MAC_STATUS_PCS_SYNCED))
7051 {
7052 /* autoneg. completed */
7053 RemotePhyAd = 0;
7054 if(SgDigStatus & BIT_19)
7055 {
7056 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
7057 }
7058
7059 if(SgDigStatus & BIT_20)
7060 {
7061 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7062 }
7063
7064 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7065 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7066 pDevice->AutoNegJustInited = FALSE;
7067 }
7068 else if (!(SgDigStatus & BIT_1))
7069 {
7070 if (pDevice->AutoNegJustInited == TRUE)
7071 {
7072 /* we may be checking too soon, so check again */
7073 /* at the next poll interval */
7074 pDevice->AutoNegJustInited = FALSE;
7075 }
7076 else
7077 {
7078 /* autoneg. failed */
7079 if (WorkAround)
7080 {
7081 if (PortA)
7082 {
7083 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7084 {
7085 REG_WR(pDevice, MacCtrl.SerdesCfg,
7086 0xc010000 | (SerdesCfg & ~0x00001000));
7087 }
7088 else
7089 {
7090 REG_WR(pDevice, MacCtrl.SerdesCfg,
7091 0xc010880 | SerdesCfg);
7092 }
7093 }
7094 else
7095 {
7096 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7097 {
7098 REG_WR(pDevice, MacCtrl.SerdesCfg,
7099 0x4010000 | (SerdesCfg & ~0x00001000));
7100 }
7101 else
7102 {
7103 REG_WR(pDevice, MacCtrl.SerdesCfg,
7104 0x4010880 | SerdesCfg);
7105 }
7106 }
7107 }
7108 /* turn off autoneg. to allow traffic to pass */
7109 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7110 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
7111 MM_Wait(40);
7112 MacStatus = REG_RD(pDevice, MacCtrl.Status);
7113 if ((MacStatus & MAC_STATUS_PCS_SYNCED) && !(MacStatus & MAC_STATUS_RECEIVING_CFG))
7114 {
7115 LM_SetFlowControl(pDevice, 0, 0);
7116 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7117 }
7118 }
7119 }
7120 }
7121 }
7122 else
7123 {
7124 if (SgDigCtrl & BIT_31) {
7125 if (WorkAround)
7126 {
7127 if (PortA)
7128 {
7129
7130 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7131 {
7132 REG_WR(pDevice, MacCtrl.SerdesCfg,
7133 0xc010000 | (SerdesCfg & ~0x00001000));
7134 }
7135 else
7136 {
7137 REG_WR(pDevice, MacCtrl.SerdesCfg,
7138 0xc010880 | SerdesCfg);
7139 }
7140 }
7141 else
7142 {
7143 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7144 {
7145 REG_WR(pDevice, MacCtrl.SerdesCfg,
7146 0x4010000 | (SerdesCfg & ~0x00001000));
7147 }
7148 else
7149 {
7150 REG_WR(pDevice, MacCtrl.SerdesCfg,
7151 0x4010880 | SerdesCfg);
7152 }
7153 }
7154 }
7155 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7156 }
7157 if(MacStatus & MAC_STATUS_PCS_SYNCED)
7158 {
7159 LM_SetFlowControl(pDevice, 0, 0);
7160 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7161 }
7162 }
7163 }
7164 else if(MacStatus & MAC_STATUS_PCS_SYNCED)
7165 {
7166 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
7167 (pDevice->DisableAutoNeg == FALSE))
7168 {
7169 /* auto-negotiation mode. */
7170 /* Initialize the autoneg default capaiblities. */
7171 AutonegInit(&pDevice->AnInfo);
7172
7173 /* Set the context pointer to point to the main device structure. */
7174 pDevice->AnInfo.pContext = pDevice;
7175
7176 /* Setup flow control advertisement register. */
7177 Value32 = GetPhyAdFlowCntrlSettings(pDevice);
7178 if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
7179 {
7180 pDevice->AnInfo.mr_adv_sym_pause = 1;
7181 }
7182 else
7183 {
7184 pDevice->AnInfo.mr_adv_sym_pause = 0;
7185 }
7186
7187 if(Value32 & PHY_AN_AD_ASYM_PAUSE)
7188 {
7189 pDevice->AnInfo.mr_adv_asym_pause = 1;
7190 }
7191 else
7192 {
7193 pDevice->AnInfo.mr_adv_asym_pause = 0;
7194 }
7195
7196 /* Try to autoneg up to six times. */
7197 if (pDevice->IgnoreTbiLinkChange)
7198 {
7199 Cnt = 1;
7200 }
7201 else
7202 {
7203 Cnt = 6;
7204 }
7205 for (j = 0; j < Cnt; j++)
7206 {
7207 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
7208
7209 Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
7210 REG_WR(pDevice, MacCtrl.Mode, Value32);
7211 REG_RD_BACK(pDevice, MacCtrl.Mode);
7212 MM_Wait(20);
7213
7214 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7215 MAC_MODE_SEND_CONFIGS);
7216 REG_RD_BACK(pDevice, MacCtrl.Mode);
7217
7218 MM_Wait(20);
7219
7220 pDevice->AnInfo.State = AN_STATE_UNKNOWN;
7221 pDevice->AnInfo.CurrentTime_us = 0;
7222
7223 REG_WR(pDevice, Grc.Timer, 0);
7224 for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
7225 (k < 75000); k++)
7226 {
7227 AnStatus = Autoneg8023z(&pDevice->AnInfo);
7228
7229 if((AnStatus == AUTONEG_STATUS_DONE) ||
7230 (AnStatus == AUTONEG_STATUS_FAILED))
7231 {
7232 break;
7233 }
7234
7235 pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
7236
7237 }
7238 if((AnStatus == AUTONEG_STATUS_DONE) ||
7239 (AnStatus == AUTONEG_STATUS_FAILED))
7240 {
7241 break;
7242 }
7243 if (j >= 1)
7244 {
7245 if (!(REG_RD(pDevice, MacCtrl.Status) &
7246 MAC_STATUS_PCS_SYNCED)) {
7247 break;
7248 }
7249 }
7250 }
7251
7252 /* Stop sending configs. */
7253 MM_AnTxIdle(&pDevice->AnInfo);
7254
7255 /* Resolve flow control settings. */
7256 if((AnStatus == AUTONEG_STATUS_DONE) &&
7257 pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
7258 pDevice->AnInfo.mr_lp_adv_full_duplex)
7259 {
7260 LM_UINT32 RemotePhyAd;
7261 LM_UINT32 LocalPhyAd;
7262
7263 LocalPhyAd = 0;
7264 if(pDevice->AnInfo.mr_adv_sym_pause)
7265 {
7266 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
7267 }
7268
7269 if(pDevice->AnInfo.mr_adv_asym_pause)
7270 {
7271 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
7272 }
7273
7274 RemotePhyAd = 0;
7275 if(pDevice->AnInfo.mr_lp_adv_sym_pause)
7276 {
7277 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
7278 }
7279
7280 if(pDevice->AnInfo.mr_lp_adv_asym_pause)
7281 {
7282 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7283 }
7284
7285 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7286
7287 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7288 }
7289 else
7290 {
7291 LM_SetFlowControl(pDevice, 0, 0);
7292 }
7293 for (j = 0; j < 30; j++)
7294 {
7295 MM_Wait(20);
7296 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7297 MAC_STATUS_CFG_CHANGED);
7298 REG_RD_BACK(pDevice, MacCtrl.Status);
7299 MM_Wait(20);
7300 if ((REG_RD(pDevice, MacCtrl.Status) &
7301 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7302 break;
7303 }
7304 if (pDevice->TbiFlags & TBI_POLLING_FLAGS)
7305 {
7306 Value32 = REG_RD(pDevice, MacCtrl.Status);
7307 if (Value32 & MAC_STATUS_RECEIVING_CFG)
7308 {
7309 pDevice->IgnoreTbiLinkChange = TRUE;
7310 }
7311 else if (pDevice->TbiFlags & TBI_POLLING_INTR_FLAG)
7312 {
7313 pDevice->IgnoreTbiLinkChange = FALSE;
7314 }
7315 }
7316 Value32 = REG_RD(pDevice, MacCtrl.Status);
7317 if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
7318 (Value32 & MAC_STATUS_PCS_SYNCED) &&
7319 ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
7320 {
7321 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7322 }
7323 }
7324 else
7325 {
7326 /* We are forcing line speed. */
7327 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7328 LM_SetFlowControl(pDevice, 0, 0);
7329
7330 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7331 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7332 MAC_MODE_SEND_CONFIGS);
7333 }
7334 }
7335 /* Set the link polarity bit. */
7336 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7337 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7338
7339 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7340 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7341
7342 for (j = 0; j < 100; j++)
7343 {
7344 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7345 MAC_STATUS_CFG_CHANGED);
7346 REG_RD_BACK(pDevice, MacCtrl.Status);
7347 MM_Wait(5);
7348 if ((REG_RD(pDevice, MacCtrl.Status) &
7349 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7350 break;
7351 }
7352
7353 Value32 = REG_RD(pDevice, MacCtrl.Status);
7354 if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
7355 {
7356 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7357 if (pDevice->DisableAutoNeg == FALSE)
7358 {
7359 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7360 MAC_MODE_SEND_CONFIGS);
7361 REG_RD_BACK(pDevice, MacCtrl.Mode);
7362 MM_Wait(1);
7363 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7364 }
7365 }
7366
7367 /* Initialize the current link status. */
7368 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7369 {
7370 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7371 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7372 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7373 LED_CTRL_OVERRIDE_LINK_LED |
7374 LED_CTRL_1000MBPS_LED_ON);
7375 }
7376 else
7377 {
7378 pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
7379 pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
7380 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7381 LED_CTRL_OVERRIDE_LINK_LED |
7382 LED_CTRL_OVERRIDE_TRAFFIC_LED);
7383 }
7384
7385 /* Indicate link status. */
7386 if ((pDevice->LinkStatus != CurrentLinkStatus) ||
7387 ((CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7388 (PreviousFlowControl != pDevice->FlowControl)))
7389 {
7390 pDevice->LinkStatus = CurrentLinkStatus;
7391 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7392 }
7393
7394 return LM_STATUS_SUCCESS;
7395 }
7396 #endif /* INCLUDE_TBI_SUPPORT */
7397
7398
7399 /******************************************************************************/
7400 /* Description: */
7401 /* */
7402 /* Return: */
7403 /******************************************************************************/
7404 LM_STATUS
7405 LM_SetupCopperPhy(
7406 PLM_DEVICE_BLOCK pDevice)
7407 {
7408 LM_STATUS CurrentLinkStatus;
7409 LM_UINT32 Value32;
7410
7411 /* Assume there is not link first. */
7412 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7413
7414 /* Disable phy link change attention. */
7415 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7416
7417 /* Clear link change attention. */
7418 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7419 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7420 MAC_STATUS_LINK_STATE_CHANGED);
7421
7422 /* Disable auto-polling for the moment. */
7423 pDevice->MiMode = 0xc0000;
7424 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7425 REG_RD_BACK(pDevice, MacCtrl.MiMode);
7426 MM_Wait(40);
7427
7428 /* Determine the requested line speed and duplex. */
7429 pDevice->OldLineSpeed = pDevice->LineSpeed;
7430 /* Set line and duplex only if we don't have a Robo switch */
7431 if (!(pDevice->Flags & ROBO_SWITCH_FLAG)) {
7432 pDevice->LineSpeed = pDevice->RequestedLineSpeed;
7433 pDevice->DuplexMode = pDevice->RequestedDuplexMode;
7434 }
7435
7436 /* Set the phy to loopback mode. */
7437 if ((pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE) ||
7438 (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE))
7439 {
7440 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7441 if(!(Value32 & PHY_CTRL_LOOPBACK_MODE) &&
7442 (pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE))
7443 {
7444 /* Disable link change and PHY interrupts. */
7445 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7446
7447 /* Clear link change attention. */
7448 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7449 MAC_STATUS_CFG_CHANGED);
7450
7451 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7452 MM_Wait(40);
7453
7454 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7455 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7456 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
7457 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
7458 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705 ||
7459 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 &&
7460 (pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID))
7461 {
7462 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7463 }
7464
7465 /* Prevent the interrupt handling from being called. */
7466 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7467 (pDevice->pStatusBlkVirt->Status &
7468 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7469
7470 /* GMII interface. */
7471 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7472 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7473 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7474 REG_RD_BACK(pDevice, MacCtrl.Mode);
7475 MM_Wait(40);
7476
7477 /* Configure PHY led mode. */
7478 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7479 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
7480 {
7481 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
7482 BCM540X_EXT_CTRL_LINK3_LED_MODE);
7483 MM_Wait(40);
7484 }
7485
7486 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7487 {
7488 int j = 0;
7489
7490 while (REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)
7491 {
7492 MM_Wait(40);
7493 j++;
7494 if (j > 20)
7495 break;
7496 }
7497
7498 Value32 = DMA_WRITE_MODE_ENABLE |
7499 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
7500 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
7501 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
7502 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
7503 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
7504 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
7505 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
7506 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
7507 REG_WR(pDevice, DmaWrite.Mode, Value32);
7508 }
7509 }
7510
7511 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7512 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7513
7514 return LM_STATUS_SUCCESS;
7515 }
7516
7517 /* For Robo switch read PHY_CTRL_REG value as zero */
7518 if (pDevice->Flags & ROBO_SWITCH_FLAG)
7519 Value32 = 0;
7520 else
7521 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7522
7523 if(Value32 & PHY_CTRL_LOOPBACK_MODE)
7524 {
7525 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7526
7527 /* Re-enable link change interrupt. This was disabled when we */
7528 /* enter loopback mode. */
7529 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7530 {
7531 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7532 }
7533 else
7534 {
7535 REG_WR(pDevice, MacCtrl.MacEvent,
7536 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7537 }
7538 }
7539 else
7540 {
7541 /* Initialize the phy chip. */
7542 CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
7543 }
7544
7545 if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
7546 {
7547 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7548 }
7549
7550 /* Setup flow control. */
7551 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
7552 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7553 {
7554 LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
7555
7556 FlowCap = LM_FLOW_CONTROL_NONE;
7557
7558 if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
7559 {
7560 if(pDevice->DisableAutoNeg == FALSE ||
7561 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
7562 {
7563 LM_UINT32 ExpectedPhyAd;
7564 LM_UINT32 LocalPhyAd;
7565 LM_UINT32 RemotePhyAd;
7566
7567 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
7568 pDevice->advertising = LocalPhyAd;
7569 LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
7570
7571 ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7572
7573 if(LocalPhyAd != ExpectedPhyAd)
7574 {
7575 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7576 }
7577 else
7578 {
7579 LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
7580 &RemotePhyAd);
7581
7582 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7583 }
7584 }
7585 else
7586 {
7587 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7588 LM_SetFlowControl(pDevice, 0, 0);
7589 }
7590 }
7591 }
7592
7593 if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
7594 {
7595 LM_ForceAutoNeg(pDevice);
7596
7597 /* If we force line speed, we make get link right away. */
7598 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7599 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7600 if(Value32 & PHY_STATUS_LINK_PASS)
7601 {
7602 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7603 }
7604 }
7605
7606 /* GMII interface. */
7607 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7608 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7609 {
7610 if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
7611 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7612 {
7613 pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
7614 }
7615 else
7616 {
7617 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7618 }
7619 }
7620 else {
7621 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7622 }
7623
7624 /* In order for the 5750 core in BCM4785 chip to work properly
7625 * in RGMII mode, the Led Control Register must be set up.
7626 */
7627 if (pDevice->Flags & RGMII_MODE_FLAG)
7628 {
7629 LM_UINT32 LedCtrl_Reg;
7630
7631 LedCtrl_Reg = REG_RD(pDevice, MacCtrl.LedCtrl);
7632 LedCtrl_Reg &= ~(LED_CTRL_1000MBPS_LED_ON | LED_CTRL_100MBPS_LED_ON);
7633
7634 if(pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7635 LedCtrl_Reg |= LED_CTRL_OVERRIDE_LINK_LED;
7636 else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS)
7637 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_100MBPS_LED_ON);
7638 else /* LM_LINE_SPEED_1000MBPS */
7639 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON);
7640
7641 REG_WR(pDevice, MacCtrl.LedCtrl, LedCtrl_Reg);
7642
7643 MM_Wait(40);
7644 }
7645
7646 /* Set the MAC to operate in the appropriate duplex mode. */
7647 pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
7648 if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
7649 {
7650 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7651 }
7652
7653 /* Set the link polarity bit. */
7654 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7655 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7656 {
7657 if((pDevice->LedCtrl == LED_CTRL_PHY_MODE_2) ||
7658 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
7659 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
7660 {
7661 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7662 }
7663 }
7664 else
7665 {
7666 if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7667 {
7668 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7669 }
7670 }
7671
7672 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7673
7674 /* Enable auto polling. */
7675 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
7676 {
7677 pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
7678 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7679 }
7680 /* if using MAC led mode and not using auto polling, need to configure */
7681 /* mi status register */
7682 else if ((pDevice->LedCtrl &
7683 (LED_CTRL_PHY_MODE_1 | LED_CTRL_PHY_MODE_2)) == 0)
7684 {
7685 if (CurrentLinkStatus != LM_STATUS_LINK_ACTIVE)
7686 {
7687 REG_WR(pDevice, MacCtrl.MiStatus, 0);
7688 }
7689 else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7690 {
7691 REG_WR(pDevice, MacCtrl.MiStatus,
7692 MI_STATUS_ENABLE_LINK_STATUS_ATTN | MI_STATUS_10MBPS);
7693 }
7694 else
7695 {
7696 REG_WR(pDevice, MacCtrl.MiStatus,
7697 MI_STATUS_ENABLE_LINK_STATUS_ATTN);
7698 }
7699 }
7700
7701 /* Enable phy link change attention. */
7702 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7703 {
7704 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7705 }
7706 else
7707 {
7708 REG_WR(pDevice, MacCtrl.MacEvent,
7709 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7710 }
7711 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
7712 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7713 (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7714 (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
7715 (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
7716 !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
7717 {
7718 MM_Wait(120);
7719 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7720 MAC_STATUS_CFG_CHANGED);
7721 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
7722 T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
7723 }
7724
7725 /* Indicate link status. */
7726 if (pDevice->LinkStatus != CurrentLinkStatus) {
7727 pDevice->LinkStatus = CurrentLinkStatus;
7728 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7729 }
7730
7731 return LM_STATUS_SUCCESS;
7732 } /* LM_SetupCopperPhy */
7733
7734
7735 void
7736 LM_5714_FamForceFiber(
7737 PLM_DEVICE_BLOCK pDevice)
7738 {
7739 LM_UINT32 Creg, new_bmcr;
7740 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7741
7742 new_bmcr = Creg & ~PHY_CTRL_AUTO_NEG_ENABLE;
7743
7744 if ( pDevice->RequestedDuplexMode == 0 ||
7745 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_FULL){
7746
7747 new_bmcr |= PHY_CTRL_FULL_DUPLEX_MODE;
7748 }
7749
7750 if(Creg == new_bmcr)
7751 return;
7752
7753 new_bmcr |= PHY_CTRL_SPEED_SELECT_1000MBPS; /* Reserve bit */
7754
7755 /* Force a linkdown */
7756 LM_WritePhy(pDevice, PHY_AN_AD_REG, 0);
7757 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr |
7758 PHY_CTRL_RESTART_AUTO_NEG |
7759 PHY_CTRL_AUTO_NEG_ENABLE |
7760 PHY_CTRL_SPEED_SELECT_1000MBPS);
7761 MM_Wait(10);
7762
7763 /* Force it */
7764 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr);
7765 MM_Wait(10);
7766
7767 return;
7768
7769 }/* LM_5714_FamForceFiber */
7770
7771
7772 void
7773 LM_5714_FamGoFiberAutoNeg(
7774 PLM_DEVICE_BLOCK pDevice)
7775 {
7776 LM_UINT32 adv,Creg,new;
7777
7778 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7779 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &adv);
7780
7781 new = adv & ~( PHY_AN_AD_1000XFULL |
7782 PHY_AN_AD_1000XHALF |
7783 PHY_AN_AD_1000XPAUSE |
7784 PHY_AN_AD_1000XPSE_ASYM |
7785 0x1f);
7786
7787 new |= PHY_AN_AD_1000XPAUSE;
7788
7789 new |= PHY_AN_AD_1000XFULL;
7790 new |= PHY_AN_AD_1000XHALF;
7791
7792 if ((new != adv) || !(Creg & PHY_CTRL_AUTO_NEG_ENABLE)){
7793 LM_WritePhy(pDevice, PHY_AN_AD_REG, new);
7794 MM_Wait(5);
7795 pDevice->AutoNegJustInited=1;
7796 LM_WritePhy(pDevice, PHY_CTRL_REG, (Creg |
7797 PHY_CTRL_RESTART_AUTO_NEG |
7798 PHY_CTRL_SPEED_SELECT_1000MBPS |
7799 PHY_CTRL_AUTO_NEG_ENABLE) );
7800 }
7801
7802 return;
7803 } /* 5714_FamGoFiberAutoNeg */
7804
7805
7806 void
7807 LM_5714_FamDoFiberLoopback(PLM_DEVICE_BLOCK pDevice)
7808 {
7809 LM_UINT32 Value32;
7810
7811 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7812
7813 if( !(Value32 & PHY_CTRL_LOOPBACK_MODE) )
7814 {
7815 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7816
7817 /* Prevent the interrupt handling from being called. */
7818 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7819 (pDevice->pStatusBlkVirt->Status &
7820 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7821 }
7822
7823 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7824 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7825
7826 return;
7827
7828 }/* 5714_FamDoFiberLoopBack */
7829
7830
7831 /******************************************************************************/
7832 /* Description: */
7833 /* */
7834 /* Return: */
7835 /******************************************************************************/
7836
7837 LM_STATUS
7838 LM_SetupNewFiberPhy(
7839 PLM_DEVICE_BLOCK pDevice)
7840 {
7841 LM_STATUS LmStatus = LM_STATUS_SUCCESS;
7842 LM_UINT32 Creg,Sreg,rsav;
7843
7844 rsav = pDevice->LinkStatus;
7845
7846 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7847 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7848 MM_Wait(40);
7849
7850 /* Disable phy link change attention. */
7851 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7852
7853 /* Clear link change attention. */
7854 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7855 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7856 MAC_STATUS_LINK_STATE_CHANGED);
7857
7858
7859 if( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7860 ( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ){
7861
7862 /* do nothing */
7863 }else if ( pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE){
7864
7865 LM_5714_FamDoFiberLoopback(pDevice);
7866 goto fiberloopbackreturn;
7867
7868 } else if( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) {
7869
7870 LM_5714_FamGoFiberAutoNeg(pDevice);
7871
7872
7873 }else {
7874
7875 LM_5714_FamForceFiber(pDevice);
7876 }
7877 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7878 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7879
7880 if(Sreg & PHY_STATUS_LINK_PASS){
7881
7882 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7883 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7884
7885 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7886
7887 if(Creg & PHY_CTRL_FULL_DUPLEX_MODE) {
7888 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7889 }else{
7890 pDevice->DuplexMode = LM_DUPLEX_MODE_HALF;
7891 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7892 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7893 }
7894
7895 if(Creg & PHY_CTRL_AUTO_NEG_ENABLE){
7896 LM_UINT32 ours,partner;
7897
7898 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &ours);
7899 LM_ReadPhy(pDevice,PHY_LINK_PARTNER_ABILITY_REG, &partner);
7900 LM_SetFlowControl(pDevice, ours, partner);
7901 }
7902
7903 }else{
7904 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
7905 pDevice->LineSpeed = 0;
7906 }
7907
7908 if(rsav != pDevice->LinkStatus)
7909 MM_IndicateStatus(pDevice, pDevice->LinkStatus);
7910
7911 fiberloopbackreturn:
7912 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7913 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7914 MM_Wait(40);
7915 /* Enable link change interrupt. */
7916 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7917
7918 return LmStatus;
7919 } /* Setup New phy */
7920
7921 void
7922 LM_5714_FamFiberCheckLink(
7923 PLM_DEVICE_BLOCK pDevice)
7924 {
7925
7926 if(pDevice->AutoNegJustInited){
7927 pDevice->AutoNegJustInited=0;
7928 return;
7929 }
7930
7931 if ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) &&
7932 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) &&
7933 !(pDevice->PhyFlags & PHY_FIBER_FALLBACK)){
7934 LM_UINT32 bmcr;
7935
7936 LM_ReadPhy(pDevice, PHY_CTRL_REG, &bmcr);
7937 if (bmcr & PHY_CTRL_AUTO_NEG_ENABLE) {
7938 LM_UINT32 phy1, phy2;
7939
7940 LM_WritePhy(pDevice, 0x1c, 0x7c00);
7941 LM_ReadPhy(pDevice, 0x1c, &phy1);
7942
7943 LM_WritePhy(pDevice, 0x17, 0x0f01);
7944 LM_ReadPhy(pDevice, 0x15, &phy2);
7945 LM_ReadPhy(pDevice, 0x15, &phy2);
7946
7947 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
7948
7949 /* We have signal detect and not receiving
7950 * configs.
7951 */
7952
7953 pDevice->PhyFlags |= PHY_FIBER_FALLBACK;
7954 LM_5714_FamForceFiber(pDevice);
7955 }
7956 }
7957 }
7958 else if ( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7959 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)) {
7960 LM_UINT32 phy2;
7961
7962 LM_WritePhy(pDevice, 0x17, 0x0f01);
7963 LM_ReadPhy(pDevice, 0x15, &phy2);
7964 if (phy2 & 0x20) {
7965 /* Receiving configs. */
7966
7967 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
7968 LM_5714_FamGoFiberAutoNeg(pDevice);
7969 }
7970 }
7971
7972 } /* LM_5714_FamFiberCheckLink */
7973
7974
7975 /******************************************************************************/
7976 /* Description: */
7977 /* */
7978 /* Return: */
7979 /******************************************************************************/
7980 LM_STATUS
7981 LM_SetupPhy(
7982 PLM_DEVICE_BLOCK pDevice)
7983 {
7984 LM_STATUS LmStatus;
7985 LM_UINT32 Value32;
7986
7987 if(pDevice->PhyFlags & PHY_IS_FIBER)
7988 {
7989 LmStatus = LM_SetupNewFiberPhy(pDevice);
7990 }else
7991 #ifdef INCLUDE_TBI_SUPPORT
7992 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
7993 {
7994 LmStatus = LM_SetupFiberPhy(pDevice);
7995 }
7996 else
7997 #endif /* INCLUDE_TBI_SUPPORT */
7998 {
7999 LmStatus = LM_SetupCopperPhy(pDevice);
8000 }
8001 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
8002 {
8003 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
8004 {
8005 Value32 = REG_RD(pDevice, PciCfg.PciState);
8006 REG_WR(pDevice, PciCfg.PciState,
8007 Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
8008 }
8009 }
8010 if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
8011 (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
8012 {
8013 REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
8014 }
8015 else
8016 {
8017 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
8018 }
8019 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8020 {
8021 if (pDevice->LinkStatus == LM_STATUS_LINK_DOWN)
8022 {
8023 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, 0);
8024 }
8025 else
8026 {
8027 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
8028 pDevice->StatsCoalescingTicks);
8029 }
8030 }
8031
8032 return LmStatus;
8033 }
8034
8035
8036 /* test data pattern */
8037 static LM_UINT32 pattern[4][6] = {
8038 /* For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6)
8039 For 5705 , each DFE TAP has 19-bits (low word 15, hi word 4)
8040 For simplicity, we check only 19-bits, so we don't have to
8041 distinguish which chip it is.
8042 the LO word contains 15 bits, make sure pattern data is < 0x7fff
8043 the HI word contains 6 bits, make sure pattern data is < 0x003f */
8044 {0x00005555, 0x00000005, /* ch0, TAP 0, LO/HI pattern */
8045 0x00002aaa, 0x0000000a, /* ch0, TAP 1, LO/HI pattern */
8046 0x00003456, 0x00000003}, /* ch0, TAP 2, LO/HI pattern */
8047
8048 {0x00002aaa, 0x0000000a, /* ch1, TAP 0, LO/HI pattern */
8049 0x00003333, 0x00000003, /* ch1, TAP 1, LO/HI pattern */
8050 0x0000789a, 0x00000005}, /* ch1, TAP 2, LO/HI pattern */
8051
8052 {0x00005a5a, 0x00000005, /* ch2, TAP 0, LO/HI pattern */
8053 0x00002a6a, 0x0000000a, /* ch2, TAP 1, LO/HI pattern */
8054 0x00001bcd, 0x00000003}, /* ch2, TAP 2, LO/HI pattern */
8055
8056 {0x00002a5a, 0x0000000a, /* ch3, TAP 0, LO/HI pattern */
8057 0x000033c3, 0x00000003, /* ch3, TAP 1, LO/HI pattern */
8058 0x00002ef1, 0x00000005}, /* ch3, TAP 2, LO/HI pattern */
8059 };
8060
8061 /********************************************************/
8062 /* Routine to wait for PHY Macro Command to complete */
8063 /* */
8064 /* If PHY's Macro operation keeps stay busy, nothing we */
8065 /* can do anyway. The timeout is there so we won't */
8066 /* stay in this routine indefinitly. */
8067 /********************************************************/
8068 static LM_UINT32 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice);
8069
8070 static LM_UINT32
8071 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice)
8072 {
8073 LM_UINT32 timeout;
8074 LM_UINT32 val32;
8075
8076 timeout = 100;
8077 while (timeout--)
8078 {
8079 /* make sure the MACRO operation is complete */
8080 LM_ReadPhy(pDevice, 0x16, &val32);
8081 if ((val32 & 0x1000) == 0) break;
8082 }
8083
8084 return( timeout > 0 );
8085 }
8086
8087 /********************************************************/
8088 /* This routine resets the PHY on following chips: */
8089 /* 5703, 04, CIOB-E and 5705 */
8090 /* */
8091 /* This routine will issue PHY_RESET and check if */
8092 /* the reset is sucessful. If not, another PHY RESET */
8093 /* will be issued, until max "retry" reaches */
8094 /* */
8095 /* Input: */
8096 /* pDevice - device's context */
8097 /* retry - number of retries */
8098 /* reset - TRUE=will cause a PHY reset initially */
8099 /* FALSE = will not issue a PHY reset */
8100 /* unless TAP lockup detected */
8101 /* */
8102 /* Output: */
8103 /* TRUE - PHY Reset is done sucessfully */
8104 /* FALSE - PHY Reset had failed, after "retry" */
8105 /* has reached */
8106 /* */
8107 /* Dependencies: */
8108 /* void LM_wait_macro_done() */
8109 /* LM_UINT32 pattern[] */
8110 /* */
8111 /* Usage: */
8112 /* a. Before calling this routine, caller must */
8113 /* determine if the chip is a 5702/03/04 or */
8114 /* CIOB-E, and only call this routine if the */
8115 /* is one of these. */
8116 /* or its derivatives. */
8117 /* b. Instead of using MII register write to reset */
8118 /* the PHY, call this routine instead */
8119 /* c. Upon return from this routine, check return */
8120 /* value (TRUE/FALSE) to determine if PHY reset */
8121 /* is successful of not and "optionally" take */
8122 /* appropriate action (such as: event log) */
8123 /* d. Regardless of the return TRUE or FALSE, */
8124 /* proceed with PHY setup as you normally would */
8125 /* after a PHY_RESET. */
8126 /* e. It is recommended that the caller will give */
8127 /* 10 "retry", however, caller can change to a */
8128 /* different number, depending on you code. */
8129 /* */
8130 /********************************************************/
8131 LM_STATUS LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset);
8132
8133 LM_STATUS
8134 LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset)
8135 {
8136 LM_UINT32 val32, save9;
8137 LM_UINT32 dataLo, dataHi;
8138 int i, channel;
8139 int reset_success = LM_STATUS_FAILURE;
8140 int force_reset;
8141
8142 /* to actually do a PHY_RESET or not is dictated by the caller */
8143 force_reset = reset;
8144
8145 while (retry-- && (reset_success != LM_STATUS_SUCCESS))
8146 {
8147 if (force_reset)
8148 {
8149 /* issue a phy reset, and wait for reset to complete */
8150 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8151 for(i = 0; i < 100; i++)
8152 {
8153 MM_Wait(10);
8154
8155 LM_ReadPhy(pDevice, PHY_CTRL_REG, &val32);
8156 if(val32 && !(val32 & PHY_CTRL_PHY_RESET))
8157 {
8158 MM_Wait(20);
8159 break;
8160 }
8161 }
8162
8163 /* no more phy reset unless lockup detected */
8164 force_reset = FALSE;
8165 }
8166
8167 /* assuming reset is successful first */
8168 reset_success = LM_STATUS_SUCCESS;
8169
8170 /* now go check the DFE TAPs to see if locked up, but
8171 first, we need to set up PHY so we can read DFE TAPs */
8172
8173 /* Disable Transmitter and Interrupt, while we play with
8174 the PHY registers, so the link partner won't see any
8175 strange data and the Driver won't see any interrupts. */
8176 LM_ReadPhy(pDevice, 0x10, &val32);
8177 LM_WritePhy(pDevice, 0x10, val32 | 0x3000);
8178
8179 /* Setup Full-Duplex, 1000 mbps */
8180 LM_WritePhy(pDevice, 0x0, 0x0140);
8181
8182 /* Set to Master mode */
8183 LM_ReadPhy(pDevice, 0x9, &save9);
8184 LM_WritePhy(pDevice, 0x9, 0x1800);
8185
8186 /* Enable SM_DSP_CLOCK & 6dB */
8187 LM_WritePhy(pDevice, 0x18, 0x0c00);
8188
8189 /* blocks the PHY control access */
8190 LM_WritePhy(pDevice, 0x17, 0x8005);
8191 LM_WritePhy(pDevice, 0x15, 0x0800);
8192
8193 /* check TAPs for all 4 channels, as soon
8194 as we see a lockup we'll stop checking */
8195 for (channel=0; (channel<4) && (reset_success == LM_STATUS_SUCCESS);
8196 channel++)
8197 {
8198 /* select channel and set TAP index to 0 */
8199 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8200 /* freeze filter again just to be safe */
8201 LM_WritePhy(pDevice, 0x16, 0x0002);
8202
8203 /* write fixed pattern to the RAM, 3 TAPs for
8204 each channel, each TAP have 2 WORDs (LO/HI) */
8205 for (i=0; i<6; i++)
8206 LM_WritePhy(pDevice, 0x15, pattern[channel][i]);
8207
8208 /* Activate PHY's Macro operation to write DFE TAP from RAM,
8209 and wait for Macro to complete */
8210 LM_WritePhy(pDevice, 0x16, 0x0202);
8211 if (!LM_wait_macro_done(pDevice))
8212 {
8213 reset_success = LM_STATUS_FAILURE;
8214 force_reset = TRUE;
8215 break;
8216 }
8217
8218 /* --- done with write phase, now begin read phase --- */
8219
8220 /* select channel and set TAP index to 0 */
8221 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8222
8223 /* Active PHY's Macro operation to load DFE TAP to RAM,
8224 and wait for Macro to complete */
8225 LM_WritePhy(pDevice, 0x16, 0x0082);
8226 if (!LM_wait_macro_done(pDevice))
8227 {
8228 reset_success = LM_STATUS_FAILURE;
8229 force_reset = TRUE;
8230 break;
8231 }
8232
8233 /* enable "pre-fetch" */
8234 LM_WritePhy(pDevice, 0x16, 0x0802);
8235 if (!LM_wait_macro_done(pDevice))
8236 {
8237 reset_success = LM_STATUS_FAILURE;
8238 force_reset = TRUE;
8239 break;
8240 }
8241
8242 /* read back the TAP values.
8243 3 TAPs for each channel, each TAP have 2 WORDs (LO/HI) */
8244 for (i=0; i<6; i+=2)
8245 {
8246 /* read Lo/Hi then wait for 'done' is faster */
8247 LM_ReadPhy(pDevice, 0x15, &dataLo);
8248 LM_ReadPhy(pDevice, 0x15, &dataHi);
8249 if (!LM_wait_macro_done(pDevice))
8250 {
8251 reset_success = LM_STATUS_FAILURE;
8252 force_reset = TRUE;
8253 break;
8254 }
8255
8256 /* For 5703/04, each DFE TAP has 21-bits (low word 15,
8257 * hi word 6) For 5705, each DFE TAP pas 19-bits (low word 15,
8258 * hi word 4) For simplicity, we check only 19-bits, so we
8259 * don't have to distinguish which chip it is. */
8260 dataLo &= 0x7fff;
8261 dataHi &= 0x000f;
8262
8263 /* check if what we wrote is what we read back */
8264 if ( (dataLo != pattern[channel][i]) || (dataHi != pattern[channel][i+1]) )
8265 {
8266 /* if failed, then the PHY is locked up,
8267 we need to do PHY reset again */
8268 reset_success = LM_STATUS_FAILURE;
8269 force_reset = TRUE;
8270 /* 04/25/2003. sb. do these writes before issueing a reset. */
8271 /* these steps will reduce the chance of back-to-back
8272 * phy lockup after reset */
8273 LM_WritePhy(pDevice, 0x17, 0x000B);
8274 LM_WritePhy(pDevice, 0x15, 0x4001);
8275 LM_WritePhy(pDevice, 0x15, 0x4005);
8276 break;
8277 }
8278 } /* for i */
8279 } /* for channel */
8280 } /* while */
8281
8282 /* restore dfe coeff back to zeros */
8283 for (channel=0; channel<4 ; channel++)
8284 {
8285 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8286 LM_WritePhy(pDevice, 0x16, 0x0002);
8287 for (i=0; i<6; i++)
8288 LM_WritePhy(pDevice, 0x15, 0x0000);
8289 LM_WritePhy(pDevice, 0x16, 0x0202);
8290 if (!LM_wait_macro_done(pDevice))
8291 {
8292 reset_success = LM_STATUS_FAILURE;
8293 break;
8294 }
8295 }
8296
8297 /* remove block phy control */
8298 LM_WritePhy(pDevice, 0x17, 0x8005);
8299 LM_WritePhy(pDevice, 0x15, 0x0000);
8300
8301 /* unfreeze DFE TAP filter for all channels */
8302 LM_WritePhy(pDevice, 0x17, 0x8200);
8303 LM_WritePhy(pDevice, 0x16, 0x0000);
8304
8305 /* Restore PHY back to operating state */
8306 LM_WritePhy(pDevice, 0x18, 0x0400);
8307
8308 /* Restore register 9 */
8309 LM_WritePhy(pDevice, 0x9, save9);
8310
8311 /* enable transmitter and interrupt */
8312 LM_ReadPhy(pDevice, 0x10, &val32);
8313 LM_WritePhy(pDevice, 0x10, (val32 & ~0x3000));
8314
8315 return reset_success;
8316 }
8317
8318 LM_VOID
8319 LM_ResetPhy(LM_DEVICE_BLOCK *pDevice)
8320 {
8321 int j;
8322 LM_UINT32 miireg;
8323
8324 if (pDevice->PhyFlags & PHY_CHECK_TAPS_AFTER_RESET)
8325 {
8326 LM_ResetPhy_5703_4_5(pDevice, 5, 1);
8327 }
8328 else
8329 {
8330 int wait_val = 100;
8331 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8332
8333 if( pDevice->PhyFlags & PHY_IS_FIBER )
8334 wait_val = 5000;
8335
8336 for(j = 0; j < wait_val; j++)
8337 {
8338 MM_Wait(10);
8339
8340 LM_ReadPhy(pDevice, PHY_CTRL_REG, &miireg);
8341 if(miireg && !(miireg & PHY_CTRL_PHY_RESET))
8342 {
8343 MM_Wait(20);
8344 break;
8345 }
8346 }
8347
8348 LM_PhyTapPowerMgmt(pDevice);
8349 }
8350 if ( (pDevice->PhyFlags & PHY_ADC_FIX) &&
8351 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8352 {
8353 LM_WritePhy(pDevice, 0x18, 0x0c00);
8354 LM_WritePhy(pDevice, 0x17, 0x201f);
8355 LM_WritePhy(pDevice, 0x15, 0x2aaa);
8356 LM_WritePhy(pDevice, 0x17, 0x000a);
8357 LM_WritePhy(pDevice, 0x15, 0x0323);
8358 LM_WritePhy(pDevice, 0x18, 0x0400);
8359 }
8360 if ( (pDevice->PhyFlags & PHY_5705_5750_FIX) &&
8361 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8362 {
8363 LM_WritePhy(pDevice, 0x18, 0x0c00);
8364 LM_WritePhy(pDevice, 0x17, 0x000a);
8365 LM_WritePhy(pDevice, 0x15, 0x310b);
8366 LM_WritePhy(pDevice, 0x17, 0x201f);
8367 LM_WritePhy(pDevice, 0x15, 0x9506);
8368 LM_WritePhy(pDevice, 0x17, 0x401f);
8369 LM_WritePhy(pDevice, 0x15, 0x14e2);
8370 LM_WritePhy(pDevice, 0x18, 0x0400);
8371 }
8372 if ( (pDevice->PhyFlags & PHY_5704_A0_FIX) &&
8373 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8374 {
8375 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8376 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8377 }
8378 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
8379 {
8380 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8381 miireg |= 1; /* set tx elastic fifo */
8382 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8383
8384 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
8385 }
8386 else if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
8387 {
8388 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
8389 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &miireg);
8390 miireg |= 0x4000; /* set rx extended packet length */
8391 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, miireg);
8392
8393 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8394 miireg |= 1; /* set tx elastic fifo */
8395 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8396
8397 }
8398
8399 LM_SetEthWireSpeed(pDevice);
8400 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
8401 }
8402
8403 STATIC LM_VOID
8404 LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice)
8405 {
8406 LM_UINT32 Value32;
8407
8408 if( pDevice->PhyFlags & PHY_IS_FIBER)
8409 return;
8410
8411 /* Enable Ethernet@WireSpeed. */
8412 if (pDevice->PhyFlags & PHY_ETHERNET_WIRESPEED)
8413 {
8414 LM_WritePhy(pDevice, 0x18, 0x7007);
8415 LM_ReadPhy(pDevice, 0x18, &Value32);
8416 LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
8417 }
8418 }
8419
8420 STATIC LM_STATUS
8421 LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice)
8422 {
8423 LM_UINT32 miireg;
8424
8425 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &miireg);
8426 pDevice->advertising = miireg;
8427 if ((miireg & PHY_AN_AD_ALL_SPEEDS) != PHY_AN_AD_ALL_SPEEDS)
8428 {
8429 return LM_STATUS_FAILURE;
8430 }
8431
8432 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &miireg);
8433 pDevice->advertising1000 = miireg;
8434
8435 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
8436 {
8437 if ((miireg & BCM540X_AN_AD_ALL_1G_SPEEDS) !=
8438 BCM540X_AN_AD_ALL_1G_SPEEDS)
8439 {
8440 return LM_STATUS_FAILURE;
8441 }
8442 }else{
8443
8444 if(miireg)
8445 {
8446 return LM_STATUS_FAILURE;
8447 }
8448 }
8449 return LM_STATUS_SUCCESS;
8450 }
8451
8452 /******************************************************************************/
8453 /* Description: */
8454 /* */
8455 /* Return: */
8456 /******************************************************************************/
8457 LM_VOID
8458 LM_ReadPhy(
8459 PLM_DEVICE_BLOCK pDevice,
8460 LM_UINT32 PhyReg,
8461 PLM_UINT32 pData32) {
8462 LM_UINT32 Value32;
8463 LM_UINT32 j;
8464
8465 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8466 {
8467 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8468 ~MI_MODE_AUTO_POLLING_ENABLE);
8469 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8470 MM_Wait(40);
8471 }
8472
8473 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8474 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8475 MI_COM_CMD_READ | MI_COM_START;
8476
8477 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8478
8479 for(j = 0; j < 200; j++)
8480 {
8481 MM_Wait(1);
8482
8483 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8484
8485 if(!(Value32 & MI_COM_BUSY))
8486 {
8487 MM_Wait(5);
8488 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8489 Value32 &= MI_COM_PHY_DATA_MASK;
8490 break;
8491 }
8492 }
8493
8494 if(Value32 & MI_COM_BUSY)
8495 {
8496 Value32 = 0;
8497 }
8498
8499 *pData32 = Value32;
8500
8501 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8502 {
8503 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8504 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8505 MM_Wait(40);
8506 }
8507 } /* LM_ReadPhy */
8508
8509
8510
8511 /******************************************************************************/
8512 /* Description: */
8513 /* */
8514 /* Return: */
8515 /******************************************************************************/
8516 LM_VOID
8517 LM_WritePhy(
8518 PLM_DEVICE_BLOCK pDevice,
8519 LM_UINT32 PhyReg,
8520 LM_UINT32 Data32) {
8521 LM_UINT32 Value32;
8522 LM_UINT32 j;
8523
8524 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8525 {
8526 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8527 ~MI_MODE_AUTO_POLLING_ENABLE);
8528 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8529 MM_Wait(40);
8530 }
8531
8532 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8533 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8534 (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
8535
8536 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8537
8538 for(j = 0; j < 200; j++)
8539 {
8540 MM_Wait(1);
8541
8542 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8543
8544 if(!(Value32 & MI_COM_BUSY))
8545 {
8546 MM_Wait(5);
8547 break;
8548 }
8549 }
8550
8551 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8552 {
8553 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8554 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8555 MM_Wait(40);
8556 }
8557 } /* LM_WritePhy */
8558
8559 /* MII read/write functions to export to the robo support code */
8560 LM_UINT16
8561 robo_miird(void *h, int phyadd, int regoff)
8562 {
8563 PLM_DEVICE_BLOCK pdev = h;
8564 LM_UINT32 savephyaddr, val32;
8565
8566 savephyaddr = pdev->PhyAddr;
8567 pdev->PhyAddr = phyadd;
8568
8569 LM_ReadPhy(pdev, regoff, &val32);
8570
8571 pdev->PhyAddr = savephyaddr;
8572
8573 return ((LM_UINT16)(val32 & 0xffff));
8574 }
8575
8576 void
8577 robo_miiwr(void *h, int phyadd, int regoff, LM_UINT16 value)
8578 {
8579 PLM_DEVICE_BLOCK pdev = h;
8580 LM_UINT32 val32, savephyaddr;
8581
8582 savephyaddr = pdev->PhyAddr;
8583 pdev->PhyAddr = phyadd;
8584
8585 val32 = (LM_UINT32)value;
8586 LM_WritePhy(pdev, regoff, val32);
8587
8588 pdev->PhyAddr = savephyaddr;
8589 }
8590
8591 STATIC void
8592 LM_GetPhyId(LM_DEVICE_BLOCK *pDevice)
8593 {
8594 LM_UINT32 Value32;
8595
8596 LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
8597 pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
8598
8599 LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
8600 pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
8601 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
8602
8603 }
8604
8605 LM_STATUS
8606 LM_EnableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8607 {
8608 pDevice->LoopBackMode = LM_MAC_LOOP_BACK_MODE;
8609 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
8610 pDevice->MacMode |= (MAC_MODE_PORT_INTERNAL_LOOPBACK |
8611 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII);
8612 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8613 MM_Wait(40);
8614 LM_SetupPhy(pDevice);
8615 return LM_STATUS_SUCCESS;
8616 }
8617
8618 LM_STATUS
8619 LM_DisableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8620 {
8621 pDevice->LoopBackMode = 0;
8622
8623 pDevice->MacMode &= ~(MAC_MODE_PORT_INTERNAL_LOOPBACK |
8624 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_MASK);
8625 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8626 MM_Wait(40);
8627 if(pDevice->PhyFlags & PHY_IS_FIBER)
8628 LM_ResetPhy(pDevice);
8629
8630 LM_SetupPhy(pDevice);
8631 return LM_STATUS_SUCCESS;
8632 }
8633
8634 LM_STATUS
8635 LM_EnablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8636 {
8637 pDevice->LoopBackMode = LM_PHY_LOOP_BACK_MODE;
8638 LM_SetupPhy(pDevice);
8639 return LM_STATUS_SUCCESS;
8640 }
8641
8642 LM_STATUS
8643 LM_DisablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8644 {
8645 pDevice->LoopBackMode = 0;
8646 LM_SetupPhy(pDevice);
8647 return LM_STATUS_SUCCESS;
8648 }
8649
8650 LM_STATUS
8651 LM_EnableExtLoopBack(PLM_DEVICE_BLOCK pDevice, LM_LINE_SPEED LineSpeed)
8652 {
8653 pDevice->LoopBackMode = LM_EXT_LOOP_BACK_MODE;
8654
8655 pDevice->SavedDisableAutoNeg = pDevice->DisableAutoNeg;
8656 pDevice->SavedRequestedLineSpeed = pDevice->RequestedLineSpeed;
8657 pDevice->SavedRequestedDuplexMode = pDevice->RequestedDuplexMode;
8658
8659 pDevice->DisableAutoNeg = TRUE;
8660 pDevice->RequestedLineSpeed = LineSpeed;
8661 pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_FULL;
8662 LM_SetupPhy(pDevice);
8663 return LM_STATUS_SUCCESS;
8664 }
8665
8666 LM_STATUS
8667 LM_DisableExtLoopBack(PLM_DEVICE_BLOCK pDevice)
8668 {
8669 pDevice->LoopBackMode = 0;
8670
8671 pDevice->DisableAutoNeg = pDevice->SavedDisableAutoNeg;
8672 pDevice->RequestedLineSpeed = pDevice->SavedRequestedLineSpeed;
8673 pDevice->RequestedDuplexMode = pDevice->SavedRequestedDuplexMode;
8674
8675 LM_SetupPhy(pDevice);
8676 return LM_STATUS_SUCCESS;
8677 }
8678
8679 /******************************************************************************/
8680 /* Description: */
8681 /* */
8682 /* Return: */
8683 /******************************************************************************/
8684 LM_STATUS
8685 LM_SetPowerState(
8686 PLM_DEVICE_BLOCK pDevice,
8687 LM_POWER_STATE PowerLevel)
8688 {
8689 #ifdef BCM_WOL
8690 LM_UINT32 PmeSupport;
8691 PLM_DEVICE_BLOCK pDevice2 = 0;
8692 int j;
8693 #endif
8694 LM_UINT32 Value32;
8695 LM_UINT32 PmCtrl;
8696
8697 /* make sureindirect accesses are enabled*/
8698 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
8699
8700 /* Clear the PME_ASSERT bit and the power state bits. Also enable */
8701 /* the PME bit. */
8702 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
8703
8704 PmCtrl |= T3_PM_PME_ASSERTED;
8705 PmCtrl &= ~T3_PM_POWER_STATE_MASK;
8706
8707 /* Set the appropriate power state. */
8708 if(PowerLevel == LM_POWER_STATE_D0)
8709 {
8710 /* Bring the card out of low power mode. */
8711 PmCtrl |= T3_PM_POWER_STATE_D0;
8712 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8713
8714 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
8715
8716 if(T3_ASIC_5752(pDevice->ChipRevId)){
8717 Value32 |= (GRC_MISC_LOCAL_CTRL_GPIO_OE3 |
8718 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 |
8719 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8720 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8721 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8722 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8723 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8724 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8725 }
8726 else
8727 {
8728 Value32 &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8729 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8730 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8731 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8732 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8733 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8734 }
8735
8736 RAW_REG_WR(pDevice, Grc.LocalCtrl, Value32);
8737
8738 MM_Wait(40); /* Required delay is about 20us. */
8739
8740 pDevice->PowerLevel = PowerLevel;
8741 return LM_STATUS_SUCCESS;
8742 }
8743 #ifdef BCM_WOL
8744 else if(PowerLevel == LM_POWER_STATE_D1)
8745 {
8746 PmCtrl |= T3_PM_POWER_STATE_D1;
8747 }
8748 else if(PowerLevel == LM_POWER_STATE_D2)
8749 {
8750 PmCtrl |= T3_PM_POWER_STATE_D2;
8751 }
8752 else if(PowerLevel == LM_POWER_STATE_D3)
8753 {
8754 PmCtrl |= T3_PM_POWER_STATE_D3;
8755 }
8756 else
8757 {
8758 return LM_STATUS_FAILURE;
8759 }
8760 PmCtrl |= T3_PM_PME_ENABLE;
8761
8762 /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
8763 /* setting new line speed. */
8764 Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
8765 REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
8766
8767 if(!pDevice->RestoreOnWakeUp)
8768 {
8769 pDevice->RestoreOnWakeUp = TRUE;
8770 pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
8771 pDevice->WakeUpRequestedLineSpeed = pDevice->RequestedLineSpeed;
8772 pDevice->WakeUpRequestedDuplexMode = pDevice->RequestedDuplexMode;
8773 }
8774
8775 /* Force auto-negotiation to 10 line speed. */
8776 pDevice->DisableAutoNeg = FALSE;
8777
8778 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8779 {
8780 pDevice->RequestedLineSpeed = LM_LINE_SPEED_10MBPS;
8781 LM_SetupPhy(pDevice);
8782 }
8783
8784 /* Put the driver in the initial state, and go through the power down */
8785 /* sequence. */
8786 LM_DoHalt(pDevice);
8787
8788 if (!(pDevice->AsfFlags & ASF_ENABLED))
8789 {
8790 for(j = 0; j < 20000; j++)
8791 {
8792 MM_Wait(10);
8793
8794 Value32 = MEM_RD_OFFSET(pDevice, T3_ASF_FW_STATUS_MAILBOX);
8795 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE)
8796 {
8797 break;
8798 }
8799 }
8800 }
8801
8802 MEM_WR_OFFSET(pDevice, DRV_WOL_MAILBOX, DRV_WOL_SIGNATURE |
8803 DRV_DOWN_STATE_SHUTDOWN | 0x2 | DRV_WOL_SET_MAGIC_PKT);
8804
8805 MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
8806
8807 if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
8808 {
8809
8810 /* Enable WOL. */
8811 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8812 {
8813 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
8814 MM_Wait(40);
8815 }
8816
8817 if (! T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
8818 {
8819 /* Let boot code deal with LED mode on shasta */
8820 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
8821 }
8822
8823 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8824 {
8825 Value32 = MAC_MODE_PORT_MODE_TBI;
8826 }
8827 else
8828 {
8829 Value32 = MAC_MODE_PORT_MODE_MII;
8830 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
8831 {
8832 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_2 ||
8833 pDevice->WolSpeed == WOL_SPEED_10MB)
8834 {
8835 Value32 |= MAC_MODE_LINK_POLARITY;
8836 }
8837 }
8838 else
8839 {
8840 Value32 |= MAC_MODE_LINK_POLARITY;
8841 }
8842 }
8843 REG_WR(pDevice, MacCtrl.Mode, Value32);
8844 REG_RD_BACK(pDevice, MacCtrl.Mode);
8845 MM_Wait(40); MM_Wait(40); MM_Wait(40);
8846
8847 /* Always enable magic packet wake-up if we have vaux. */
8848 if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
8849 (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
8850 {
8851 Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
8852 }
8853
8854 #ifdef BCM_ASF
8855 if (pDevice->AsfFlags & ASF_ENABLED)
8856 {
8857 Value32 &= ~MAC_MODE_ACPI_POWER_ON_ENABLE;
8858 }
8859 #endif
8860 REG_WR(pDevice, MacCtrl.Mode, Value32);
8861
8862 /* Enable the receiver. */
8863 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
8864 }
8865 else if (!(pDevice->AsfFlags & ASF_ENABLED))
8866 {
8867 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8868 {
8869 REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
8870 LED_CTRL_OVERRIDE_TRAFFIC_LED);
8871 }
8872 else
8873 {
8874 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
8875 BCM540X_EXT_CTRL_FORCE_LED_OFF);
8876 LM_WritePhy(pDevice, 0x18, 0x01b2);
8877 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8878 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
8879 !T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8880 {
8881 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOWER_POWER_MODE);
8882 }
8883 }
8884 }
8885
8886 /* Disable tx/rx clocks, and select an alternate clock. */
8887 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
8888 /* Do nothing */
8889 }
8890 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
8891 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
8892 (pDevice->WolSpeed == WOL_SPEED_10MB)))
8893 {
8894 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8895 T3_PCI_SELECT_ALTERNATE_CLOCK |
8896 T3_PCI_POWER_DOWN_PCI_PLL133;
8897
8898 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8899 }
8900 /* ASF on 5750 will not run properly on slow core clock */
8901 else if( !(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) &&
8902 (pDevice->AsfFlags & ASF_ENABLED) ))
8903 {
8904 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8905 {
8906 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8907 T3_PCI_SELECT_ALTERNATE_CLOCK;
8908 }
8909 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8910 {
8911 Value32 = T3_PCI_625_CORE_CLOCK;
8912 }
8913 else
8914 {
8915 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
8916 }
8917 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8918
8919 MM_Wait(40);
8920
8921 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8922 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8923 {
8924 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8925 T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8926 }
8927 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8928 {
8929 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_625_CORE_CLOCK;
8930 }
8931 else if(!T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8932 {
8933 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8934 }
8935
8936 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8937
8938 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8939 {
8940 MM_Wait(40);
8941
8942 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8943 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8944 {
8945 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8946 T3_PCI_44MHZ_CORE_CLOCK;
8947 }
8948 else
8949 {
8950 Value32 = T3_PCI_44MHZ_CORE_CLOCK;
8951 }
8952
8953 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8954 }
8955 }
8956
8957 MM_Wait(40);
8958
8959 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
8960 {
8961 pDevice2 = MM_FindPeerDev(pDevice);
8962 }
8963 if (!(pDevice->Flags & EEPROM_WP_FLAG))
8964 {
8965 LM_SwitchVaux(pDevice, pDevice2);
8966 }
8967
8968 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8969
8970 if((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_AX) ||
8971 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_BX)) {
8972
8973 Value32= REG_RD_OFFSET(pDevice, 0x7d00);
8974 REG_WR_OFFSET(pDevice, 0x7d00,Value32 & ~(BIT_16 | BIT_4 | BIT_2 | BIT_1 | BIT_0));
8975
8976 if(!(pDevice->AsfFlags & ASF_ENABLED))
8977 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
8978
8979 }
8980
8981 /* Put the the hardware in low power mode. */
8982 if (!(pDevice->Flags & DISABLE_D3HOT_FLAG))
8983 {
8984 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8985 MM_Wait(200); /* Wait 200us for state transition */
8986 }
8987
8988 pDevice->PowerLevel = PowerLevel;
8989
8990 #else
8991 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8992 #endif /* BCM_WOL */
8993
8994 return LM_STATUS_SUCCESS;
8995 } /* LM_SetPowerState */
8996
8997
8998 LM_VOID
8999 LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2)
9000 {
9001 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9002 return;
9003
9004 pDevice->GrcLocalCtrl &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9005 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9006 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9007 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9008 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9009 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9010
9011 /* Switch adapter to auxilliary power if WOL enabled */
9012 if ((pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
9013 (pDevice->AsfFlags & ASF_ENABLED) ||
9014 (pDevice2 && ((pDevice2->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
9015 (pDevice2->AsfFlags & ASF_ENABLED))))
9016 {
9017 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
9018 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
9019 {
9020 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
9021 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9022 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9023 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9024 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9025 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9026 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9027 MM_Wait(40);
9028 }
9029 else
9030 {
9031 if (pDevice2 && pDevice2->InitDone)
9032 {
9033 return;
9034 }
9035
9036 /* On NICs GPIOs are used for vaux.
9037 The transition of GPIO0 from 0-1 causes vaux
9038 to power up. Transition of GPIO1 from 1-0 turns vaux off.
9039 GPIO2 transition from 1-0 enables a non-glitch vaux
9040 transition from one state to another.
9041 On certain designs we should not output GPIO2.
9042 */
9043 if(pDevice->Flags & GPIO2_DONOT_OUTPUT)
9044 {
9045 /* GPIO0 = 0, GPIO1 = 1. */
9046 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9047 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9048 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9049 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9050
9051 MM_Wait(40);
9052
9053 /* GPIO0 = 1, GPIO1 = 1. */
9054 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9055 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9056 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9057 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9058 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9059
9060 MM_Wait(40);
9061 }
9062 else
9063 {
9064
9065 /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
9066 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9067 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9068 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9069 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9070 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9071 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9072
9073 MM_Wait(40);
9074
9075 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
9076 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9077 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9078 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9079 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9080 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9081 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9082 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9083 MM_Wait(40);
9084
9085 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
9086 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9087 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9088 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9089 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9090 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9091 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9092 MM_Wait(40);
9093 } /* GPIO2 OK */
9094 } /* Not 5700||5701 */
9095 } /* WOL disabled */
9096 else
9097 {
9098 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9099 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9100 {
9101 if (pDevice2 && pDevice2->InitDone)
9102 {
9103 return;
9104 }
9105
9106 /* GPIO1 = 1 */
9107 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9108 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9109 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9110 MM_Wait(40);
9111
9112 /* GPIO1 = 0 */
9113 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9114 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
9115 MM_Wait(40);
9116
9117 /* GPIO1 = 1 */
9118 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9119 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9120 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9121 MM_Wait(40);
9122 }
9123 }
9124 }
9125
9126
9127 /******************************************************************************/
9128 /* Description: */
9129 /* */
9130 /* Return: */
9131 /******************************************************************************/
9132 static LM_UINT32
9133 GetPhyAdFlowCntrlSettings(
9134 PLM_DEVICE_BLOCK pDevice)
9135 {
9136 LM_UINT32 Value32;
9137
9138 Value32 = 0;
9139
9140 /* Auto negotiation flow control only when autonegotiation is enabled. */
9141 if(pDevice->DisableAutoNeg == FALSE ||
9142 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
9143 {
9144 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
9145 (pDevice->PhyFlags & PHY_IS_FIBER)) {
9146
9147 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9148 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9149 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9150 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9151 {
9152 Value32 |=PHY_AN_AD_1000XPAUSE;
9153 }
9154 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9155 {
9156 Value32 |= PHY_AN_AD_1000XPSE_ASYM;
9157 }
9158 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9159 {
9160 Value32 |= (PHY_AN_AD_1000XPSE_ASYM | PHY_AN_AD_1000XPAUSE);
9161 }
9162
9163 }else{
9164
9165 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9166 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9167 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9168 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9169 {
9170 Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
9171 }
9172 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9173 {
9174 Value32 |= PHY_AN_AD_ASYM_PAUSE;
9175 }
9176 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9177 {
9178 Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
9179 }
9180 }
9181 }
9182
9183 return Value32;
9184 }
9185
9186
9187
9188 /******************************************************************************/
9189 /* Description: */
9190 /* */
9191 /* Return: */
9192 /* LM_STATUS_FAILURE */
9193 /* LM_STATUS_SUCCESS */
9194 /* */
9195 /******************************************************************************/
9196 static LM_STATUS
9197 LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice)
9198 {
9199 LM_LINE_SPEED LineSpeed;
9200 LM_DUPLEX_MODE DuplexMode;
9201 LM_UINT32 NewPhyCtrl;
9202 LM_UINT32 Value32, PhyReg18;
9203 LM_UINT32 Cnt;
9204
9205 /* Get the interface type, line speed, and duplex mode. */
9206 LineSpeed = pDevice->RequestedLineSpeed;
9207 DuplexMode = pDevice->RequestedDuplexMode;
9208
9209 /* Exit ext. loop back, in case it was in ext. loopback mode */
9210 /* Set Extended packet length bit on chips that support jumbo frames */
9211 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9212 {
9213 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
9214
9215 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9216 Value32 |= 1; /* set tx elastic fifo */
9217 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9218
9219 }
9220 else
9221 {
9222 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9223 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9224 PhyReg18 &= ~0x8000; /* clear external loop back */
9225
9226 if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
9227 {
9228 PhyReg18 |= 0x4000; /* set extended packet length */
9229 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9230 Value32 |= 1; /* set tx elastic fifo */
9231 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9232 }
9233 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9234 }
9235
9236 #ifdef BCM_WOL
9237 if (pDevice->RestoreOnWakeUp)
9238 {
9239 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9240 pDevice->advertising1000 = 0;
9241 Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
9242 if (pDevice->WolSpeed == WOL_SPEED_100MB)
9243 {
9244 Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
9245 }
9246 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9247 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9248 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9249 pDevice->advertising = Value32;
9250 }
9251 /* Setup the auto-negotiation advertisement register. */
9252 else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9253 #else
9254 /* Setup the auto-negotiation advertisement register. */
9255 if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9256 #endif
9257 {
9258 /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
9259 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | PHY_AN_AD_ALL_SPEEDS;
9260 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9261
9262 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9263 pDevice->advertising = Value32;
9264
9265 /* Advertise 1000Mbps */
9266 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
9267 {
9268 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS;
9269
9270 #ifdef INCLUDE_5701_AX_FIX
9271 /* slave mode. This will force the PHY to operate in */
9272 /* master mode. */
9273 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9274 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
9275 {
9276 Value32 |= BCM540X_CONFIG_AS_MASTER |
9277 BCM540X_ENABLE_CONFIG_AS_MASTER;
9278 }
9279 #endif
9280
9281 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9282 pDevice->advertising1000 = Value32;
9283 }
9284 else
9285 {
9286 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9287 pDevice->advertising1000 = 0;
9288 }
9289 }
9290 else
9291 {
9292 if ((pDevice->PhyFlags & PHY_NO_GIGABIT) &&
9293 (LineSpeed == LM_LINE_SPEED_1000MBPS))
9294 {
9295 LineSpeed = LM_LINE_SPEED_100MBPS;
9296 }
9297 if(LineSpeed == LM_LINE_SPEED_1000MBPS)
9298 {
9299 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9300 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9301
9302 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9303 pDevice->advertising = Value32;
9304
9305 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9306 {
9307 Value32 = BCM540X_AN_AD_1000BASET_HALF;
9308 }
9309 else
9310 {
9311 Value32 = BCM540X_AN_AD_1000BASET_FULL;
9312 }
9313
9314 #ifdef INCLUDE_5701_AX_FIX
9315 if ((pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE) ||
9316 (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9317 pDevice->ChipRevId == T3_CHIP_ID_5701_B0))
9318 #else
9319 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9320 #endif
9321 {
9322 Value32 |= BCM540X_CONFIG_AS_MASTER |
9323 BCM540X_ENABLE_CONFIG_AS_MASTER;
9324 }
9325 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9326 pDevice->advertising1000 = Value32;
9327 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9328 {
9329 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9330 {
9331 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x8c20);
9332 }
9333 else
9334 {
9335 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9336 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9337 PhyReg18 |= 0x8000; /* set loop back */
9338 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9339 }
9340 }
9341 }
9342 else if(LineSpeed == LM_LINE_SPEED_100MBPS)
9343 {
9344 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9345 pDevice->advertising1000 = 0;
9346
9347 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9348 {
9349 Value32 = PHY_AN_AD_100BASETX_HALF;
9350 }
9351 else
9352 {
9353 Value32 = PHY_AN_AD_100BASETX_FULL;
9354 }
9355
9356 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9357 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9358
9359 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9360 pDevice->advertising = Value32;
9361 }
9362 else if(LineSpeed == LM_LINE_SPEED_10MBPS)
9363 {
9364 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9365 pDevice->advertising1000 = 0;
9366
9367 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9368 {
9369 Value32 = PHY_AN_AD_10BASET_HALF;
9370 }
9371 else
9372 {
9373 Value32 = PHY_AN_AD_10BASET_FULL;
9374 }
9375
9376 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9377 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9378
9379 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9380 pDevice->advertising = Value32;
9381 }
9382 }
9383
9384 /* Force line speed if auto-negotiation is disabled. */
9385 if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
9386 {
9387 /* This code path is executed only when there is link. */
9388 pDevice->LineSpeed = LineSpeed;
9389 pDevice->DuplexMode = DuplexMode;
9390
9391 /* Force line seepd. */
9392 NewPhyCtrl = 0;
9393 switch(LineSpeed)
9394 {
9395 case LM_LINE_SPEED_10MBPS:
9396 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
9397 break;
9398 case LM_LINE_SPEED_100MBPS:
9399 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
9400 break;
9401 case LM_LINE_SPEED_1000MBPS:
9402 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9403 break;
9404 default:
9405 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9406 break;
9407 }
9408
9409 if(DuplexMode == LM_DUPLEX_MODE_FULL)
9410 {
9411 NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
9412 }
9413
9414 /* Don't do anything if the PHY_CTRL is already what we wanted. */
9415 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
9416 if(Value32 != NewPhyCtrl)
9417 {
9418 /* Temporary bring the link down before forcing line speed. */
9419 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
9420
9421 /* Wait for link to go down. */
9422 for(Cnt = 0; Cnt < 1500; Cnt++)
9423 {
9424 MM_Wait(10);
9425
9426 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9427 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9428
9429 if(!(Value32 & PHY_STATUS_LINK_PASS))
9430 {
9431 MM_Wait(40);
9432 break;
9433 }
9434 }
9435
9436 LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
9437 MM_Wait(40);
9438 }
9439 }
9440 else
9441 {
9442 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
9443 PHY_CTRL_RESTART_AUTO_NEG);
9444 }
9445
9446 return LM_STATUS_SUCCESS;
9447 } /* LM_ForceAutoNegBcm540xPhy */
9448
9449 /******************************************************************************/
9450 /* Description: */
9451 /* */
9452 /* Return: */
9453 /******************************************************************************/
9454 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
9455 PT3_FWIMG_INFO pFwImg,
9456 LM_UINT32 LoadCpu,
9457 LM_UINT32 StartCpu)
9458 {
9459 LM_UINT32 i;
9460 LM_UINT32 address;
9461 LM_VOID (*Wr_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register,LM_UINT32 Value32);
9462 LM_UINT32 (*Rd_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register);
9463 LM_UINT32 len;
9464 LM_UINT32 base_addr;
9465
9466 /* BCM4785: Avoid all use of firmware. */
9467 if (pDevice->Flags & SB_CORE_FLAG)
9468 return LM_STATUS_FAILURE;
9469
9470 #ifdef INCLUDE_TCP_SEG_SUPPORT
9471 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
9472 {
9473 Wr_fn = LM_MemWrInd;
9474 Rd_fn = LM_MemRdInd;
9475 len = LM_GetStkOffLdFirmwareSize(pDevice);
9476 base_addr = T3_NIC_BCM5705_MBUF_POOL_ADDR;
9477 }
9478 else
9479 #endif
9480 {
9481 Wr_fn = LM_RegWrInd;
9482 Rd_fn = LM_RegRdInd;
9483 len = T3_RX_CPU_SPAD_SIZE;
9484 base_addr = T3_RX_CPU_SPAD_ADDR;
9485 }
9486
9487 if (LoadCpu & T3_RX_CPU_ID)
9488 {
9489 if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
9490 {
9491 return LM_STATUS_FAILURE;
9492 }
9493
9494 /* First of all clear scrach pad memory */
9495 for (i = 0; i < len; i+=4)
9496 {
9497 Wr_fn(pDevice,base_addr+i,0);
9498 }
9499
9500 /* Copy code first */
9501 address = base_addr + (pFwImg->Text.Offset & 0xffff);
9502 for (i = 0; i <= pFwImg->Text.Length; i+=4)
9503 {
9504 Wr_fn(pDevice,address+i,
9505 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9506 }
9507
9508 address = base_addr + (pFwImg->ROnlyData.Offset & 0xffff);
9509 for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
9510 {
9511 Wr_fn(pDevice,address+i,
9512 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9513 }
9514
9515 address = base_addr + (pFwImg->Data.Offset & 0xffff);
9516 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9517 {
9518 Wr_fn(pDevice,address+i,
9519 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9520 }
9521 }
9522
9523 if ((LoadCpu & T3_TX_CPU_ID) &&
9524 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9525 {
9526 if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
9527 {
9528 return LM_STATUS_FAILURE;
9529 }
9530
9531 /* First of all clear scrach pad memory */
9532 for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
9533 {
9534 Wr_fn(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
9535 }
9536
9537 /* Copy code first */
9538 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
9539 for (i= 0; i <= pFwImg->Text.Length; i+=4)
9540 {
9541 Wr_fn(pDevice,address+i,
9542 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9543 }
9544
9545 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
9546 for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
9547 {
9548 Wr_fn(pDevice,address+i,
9549 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9550 }
9551
9552 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
9553 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9554 {
9555 Wr_fn(pDevice,address+i,
9556 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9557 }
9558 }
9559
9560 if (StartCpu & T3_RX_CPU_ID)
9561 {
9562 /* Start Rx CPU */
9563 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9564 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9565 for (i = 0 ; i < 5; i++)
9566 {
9567 if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
9568 break;
9569
9570 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9571 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9572 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9573 REG_RD_BACK(pDevice,rxCpu.reg.PC);
9574 MM_Wait(1000);
9575 }
9576
9577 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9578 REG_WR(pDevice,rxCpu.reg.mode, 0);
9579 }
9580
9581 if ((StartCpu & T3_TX_CPU_ID) &&
9582 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9583 {
9584 /* Start Tx CPU */
9585 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9586 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9587 for (i = 0 ; i < 5; i++)
9588 {
9589 if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
9590 break;
9591
9592 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9593 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9594 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9595 REG_RD_BACK(pDevice,txCpu.reg.PC);
9596 MM_Wait(1000);
9597 }
9598
9599 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9600 REG_WR(pDevice,txCpu.reg.mode, 0);
9601 }
9602
9603 return LM_STATUS_SUCCESS;
9604 }
9605
9606 LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
9607 {
9608 LM_UINT32 i;
9609 LM_STATUS status;
9610
9611 status = LM_STATUS_SUCCESS;
9612
9613 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) &&
9614 !(cpu_number & T3_RX_CPU_ID))
9615 {
9616 return status;
9617 }
9618
9619 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9620 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9621 {
9622 status = LM_NVRAM_AcquireLock(pDevice);
9623 }
9624
9625 if (cpu_number & T3_RX_CPU_ID)
9626 {
9627 for (i = 0 ; i < 10000; i++)
9628 {
9629 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9630 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9631
9632 if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
9633 break;
9634 }
9635
9636 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9637 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9638 REG_RD_BACK(pDevice,rxCpu.reg.mode);
9639 MM_Wait(10);
9640
9641 if (i == 10000)
9642 status = LM_STATUS_FAILURE;
9643 }
9644
9645 /*
9646 * BCM4785: There is only an Rx CPU for the 5750 derivative in
9647 * the 4785. Don't go any further in this code in order to
9648 * avoid access to the NVRAM arbitration register.
9649 */
9650 if (pDevice->Flags & SB_CORE_FLAG)
9651 return status;
9652
9653 if ((pDevice->Flags & T3_HAS_TWO_CPUS) &&
9654 (cpu_number & T3_TX_CPU_ID))
9655 {
9656 for (i = 0 ; i < 10000; i++)
9657 {
9658 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9659 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9660
9661 if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
9662 break;
9663 }
9664
9665 if (i == 10000)
9666 status = LM_STATUS_FAILURE;
9667 }
9668
9669 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9670 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9671 {
9672 if (status != LM_STATUS_SUCCESS)
9673 {
9674 /*
9675 * Some part of this operation failed.
9676 * Just undo our own actions.
9677 */
9678 LM_NVRAM_ReleaseLock(pDevice);
9679 }
9680 else if (!(pDevice->Flags & T3_HAS_TWO_CPUS) ||
9681 cpu_number == (T3_TX_CPU_ID | T3_RX_CPU_ID))
9682 {
9683 /*
9684 * Release our NVRAM arbitration grant along
9685 * with the firmware's arbitration request bit.
9686 */
9687 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9688 REG_RD_BACK(pDevice, Nvram.SwArb);
9689 }
9690 else
9691 {
9692 LM_NVRAM_ReleaseLock(pDevice);
9693
9694 if (LM_NVRAM_AcquireLock(pDevice) == LM_STATUS_SUCCESS)
9695 {
9696 /* All is well. Release the arbitration and continue. */
9697 LM_NVRAM_ReleaseLock(pDevice);
9698 }
9699 else
9700 {
9701 /*
9702 * We've timed out while attempting to get the
9703 * NVRAM arbitration. Assume the cause is that
9704 * the NVRAM has requested arbitration after we
9705 * acquired arbitration the first time, but before
9706 * the CPU was actually halted.
9707 */
9708
9709 /*
9710 * Release our NVRAM arbitration grant along
9711 * with the firmware's arbitration request bit.
9712 */
9713 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9714 REG_RD_BACK(pDevice, Nvram.SwArb);
9715 }
9716 }
9717 }
9718
9719 return status;
9720 }
9721
9722
9723 LM_STATUS
9724 LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
9725 {
9726 int j;
9727 int ret = LM_STATUS_SUCCESS;
9728
9729 if(BlinkDurationSec == 0)
9730 {
9731 BlinkDurationSec = 1;
9732 }
9733 if(BlinkDurationSec > 120)
9734 {
9735 BlinkDurationSec = 120;
9736 }
9737
9738 for(j = 0; j < BlinkDurationSec * 2; j++)
9739 {
9740 if(j % 2)
9741 {
9742 // Turn on the LEDs.
9743 REG_WR(pDevice, MacCtrl.LedCtrl,
9744 LED_CTRL_OVERRIDE_LINK_LED |
9745 LED_CTRL_1000MBPS_LED_ON |
9746 LED_CTRL_100MBPS_LED_ON |
9747 LED_CTRL_10MBPS_LED_ON |
9748 LED_CTRL_OVERRIDE_TRAFFIC_LED |
9749 LED_CTRL_BLINK_TRAFFIC_LED |
9750 LED_CTRL_TRAFFIC_LED);
9751 }
9752 else
9753 {
9754 // Turn off the LEDs.
9755 REG_WR(pDevice, MacCtrl.LedCtrl,
9756 LED_CTRL_OVERRIDE_LINK_LED |
9757 LED_CTRL_OVERRIDE_TRAFFIC_LED);
9758 }
9759 if (MM_Sleep(pDevice, 500) != LM_STATUS_SUCCESS)/* 0.5 second */
9760 {
9761 ret = LM_STATUS_FAILURE;
9762 break;
9763 }
9764 }
9765 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
9766 return ret;
9767 }
9768
9769 LM_STATUS
9770 LM_SwitchClocks(PLM_DEVICE_BLOCK pDevice)
9771 {
9772 LM_UINT32 ClockCtrl;
9773
9774 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9775 return LM_STATUS_SUCCESS;
9776
9777 ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl);
9778 pDevice->ClockCtrl = ClockCtrl & (T3_PCI_FORCE_CLKRUN |
9779 T3_PCI_CLKRUN_OUTPUT_EN | 0x1f);
9780 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9781 {
9782 if (ClockCtrl & T3_PCI_625_CORE_CLOCK)
9783 {
9784 /* clear ALT clock first */
9785 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9786 T3_PCI_625_CORE_CLOCK);
9787 MM_Wait(40); /* required delay is 27usec */
9788 }
9789 }
9790 else
9791 {
9792 if (ClockCtrl & T3_PCI_44MHZ_CORE_CLOCK)
9793 {
9794 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9795 T3_PCI_44MHZ_CORE_CLOCK | T3_PCI_SELECT_ALTERNATE_CLOCK);
9796 MM_Wait(40); /* required delay is 27usec */
9797 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9798 T3_PCI_SELECT_ALTERNATE_CLOCK);
9799 MM_Wait(40); /* required delay is 27usec */
9800 }
9801 }
9802
9803 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
9804 MM_Wait(40); /* required delay is 27usec */
9805 return LM_STATUS_SUCCESS;
9806 }
9807
9808 int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
9809 LM_PHYSICAL_ADDRESS host_addr_phy, int length,
9810 int dma_read)
9811 {
9812 T3_DMA_DESC dma_desc;
9813 int i;
9814 LM_UINT32 dma_desc_addr;
9815 LM_UINT32 value32;
9816
9817 REG_WR(pDevice, BufMgr.Mode, 0);
9818 REG_WR(pDevice, Ftq.Reset, 0);
9819
9820 dma_desc.host_addr.High = host_addr_phy.High;
9821 dma_desc.host_addr.Low = host_addr_phy.Low;
9822 dma_desc.nic_mbuf = 0x2100;
9823 dma_desc.len = length;
9824 dma_desc.flags = 0x00000005; /* Generate Rx-CPU event */
9825
9826 if (dma_read)
9827 {
9828 dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
9829 T3_QID_DMA_HIGH_PRI_READ;
9830 REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
9831 }
9832 else
9833 {
9834 dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
9835 T3_QID_DMA_HIGH_PRI_WRITE;
9836 REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
9837 }
9838
9839 dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
9840
9841 /* Writing this DMA descriptor to DMA memory */
9842 for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
9843 {
9844 value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
9845 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
9846 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG,
9847 MM_SWAP_LE32(value32));
9848 }
9849 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
9850
9851 if (dma_read)
9852 REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
9853 else
9854 REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
9855
9856 for (i = 0; i < 40; i++)
9857 {
9858 if (dma_read)
9859 value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
9860 else
9861 value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
9862
9863 if ((value32 & 0xffff) == dma_desc_addr)
9864 break;
9865
9866 MM_Wait(10);
9867 }
9868
9869 return LM_STATUS_SUCCESS;
9870 }
9871
9872 STATIC LM_STATUS
9873 LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
9874 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
9875 {
9876 int j;
9877 LM_UINT32 *ptr;
9878 int dma_success = 0;
9879 LM_STATUS ret = LM_STATUS_FAILURE;
9880
9881 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
9882 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
9883 {
9884 return LM_STATUS_SUCCESS;
9885 }
9886 while (!dma_success)
9887 {
9888 /* Fill data with incremental patterns */
9889 ptr = (LM_UINT32 *)pBufferVirt;
9890 for (j = 0; j < BufferSize/4; j++)
9891 *ptr++ = j;
9892
9893 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
9894 {
9895 goto LM_DmaTestDone;
9896 }
9897
9898 MM_Wait(40);
9899 ptr = (LM_UINT32 *)pBufferVirt;
9900 /* Fill data with zero */
9901 for (j = 0; j < BufferSize/4; j++)
9902 *ptr++ = 0;
9903
9904 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
9905 {
9906 goto LM_DmaTestDone;
9907 }
9908
9909 MM_Wait(40);
9910 /* Check for data */
9911 ptr = (LM_UINT32 *)pBufferVirt;
9912 for (j = 0; j < BufferSize/4; j++)
9913 {
9914 if (*ptr++ != j)
9915 {
9916 if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
9917 != DMA_CTRL_WRITE_BOUNDARY_16)
9918 {
9919 pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
9920 ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
9921 DMA_CTRL_WRITE_BOUNDARY_16;
9922 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
9923 pDevice->DmaReadWriteCtrl);
9924 break;
9925 }
9926 else
9927 {
9928 goto LM_DmaTestDone;
9929 }
9930 }
9931 }
9932 if (j == (BufferSize/4))
9933 dma_success = 1;
9934 }
9935 ret = LM_STATUS_SUCCESS;
9936 LM_DmaTestDone:
9937 memset(pBufferVirt, 0, BufferSize);
9938 return ret;
9939 }
9940
9941 void
9942 LM_Add32To64Counter(LM_UINT32 Counter32, T3_64BIT_REGISTER *Counter64)
9943 {
9944 Counter64->Low += Counter32;
9945 if (Counter64->Low < Counter32)
9946 {
9947 Counter64->High++;
9948 }
9949 }
9950
9951 LM_STATUS
9952 LM_GetStats(PLM_DEVICE_BLOCK pDevice)
9953 {
9954 PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt;
9955
9956 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9957 {
9958 return LM_STATUS_FAILURE;
9959 }
9960
9961 if (pStats == 0)
9962 {
9963 return LM_STATUS_FAILURE;
9964 }
9965 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutOctets),
9966 &pStats->ifHCOutOctets);
9967 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsCollisions),
9968 &pStats->etherStatsCollisions);
9969 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXonSent),
9970 &pStats->outXonSent);
9971 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXoffSent),
9972 &pStats->outXoffSent);
9973 LM_Add32To64Counter(REG_RD(pDevice,
9974 MacCtrl.dot3StatsInternalMacTransmitErrors),
9975 &pStats->dot3StatsInternalMacTransmitErrors);
9976 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsSingleCollisionFrames),
9977 &pStats->dot3StatsSingleCollisionFrames);
9978 LM_Add32To64Counter(REG_RD(pDevice,
9979 MacCtrl.dot3StatsMultipleCollisionFrames),
9980 &pStats->dot3StatsMultipleCollisionFrames);
9981 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsDeferredTransmissions),
9982 &pStats->dot3StatsDeferredTransmissions);
9983 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsExcessiveCollisions),
9984 &pStats->dot3StatsExcessiveCollisions);
9985 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsLateCollisions),
9986 &pStats->dot3StatsLateCollisions);
9987 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutUcastPkts),
9988 &pStats->ifHCOutUcastPkts);
9989 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutMulticastPkts),
9990 &pStats->ifHCOutMulticastPkts);
9991 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutBroadcastPkts),
9992 &pStats->ifHCOutBroadcastPkts);
9993 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInOctets),
9994 &pStats->ifHCInOctets);
9995 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsFragments),
9996 &pStats->etherStatsFragments);
9997 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInUcastPkts),
9998 &pStats->ifHCInUcastPkts);
9999 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInMulticastPkts),
10000 &pStats->ifHCInMulticastPkts);
10001 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInBroadcastPkts),
10002 &pStats->ifHCInBroadcastPkts);
10003 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFCSErrors),
10004 &pStats->dot3StatsFCSErrors);
10005 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsAlignmentErrors),
10006 &pStats->dot3StatsAlignmentErrors);
10007 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xonPauseFramesReceived),
10008 &pStats->xonPauseFramesReceived);
10009 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffPauseFramesReceived),
10010 &pStats->xoffPauseFramesReceived);
10011 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.macControlFramesReceived),
10012 &pStats->macControlFramesReceived);
10013 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffStateEntered),
10014 &pStats->xoffStateEntered);
10015 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFramesTooLong),
10016 &pStats->dot3StatsFramesTooLong);
10017 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsJabbers),
10018 &pStats->etherStatsJabbers);
10019 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsUndersizePkts),
10020 &pStats->etherStatsUndersizePkts);
10021
10022 return LM_STATUS_SUCCESS;
10023 }
Tomato firmware and modifications.