release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/ssb/ssb.h

   1 #ifndef LINUX_SSB_H_
   2 #define LINUX_SSB_H_
   3
   4 #include <linux/device.h>
   5 #include <linux/list.h>
   6 #include <linux/types.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/pci.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/dma-mapping.h>
  11
  12 #include <linux/ssb/ssb_regs.h>
  13
  14
  15 struct pcmcia_device;
  16 struct ssb_bus;
  17 struct ssb_driver;
  18
  19 struct ssb_sprom {
  20         u8 revision;
  21         u8 il0mac[6];           /* MAC address for 802.11b/g */
  22         u8 et0mac[6];           /* MAC address for Ethernet */
  23         u8 et1mac[6];           /* MAC address for 802.11a */
  24         u8 et0phyaddr;          /* MII address for enet0 */
  25         u8 et1phyaddr;          /* MII address for enet1 */
  26         u8 et0mdcport;          /* MDIO for enet0 */
  27         u8 et1mdcport;          /* MDIO for enet1 */
  28         u8 board_rev;           /* Board revision number from SPROM. */
  29         u8 country_code;        /* Country Code */
  30         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
  31         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
  32         u16 pa0b0;
  33         u16 pa0b1;
  34         u16 pa0b2;
  35         u16 pa1b0;
  36         u16 pa1b1;
  37         u16 pa1b2;
  38         u16 pa1lob0;
  39         u16 pa1lob1;
  40         u16 pa1lob2;
  41         u16 pa1hib0;
  42         u16 pa1hib1;
  43         u16 pa1hib2;
  44         u8 gpio0;               /* GPIO pin 0 */
  45         u8 gpio1;               /* GPIO pin 1 */
  46         u8 gpio2;               /* GPIO pin 2 */
  47         u8 gpio3;               /* GPIO pin 3 */
  48         u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
  49         u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
  50         u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
  51         u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
  52         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
  53         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
  54         u8 tri2g;               /* 2.4GHz TX isolation */
  55         u8 tri5gl;              /* 5.2GHz TX isolation */
  56         u8 tri5g;               /* 5.3GHz TX isolation */
  57         u8 tri5gh;              /* 5.8GHz TX isolation */
  58         u8 rxpo2g;              /* 2GHz RX power offset */
  59         u8 rxpo5g;              /* 5GHz RX power offset */
  60         u8 rssisav2g;           /* 2GHz RSSI params */
  61         u8 rssismc2g;
  62         u8 rssismf2g;
  63         u8 bxa2g;               /* 2GHz BX arch */
  64         u8 rssisav5g;           /* 5GHz RSSI params */
  65         u8 rssismc5g;
  66         u8 rssismf5g;
  67         u8 bxa5g;               /* 5GHz BX arch */
  68         u16 cck2gpo;            /* CCK power offset */
  69         u32 ofdm2gpo;           /* 2.4GHz OFDM power offset */
  70         u32 ofdm5glpo;          /* 5.2GHz OFDM power offset */
  71         u32 ofdm5gpo;           /* 5.3GHz OFDM power offset */
  72         u32 ofdm5ghpo;          /* 5.8GHz OFDM power offset */
  73         u16 boardflags_lo;      /* Board flags (bits 0-15) */
  74         u16 boardflags_hi;      /* Board flags (bits 16-31) */
  75         u16 boardflags2_lo;     /* Board flags (bits 32-47) */
  76         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
  77         /* TODO store board flags in a single u64 */
  78
  79         /* Antenna gain values for up to 4 antennas
  80          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
  81          * loss in the connectors is bigger than the gain. */
  82         struct {
  83                 struct {
  84                         s8 a0, a1, a2, a3;
  85                 } ghz24;        /* 2.4GHz band */
  86                 struct {
  87                         s8 a0, a1, a2, a3;
  88                 } ghz5;         /* 5GHz band */
  89         } antenna_gain;
  90
  91         /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
  92 };
  93
  94 /* Information about the PCB the circuitry is soldered on. */
  95 struct ssb_boardinfo {
  96         u16 vendor;
  97         u16 type;
  98         u16 rev;
  99 };
 100
 101
 102 struct ssb_device;
 103 /* Lowlevel read/write operations on the device MMIO.
 104  * Internal, don't use that outside of ssb. */
 105 struct ssb_bus_ops {
 106         u8 (*read8)(struct ssb_device *dev, u16 offset);
 107         u16 (*read16)(struct ssb_device *dev, u16 offset);
 108         u32 (*read32)(struct ssb_device *dev, u16 offset);
 109         void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
 110         void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
 111         void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
 112 #ifdef CONFIG_SSB_BLOCKIO
 113         void (*block_read)(struct ssb_device *dev, void *buffer,
 114                            size_t count, u16 offset, u8 reg_width);
 115         void (*block_write)(struct ssb_device *dev, const void *buffer,
 116                             size_t count, u16 offset, u8 reg_width);
 117 #endif
 118 };
 119
 120
 121 /* Core-ID values. */
 122 #define SSB_DEV_CHIPCOMMON      0x800
 123 #define SSB_DEV_ILINE20         0x801
 124 #define SSB_DEV_SDRAM           0x803
 125 #define SSB_DEV_PCI             0x804
 126 #define SSB_DEV_MIPS            0x805
 127 #define SSB_DEV_ETHERNET        0x806
 128 #define SSB_DEV_V90             0x807
 129 #define SSB_DEV_USB11_HOSTDEV   0x808
 130 #define SSB_DEV_ADSL            0x809
 131 #define SSB_DEV_ILINE100        0x80A
 132 #define SSB_DEV_IPSEC           0x80B
 133 #define SSB_DEV_PCMCIA          0x80D
 134 #define SSB_DEV_INTERNAL_MEM    0x80E
 135 #define SSB_DEV_MEMC_SDRAM      0x80F
 136 #define SSB_DEV_EXTIF           0x811
 137 #define SSB_DEV_80211           0x812
 138 #define SSB_DEV_MIPS_3302       0x816
 139 #define SSB_DEV_USB11_HOST      0x817
 140 #define SSB_DEV_USB11_DEV       0x818
 141 #define SSB_DEV_USB20_HOST      0x819
 142 #define SSB_DEV_USB20_DEV       0x81A
 143 #define SSB_DEV_SDIO_HOST       0x81B
 144 #define SSB_DEV_ROBOSWITCH      0x81C
 145 #define SSB_DEV_PARA_ATA        0x81D
 146 #define SSB_DEV_SATA_XORDMA     0x81E
 147 #define SSB_DEV_ETHERNET_GBIT   0x81F
 148 #define SSB_DEV_PCIE            0x820
 149 #define SSB_DEV_MIMO_PHY        0x821
 150 #define SSB_DEV_SRAM_CTRLR      0x822
 151 #define SSB_DEV_MINI_MACPHY     0x823
 152 #define SSB_DEV_ARM_1176        0x824
 153 #define SSB_DEV_ARM_7TDMI       0x825
 154
 155 /* Vendor-ID values */
 156 #define SSB_VENDOR_BROADCOM     0x4243
 157
 158 struct __ssb_dev_wrapper {
 159         struct device dev;
 160         struct ssb_device *sdev;
 161 };
 162
 163 struct ssb_device {
 164         /* Having a copy of the ops pointer in each dev struct
 165          * is an optimization. */
 166         const struct ssb_bus_ops *ops;
 167
 168         struct device *dev, *dma_dev;
 169
 170         struct ssb_bus *bus;
 171         struct ssb_device_id id;
 172
 173         u8 core_index;
 174         unsigned int irq;
 175
 176         /* Internal-only stuff follows. */
 177         void *drvdata;          /* Per-device data */
 178         void *devtypedata;      /* Per-devicetype (eg 802.11) data */
 179 };
 180
 181 /* Go from struct device to struct ssb_device. */
 182 static inline
 183 struct ssb_device * dev_to_ssb_dev(struct device *dev)
 184 {
 185         struct __ssb_dev_wrapper *wrap;
 186         wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
 187         return wrap->sdev;
 188 }
 189
 190 /* Device specific user data */
 191 static inline
 192 void ssb_set_drvdata(struct ssb_device *dev, void *data)
 193 {
 194         dev->drvdata = data;
 195 }
 196 static inline
 197 void * ssb_get_drvdata(struct ssb_device *dev)
 198 {
 199         return dev->drvdata;
 200 }
 201
 202 /* Devicetype specific user data. This is per device-type (not per device) */
 203 void ssb_set_devtypedata(struct ssb_device *dev, void *data);
 204 static inline
 205 void * ssb_get_devtypedata(struct ssb_device *dev)
 206 {
 207         return dev->devtypedata;
 208 }
 209
 210
 211 struct ssb_driver {
 212         const char *name;
 213         const struct ssb_device_id *id_table;
 214
 215         int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
 216         void (*remove)(struct ssb_device *dev);
 217         int (*suspend)(struct ssb_device *dev, pm_message_t state);
 218         int (*resume)(struct ssb_device *dev);
 219         void (*shutdown)(struct ssb_device *dev);
 220
 221         struct device_driver drv;
 222 };
 223 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
 224
 225 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
 226 static inline int ssb_driver_register(struct ssb_driver *drv)
 227 {
 228         return __ssb_driver_register(drv, THIS_MODULE);
 229 }
 230 extern void ssb_driver_unregister(struct ssb_driver *drv);
 231
 232
 233
 234
 235 enum ssb_bustype {
 236         SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
 237         SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
 238         SSB_BUSTYPE_PCMCIA,     /* SSB is connected to PCMCIA bus */
 239         SSB_BUSTYPE_SDIO,       /* SSB is connected to SDIO bus */
 240 };
 241
 242 /* board_vendor */
 243 #define SSB_BOARDVENDOR_BCM     0x14E4  /* Broadcom */
 244 #define SSB_BOARDVENDOR_DELL    0x1028  /* Dell */
 245 #define SSB_BOARDVENDOR_HP      0x0E11  /* HP */
 246 /* board_type */
 247 #define SSB_BOARD_BCM94306MP    0x0418
 248 #define SSB_BOARD_BCM4309G      0x0421
 249 #define SSB_BOARD_BCM4306CB     0x0417
 250 #define SSB_BOARD_BCM4309MP     0x040C
 251 #define SSB_BOARD_MP4318        0x044A
 252 #define SSB_BOARD_BU4306        0x0416
 253 #define SSB_BOARD_BU4309        0x040A
 254 /* chip_package */
 255 #define SSB_CHIPPACK_BCM4712S   1       /* Small 200pin 4712 */
 256 #define SSB_CHIPPACK_BCM4712M   2       /* Medium 225pin 4712 */
 257 #define SSB_CHIPPACK_BCM4712L   0       /* Large 340pin 4712 */
 258
 259 #include <linux/ssb/ssb_driver_chipcommon.h>
 260 #include <linux/ssb/ssb_driver_mips.h>
 261 #include <linux/ssb/ssb_driver_extif.h>
 262 #include <linux/ssb/ssb_driver_pci.h>
 263
 264 struct ssb_bus {
 265         /* The MMIO area. */
 266         void __iomem *mmio;
 267
 268         const struct ssb_bus_ops *ops;
 269
 270         /* The core currently mapped into the MMIO window.
 271          * Not valid on all host-buses. So don't use outside of SSB. */
 272         struct ssb_device *mapped_device;
 273         union {
 274                 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
 275                 u8 mapped_pcmcia_seg;
 276                 /* Current SSB base address window for SDIO. */
 277                 u32 sdio_sbaddr;
 278         };
 279         /* Lock for core and segment switching.
 280          * On PCMCIA-host busses this is used to protect the whole MMIO access. */
 281         spinlock_t bar_lock;
 282
 283         /* The host-bus this backplane is running on. */
 284         enum ssb_bustype bustype;
 285         /* Pointers to the host-bus. Check bustype before using any of these pointers. */
 286         union {
 287                 /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
 288                 struct pci_dev *host_pci;
 289                 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
 290                 struct pcmcia_device *host_pcmcia;
 291                 /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
 292                 struct sdio_func *host_sdio;
 293         };
 294
 295         /* See enum ssb_quirks */
 296         unsigned int quirks;
 297
 298 #ifdef CONFIG_SSB_SPROM
 299         /* Mutex to protect the SPROM writing. */
 300         struct mutex sprom_mutex;
 301 #endif
 302
 303         /* ID information about the Chip. */
 304         u16 chip_id;
 305         u16 chip_rev;
 306         u16 sprom_offset;
 307         u16 sprom_size;         /* number of words in sprom */
 308         u8 chip_package;
 309
 310         /* List of devices (cores) on the backplane. */
 311         struct ssb_device devices[SSB_MAX_NR_CORES];
 312         u8 nr_devices;
 313
 314         /* Software ID number for this bus. */
 315         unsigned int busnumber;
 316
 317         /* The ChipCommon device (if available). */
 318         struct ssb_chipcommon chipco;
 319         /* The PCI-core device (if available). */
 320         struct ssb_pcicore pcicore;
 321         /* The MIPS-core device (if available). */
 322         struct ssb_mipscore mipscore;
 323         /* The EXTif-core device (if available). */
 324         struct ssb_extif extif;
 325
 326         /* The following structure elements are not available in early
 327          * SSB initialization. Though, they are available for regular
 328          * registered drivers at any stage. So be careful when
 329          * using them in the ssb core code. */
 330
 331         /* ID information about the PCB. */
 332         struct ssb_boardinfo boardinfo;
 333         /* Contents of the SPROM. */
 334         struct ssb_sprom sprom;
 335         /* If the board has a cardbus slot, this is set to true. */
 336         bool has_cardbus_slot;
 337
 338 #ifdef CONFIG_SSB_EMBEDDED
 339         /* Lock for GPIO register access. */
 340         spinlock_t gpio_lock;
 341 #endif /* EMBEDDED */
 342
 343         /* Internal-only stuff follows. Do not touch. */
 344         struct list_head list;
 345 #ifdef CONFIG_SSB_DEBUG
 346         /* Is the bus already powered up? */
 347         bool powered_up;
 348         int power_warn_count;
 349 #endif /* DEBUG */
 350 };
 351
 352 enum ssb_quirks {
 353         /* SDIO connected card requires performing a read after writing a 32-bit value */
 354         SSB_QUIRK_SDIO_READ_AFTER_WRITE32       = (1 << 0),
 355 };
 356
 357 /* The initialization-invariants. */
 358 struct ssb_init_invariants {
 359         /* Versioning information about the PCB. */
 360         struct ssb_boardinfo boardinfo;
 361         /* The SPROM information. That's either stored in an
 362          * EEPROM or NVRAM on the board. */
 363         struct ssb_sprom sprom;
 364         /* If the board has a cardbus slot, this is set to true. */
 365         bool has_cardbus_slot;
 366 };
 367 /* Type of function to fetch the invariants. */
 368 typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
 369                                      struct ssb_init_invariants *iv);
 370
 371 /* Register a SSB system bus. get_invariants() is called after the
 372  * basic system devices are initialized.
 373  * The invariants are usually fetched from some NVRAM.
 374  * Put the invariants into the struct pointed to by iv. */
 375 extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
 376                                    unsigned long baseaddr,
 377                                    ssb_invariants_func_t get_invariants);
 378 #ifdef CONFIG_SSB_PCIHOST
 379 extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
 380                                    struct pci_dev *host_pci);
 381 #endif /* CONFIG_SSB_PCIHOST */
 382 #ifdef CONFIG_SSB_PCMCIAHOST
 383 extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
 384                                       struct pcmcia_device *pcmcia_dev,
 385                                       unsigned long baseaddr);
 386 #endif /* CONFIG_SSB_PCMCIAHOST */
 387 #ifdef CONFIG_SSB_SDIOHOST
 388 extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
 389                                     struct sdio_func *sdio_func,
 390                                     unsigned int quirks);
 391 #endif /* CONFIG_SSB_SDIOHOST */
 392
 393
 394 extern void ssb_bus_unregister(struct ssb_bus *bus);
 395
 396 /* Does the device have an SPROM? */
 397 extern bool ssb_is_sprom_available(struct ssb_bus *bus);
 398
 399 /* Set a fallback SPROM.
 400  * See kdoc at the function definition for complete documentation. */
 401 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
 402
 403 /* Suspend a SSB bus.
 404  * Call this from the parent bus suspend routine. */
 405 extern int ssb_bus_suspend(struct ssb_bus *bus);
 406 /* Resume a SSB bus.
 407  * Call this from the parent bus resume routine. */
 408 extern int ssb_bus_resume(struct ssb_bus *bus);
 409
 410 extern u32 ssb_clockspeed(struct ssb_bus *bus);
 411
 412 /* Is the device enabled in hardware? */
 413 int ssb_device_is_enabled(struct ssb_device *dev);
 414 /* Enable a device and pass device-specific SSB_TMSLOW flags.
 415  * If no device-specific flags are available, use 0. */
 416 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
 417 /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
 418 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
 419
 420
 421 /* Device MMIO register read/write functions. */
 422 static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
 423 {
 424         return dev->ops->read8(dev, offset);
 425 }
 426 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
 427 {
 428         return dev->ops->read16(dev, offset);
 429 }
 430 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
 431 {
 432         return dev->ops->read32(dev, offset);
 433 }
 434 static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
 435 {
 436         dev->ops->write8(dev, offset, value);
 437 }
 438 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
 439 {
 440         dev->ops->write16(dev, offset, value);
 441 }
 442 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
 443 {
 444         dev->ops->write32(dev, offset, value);
 445 }
 446 #ifdef CONFIG_SSB_BLOCKIO
 447 static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
 448                                   size_t count, u16 offset, u8 reg_width)
 449 {
 450         dev->ops->block_read(dev, buffer, count, offset, reg_width);
 451 }
 452
 453 static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
 454                                    size_t count, u16 offset, u8 reg_width)
 455 {
 456         dev->ops->block_write(dev, buffer, count, offset, reg_width);
 457 }
 458 #endif /* CONFIG_SSB_BLOCKIO */
 459
 460
 461 /* The SSB DMA API. Use this API for any DMA operation on the device.
 462  * This API basically is a wrapper that calls the correct DMA API for
 463  * the host device type the SSB device is attached to. */
 464
 465 /* Translation (routing) bits that need to be ORed to DMA
 466  * addresses before they are given to a device. */
 467 extern u32 ssb_dma_translation(struct ssb_device *dev);
 468 #define SSB_DMA_TRANSLATION_MASK        0xC0000000
 469 #define SSB_DMA_TRANSLATION_SHIFT       30
 470
 471 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
 472 {
 473 #ifdef CONFIG_SSB_DEBUG
 474         printk(KERN_ERR "SSB: BUG! Calling DMA API for "
 475                "unsupported bustype %d\n", dev->bus->bustype);
 476 #endif /* DEBUG */
 477 }
 478
 479 #ifdef CONFIG_SSB_PCIHOST
 480 /* PCI-host wrapper driver */
 481 extern int ssb_pcihost_register(struct pci_driver *driver);
 482 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
 483 {
 484         pci_unregister_driver(driver);
 485 }
 486
 487 static inline
 488 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
 489 {
 490         if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
 491                 pci_set_power_state(sdev->bus->host_pci, state);
 492 }
 493 #else
 494 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
 495 {
 496 }
 497
 498 static inline
 499 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
 500 {
 501 }
 502 #endif /* CONFIG_SSB_PCIHOST */
 503
 504
 505 /* If a driver is shutdown or suspended, call this to signal
 506  * that the bus may be completely powered down. SSB will decide,
 507  * if it's really time to power down the bus, based on if there
 508  * are other devices that want to run. */
 509 extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
 510 /* Before initializing and enabling a device, call this to power-up the bus.
 511  * If you want to allow use of dynamic-power-control, pass the flag.
 512  * Otherwise static always-on powercontrol will be used. */
 513 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
 514
 515
 516 /* Various helper functions */
 517 extern u32 ssb_admatch_base(u32 adm);
 518 extern u32 ssb_admatch_size(u32 adm);
 519
 520 /* PCI device mapping and fixup routines.
 521  * Called from the architecture pcibios init code.
 522  * These are only available on SSB_EMBEDDED configurations. */
 523 #ifdef CONFIG_SSB_EMBEDDED
 524 int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
 525 int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 526 #endif /* CONFIG_SSB_EMBEDDED */
 527
 528 #endif /* LINUX_SSB_H_ */