release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/via/share.h

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #ifndef __SHARE_H__
  23 #define __SHARE_H__
  24
  25 /* Define Return Value */
  26 #define FAIL        -1
  27 #define OK          1
  28
  29 #ifndef NULL
  30 #define NULL 0
  31 #endif
  32
  33 /* Define Bit Field */
  34 #define BIT0    0x01
  35 #define BIT1    0x02
  36 #define BIT2    0x04
  37 #define BIT3    0x08
  38 #define BIT4    0x10
  39 #define BIT5    0x20
  40 #define BIT6    0x40
  41 #define BIT7    0x80
  42
  43 /* Video Memory Size */
  44 #define VIDEO_MEMORY_SIZE_16M    0x1000000
  45
  46 /*
  47  * Lengths of the VPIT structure arrays.
  48  */
  49 #define StdCR       0x19
  50 #define StdSR       0x04
  51 #define StdGR       0x09
  52 #define StdAR       0x14
  53
  54 #define PatchCR     11
  55
  56 /* Display path */
  57 #define IGA1        1
  58 #define IGA2        2
  59
  60 /* Define Color Depth  */
  61 #define MODE_8BPP       1
  62 #define MODE_16BPP      2
  63 #define MODE_32BPP      4
  64
  65 #define GR20    0x20
  66 #define GR21    0x21
  67 #define GR22    0x22
  68
  69 /* Sequencer Registers */
  70 #define SR01    0x01
  71 #define SR10    0x10
  72 #define SR12    0x12
  73 #define SR15    0x15
  74 #define SR16    0x16
  75 #define SR17    0x17
  76 #define SR18    0x18
  77 #define SR1B    0x1B
  78 #define SR1A    0x1A
  79 #define SR1C    0x1C
  80 #define SR1D    0x1D
  81 #define SR1E    0x1E
  82 #define SR1F    0x1F
  83 #define SR20    0x20
  84 #define SR21    0x21
  85 #define SR22    0x22
  86 #define SR2A    0x2A
  87 #define SR2D    0x2D
  88 #define SR2E    0x2E
  89
  90 #define SR30    0x30
  91 #define SR39    0x39
  92 #define SR3D    0x3D
  93 #define SR3E    0x3E
  94 #define SR3F    0x3F
  95 #define SR40    0x40
  96 #define SR43    0x43
  97 #define SR44    0x44
  98 #define SR45    0x45
  99 #define SR46    0x46
 100 #define SR47    0x47
 101 #define SR48    0x48
 102 #define SR49    0x49
 103 #define SR4A    0x4A
 104 #define SR4B    0x4B
 105 #define SR4C    0x4C
 106 #define SR52    0x52
 107 #define SR57    0x57
 108 #define SR58    0x58
 109 #define SR59    0x59
 110 #define SR5D    0x5D
 111 #define SR5E    0x5E
 112 #define SR65    0x65
 113
 114 /* CRT Controller Registers */
 115 #define CR00    0x00
 116 #define CR01    0x01
 117 #define CR02    0x02
 118 #define CR03    0x03
 119 #define CR04    0x04
 120 #define CR05    0x05
 121 #define CR06    0x06
 122 #define CR07    0x07
 123 #define CR08    0x08
 124 #define CR09    0x09
 125 #define CR0A    0x0A
 126 #define CR0B    0x0B
 127 #define CR0C    0x0C
 128 #define CR0D    0x0D
 129 #define CR0E    0x0E
 130 #define CR0F    0x0F
 131 #define CR10    0x10
 132 #define CR11    0x11
 133 #define CR12    0x12
 134 #define CR13    0x13
 135 #define CR14    0x14
 136 #define CR15    0x15
 137 #define CR16    0x16
 138 #define CR17    0x17
 139 #define CR18    0x18
 140
 141 /* Extend CRT Controller Registers */
 142 #define CR30    0x30
 143 #define CR31    0x31
 144 #define CR32    0x32
 145 #define CR33    0x33
 146 #define CR34    0x34
 147 #define CR35    0x35
 148 #define CR36    0x36
 149 #define CR37    0x37
 150 #define CR38    0x38
 151 #define CR39    0x39
 152 #define CR3A    0x3A
 153 #define CR3B    0x3B
 154 #define CR3C    0x3C
 155 #define CR3D    0x3D
 156 #define CR3E    0x3E
 157 #define CR3F    0x3F
 158 #define CR40    0x40
 159 #define CR41    0x41
 160 #define CR42    0x42
 161 #define CR43    0x43
 162 #define CR44    0x44
 163 #define CR45    0x45
 164 #define CR46    0x46
 165 #define CR47    0x47
 166 #define CR48    0x48
 167 #define CR49    0x49
 168 #define CR4A    0x4A
 169 #define CR4B    0x4B
 170 #define CR4C    0x4C
 171 #define CR4D    0x4D
 172 #define CR4E    0x4E
 173 #define CR4F    0x4F
 174 #define CR50    0x50
 175 #define CR51    0x51
 176 #define CR52    0x52
 177 #define CR53    0x53
 178 #define CR54    0x54
 179 #define CR55    0x55
 180 #define CR56    0x56
 181 #define CR57    0x57
 182 #define CR58    0x58
 183 #define CR59    0x59
 184 #define CR5A    0x5A
 185 #define CR5B    0x5B
 186 #define CR5C    0x5C
 187 #define CR5D    0x5D
 188 #define CR5E    0x5E
 189 #define CR5F    0x5F
 190 #define CR60    0x60
 191 #define CR61    0x61
 192 #define CR62    0x62
 193 #define CR63    0x63
 194 #define CR64    0x64
 195 #define CR65    0x65
 196 #define CR66    0x66
 197 #define CR67    0x67
 198 #define CR68    0x68
 199 #define CR69    0x69
 200 #define CR6A    0x6A
 201 #define CR6B    0x6B
 202 #define CR6C    0x6C
 203 #define CR6D    0x6D
 204 #define CR6E    0x6E
 205 #define CR6F    0x6F
 206 #define CR70    0x70
 207 #define CR71    0x71
 208 #define CR72    0x72
 209 #define CR73    0x73
 210 #define CR74    0x74
 211 #define CR75    0x75
 212 #define CR76    0x76
 213 #define CR77    0x77
 214 #define CR78    0x78
 215 #define CR79    0x79
 216 #define CR7A    0x7A
 217 #define CR7B    0x7B
 218 #define CR7C    0x7C
 219 #define CR7D    0x7D
 220 #define CR7E    0x7E
 221 #define CR7F    0x7F
 222 #define CR80    0x80
 223 #define CR81    0x81
 224 #define CR82    0x82
 225 #define CR83    0x83
 226 #define CR84    0x84
 227 #define CR85    0x85
 228 #define CR86    0x86
 229 #define CR87    0x87
 230 #define CR88    0x88
 231 #define CR89    0x89
 232 #define CR8A    0x8A
 233 #define CR8B    0x8B
 234 #define CR8C    0x8C
 235 #define CR8D    0x8D
 236 #define CR8E    0x8E
 237 #define CR8F    0x8F
 238 #define CR90    0x90
 239 #define CR91    0x91
 240 #define CR92    0x92
 241 #define CR93    0x93
 242 #define CR94    0x94
 243 #define CR95    0x95
 244 #define CR96    0x96
 245 #define CR97    0x97
 246 #define CR98    0x98
 247 #define CR99    0x99
 248 #define CR9A    0x9A
 249 #define CR9B    0x9B
 250 #define CR9C    0x9C
 251 #define CR9D    0x9D
 252 #define CR9E    0x9E
 253 #define CR9F    0x9F
 254 #define CRA0    0xA0
 255 #define CRA1    0xA1
 256 #define CRA2    0xA2
 257 #define CRA3    0xA3
 258 #define CRD2    0xD2
 259 #define CRD3    0xD3
 260 #define CRD4    0xD4
 261
 262 /* LUT Table*/
 263 #define LUT_DATA             0x3C9      /* DACDATA */
 264 #define LUT_INDEX_READ       0x3C7      /* DACRX */
 265 #define LUT_INDEX_WRITE      0x3C8      /* DACWX */
 266 #define DACMASK              0x3C6
 267
 268 /* Definition Device */
 269 #define DEVICE_CRT  0x01
 270 #define DEVICE_DVI  0x03
 271 #define DEVICE_LCD  0x04
 272
 273 /* Device output interface */
 274 #define INTERFACE_NONE          0x00
 275 #define INTERFACE_ANALOG_RGB    0x01
 276 #define INTERFACE_DVP0          0x02
 277 #define INTERFACE_DVP1          0x03
 278 #define INTERFACE_DFP_HIGH      0x04
 279 #define INTERFACE_DFP_LOW       0x05
 280 #define INTERFACE_DFP           0x06
 281 #define INTERFACE_LVDS0         0x07
 282 #define INTERFACE_LVDS1         0x08
 283 #define INTERFACE_LVDS0LVDS1    0x09
 284 #define INTERFACE_TMDS          0x0A
 285
 286 #define HW_LAYOUT_LCD_ONLY      0x01
 287 #define HW_LAYOUT_DVI_ONLY      0x02
 288 #define HW_LAYOUT_LCD_DVI       0x03
 289 #define HW_LAYOUT_LCD1_LCD2     0x04
 290 #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
 291
 292 /* Definition Refresh Rate */
 293 #define REFRESH_50      50
 294 #define REFRESH_60      60
 295 #define REFRESH_75      75
 296 #define REFRESH_85      85
 297 #define REFRESH_100     100
 298 #define REFRESH_120     120
 299
 300 /* Definition Sync Polarity*/
 301 #define NEGATIVE        1
 302 #define POSITIVE        0
 303
 304 /*480x640@60 Sync Polarity (GTF)
 305 */
 306 #define M480X640_R60_HSP        NEGATIVE
 307 #define M480X640_R60_VSP        POSITIVE
 308
 309 /*640x480@60 Sync Polarity (VESA Mode)
 310 */
 311 #define M640X480_R60_HSP        NEGATIVE
 312 #define M640X480_R60_VSP        NEGATIVE
 313
 314 /*640x480@75 Sync Polarity (VESA Mode)
 315 */
 316 #define M640X480_R75_HSP        NEGATIVE
 317 #define M640X480_R75_VSP        NEGATIVE
 318
 319 /*640x480@85 Sync Polarity (VESA Mode)
 320 */
 321 #define M640X480_R85_HSP        NEGATIVE
 322 #define M640X480_R85_VSP        NEGATIVE
 323
 324 /*640x480@100 Sync Polarity (GTF Mode)
 325 */
 326 #define M640X480_R100_HSP       NEGATIVE
 327 #define M640X480_R100_VSP       POSITIVE
 328
 329 /*640x480@120 Sync Polarity (GTF Mode)
 330 */
 331 #define M640X480_R120_HSP       NEGATIVE
 332 #define M640X480_R120_VSP       POSITIVE
 333
 334 /*720x480@60 Sync Polarity  (GTF Mode)
 335 */
 336 #define M720X480_R60_HSP        NEGATIVE
 337 #define M720X480_R60_VSP        POSITIVE
 338
 339 /*720x576@60 Sync Polarity  (GTF Mode)
 340 */
 341 #define M720X576_R60_HSP        NEGATIVE
 342 #define M720X576_R60_VSP        POSITIVE
 343
 344 /*800x600@60 Sync Polarity (VESA Mode)
 345 */
 346 #define M800X600_R60_HSP        POSITIVE
 347 #define M800X600_R60_VSP        POSITIVE
 348
 349 /*800x600@75 Sync Polarity (VESA Mode)
 350 */
 351 #define M800X600_R75_HSP        POSITIVE
 352 #define M800X600_R75_VSP        POSITIVE
 353
 354 /*800x600@85 Sync Polarity (VESA Mode)
 355 */
 356 #define M800X600_R85_HSP        POSITIVE
 357 #define M800X600_R85_VSP        POSITIVE
 358
 359 /*800x600@100 Sync Polarity (GTF Mode)
 360 */
 361 #define M800X600_R100_HSP       NEGATIVE
 362 #define M800X600_R100_VSP       POSITIVE
 363
 364 /*800x600@120 Sync Polarity (GTF Mode)
 365 */
 366 #define M800X600_R120_HSP       NEGATIVE
 367 #define M800X600_R120_VSP       POSITIVE
 368
 369 /*800x480@60 Sync Polarity  (CVT Mode)
 370 */
 371 #define M800X480_R60_HSP        NEGATIVE
 372 #define M800X480_R60_VSP        POSITIVE
 373
 374 /*848x480@60 Sync Polarity  (CVT Mode)
 375 */
 376 #define M848X480_R60_HSP        NEGATIVE
 377 #define M848X480_R60_VSP        POSITIVE
 378
 379 /*852x480@60 Sync Polarity  (GTF Mode)
 380 */
 381 #define M852X480_R60_HSP        NEGATIVE
 382 #define M852X480_R60_VSP        POSITIVE
 383
 384 /*1024x512@60 Sync Polarity (GTF Mode)
 385 */
 386 #define M1024X512_R60_HSP       NEGATIVE
 387 #define M1024X512_R60_VSP       POSITIVE
 388
 389 /*1024x600@60 Sync Polarity (GTF Mode)
 390 */
 391 #define M1024X600_R60_HSP       NEGATIVE
 392 #define M1024X600_R60_VSP       POSITIVE
 393
 394 /*1024x768@60 Sync Polarity (VESA Mode)
 395 */
 396 #define M1024X768_R60_HSP       NEGATIVE
 397 #define M1024X768_R60_VSP       NEGATIVE
 398
 399 /*1024x768@75 Sync Polarity (VESA Mode)
 400 */
 401 #define M1024X768_R75_HSP       POSITIVE
 402 #define M1024X768_R75_VSP       POSITIVE
 403
 404 /*1024x768@85 Sync Polarity (VESA Mode)
 405 */
 406 #define M1024X768_R85_HSP       POSITIVE
 407 #define M1024X768_R85_VSP       POSITIVE
 408
 409 /*1024x768@100 Sync Polarity (GTF Mode)
 410 */
 411 #define M1024X768_R100_HSP      NEGATIVE
 412 #define M1024X768_R100_VSP      POSITIVE
 413
 414 /*1152x864@75 Sync Polarity (VESA Mode)
 415 */
 416 #define M1152X864_R75_HSP       POSITIVE
 417 #define M1152X864_R75_VSP       POSITIVE
 418
 419 /*1280x720@60 Sync Polarity  (GTF Mode)
 420 */
 421 #define M1280X720_R60_HSP       NEGATIVE
 422 #define M1280X720_R60_VSP       POSITIVE
 423
 424 /* 1280x768@50 Sync Polarity  (GTF Mode) */
 425 #define M1280X768_R50_HSP       NEGATIVE
 426 #define M1280X768_R50_VSP       POSITIVE
 427
 428 /*1280x768@60 Sync Polarity  (GTF Mode)
 429 */
 430 #define M1280X768_R60_HSP       NEGATIVE
 431 #define M1280X768_R60_VSP       POSITIVE
 432
 433 /*1280x800@60 Sync Polarity  (CVT Mode)
 434 */
 435 #define M1280X800_R60_HSP       NEGATIVE
 436 #define M1280X800_R60_VSP       POSITIVE
 437
 438 /*1280x960@60 Sync Polarity (VESA Mode)
 439 */
 440 #define M1280X960_R60_HSP       POSITIVE
 441 #define M1280X960_R60_VSP       POSITIVE
 442
 443 /*1280x1024@60 Sync Polarity (VESA Mode)
 444 */
 445 #define M1280X1024_R60_HSP      POSITIVE
 446 #define M1280X1024_R60_VSP      POSITIVE
 447
 448 /* 1360x768@60 Sync Polarity (CVT Mode) */
 449 #define M1360X768_R60_HSP       POSITIVE
 450 #define M1360X768_R60_VSP       POSITIVE
 451
 452 /* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
 453 #define M1360X768_RB_R60_HSP       POSITIVE
 454 #define M1360X768_RB_R60_VSP       NEGATIVE
 455
 456 /* 1368x768@50 Sync Polarity (GTF Mode) */
 457 #define M1368X768_R50_HSP       NEGATIVE
 458 #define M1368X768_R50_VSP       POSITIVE
 459
 460 /* 1368x768@60 Sync Polarity (VESA Mode) */
 461 #define M1368X768_R60_HSP       NEGATIVE
 462 #define M1368X768_R60_VSP       POSITIVE
 463
 464 /*1280x1024@75 Sync Polarity (VESA Mode)
 465 */
 466 #define M1280X1024_R75_HSP      POSITIVE
 467 #define M1280X1024_R75_VSP      POSITIVE
 468
 469 /*1280x1024@85 Sync Polarity (VESA Mode)
 470 */
 471 #define M1280X1024_R85_HSP      POSITIVE
 472 #define M1280X1024_R85_VSP      POSITIVE
 473
 474 /*1440x1050@60 Sync Polarity (GTF Mode)
 475 */
 476 #define M1440X1050_R60_HSP      NEGATIVE
 477 #define M1440X1050_R60_VSP      POSITIVE
 478
 479 /*1600x1200@60 Sync Polarity (VESA Mode)
 480 */
 481 #define M1600X1200_R60_HSP      POSITIVE
 482 #define M1600X1200_R60_VSP      POSITIVE
 483
 484 /*1600x1200@75 Sync Polarity (VESA Mode)
 485 */
 486 #define M1600X1200_R75_HSP      POSITIVE
 487 #define M1600X1200_R75_VSP      POSITIVE
 488
 489 /* 1680x1050@60 Sync Polarity (CVT Mode) */
 490 #define M1680x1050_R60_HSP      NEGATIVE
 491 #define M1680x1050_R60_VSP      NEGATIVE
 492
 493 /* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
 494 #define M1680x1050_RB_R60_HSP      POSITIVE
 495 #define M1680x1050_RB_R60_VSP      NEGATIVE
 496
 497 /* 1680x1050@75 Sync Polarity (CVT Mode) */
 498 #define M1680x1050_R75_HSP      NEGATIVE
 499 #define M1680x1050_R75_VSP      POSITIVE
 500
 501 /*1920x1080@60 Sync Polarity (CVT Mode)
 502 */
 503 #define M1920X1080_R60_HSP      NEGATIVE
 504 #define M1920X1080_R60_VSP      POSITIVE
 505
 506 /* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
 507 #define M1920X1080_RB_R60_HSP  POSITIVE
 508 #define M1920X1080_RB_R60_VSP  NEGATIVE
 509
 510 /*1920x1440@60 Sync Polarity (VESA Mode)
 511 */
 512 #define M1920X1440_R60_HSP      NEGATIVE
 513 #define M1920X1440_R60_VSP      POSITIVE
 514
 515 /*1920x1440@75 Sync Polarity (VESA Mode)
 516 */
 517 #define M1920X1440_R75_HSP      NEGATIVE
 518 #define M1920X1440_R75_VSP      POSITIVE
 519
 520
 521 /* 1400x1050@60 Sync Polarity (CVT Mode) */
 522 #define M1400X1050_R60_HSP      NEGATIVE
 523 #define M1400X1050_R60_VSP      POSITIVE
 524
 525 /* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
 526 #define M1400X1050_RB_R60_HSP      POSITIVE
 527 #define M1400X1050_RB_R60_VSP      NEGATIVE
 528
 529 /* 1400x1050@75 Sync Polarity (CVT Mode) */
 530 #define M1400X1050_R75_HSP      NEGATIVE
 531 #define M1400X1050_R75_VSP      POSITIVE
 532
 533 /* 960x600@60 Sync Polarity (CVT Mode) */
 534 #define M960X600_R60_HSP        NEGATIVE
 535 #define M960X600_R60_VSP        POSITIVE
 536
 537 /* 1000x600@60 Sync Polarity (GTF Mode) */
 538 #define M1000X600_R60_HSP       NEGATIVE
 539 #define M1000X600_R60_VSP       POSITIVE
 540
 541 /* 1024x576@60 Sync Polarity (GTF Mode) */
 542 #define M1024X576_R60_HSP       NEGATIVE
 543 #define M1024X576_R60_VSP       POSITIVE
 544
 545 /*1024x600@60 Sync Polarity (GTF Mode)*/
 546 #define M1024X600_R60_HSP       NEGATIVE
 547 #define M1024X600_R60_VSP       POSITIVE
 548
 549 /* 1088x612@60 Sync Polarity (CVT Mode) */
 550 #define M1088X612_R60_HSP       NEGATIVE
 551 #define M1088X612_R60_VSP       POSITIVE
 552
 553 /* 1152x720@60 Sync Polarity (CVT Mode) */
 554 #define M1152X720_R60_HSP       NEGATIVE
 555 #define M1152X720_R60_VSP       POSITIVE
 556
 557 /* 1200x720@60 Sync Polarity (GTF Mode) */
 558 #define M1200X720_R60_HSP       NEGATIVE
 559 #define M1200X720_R60_VSP       POSITIVE
 560
 561 /* 1200x900@60 Sync Polarity (DCON) */
 562 #define M1200X900_R60_HSP       NEGATIVE
 563 #define M1200X900_R60_VSP       NEGATIVE
 564
 565 /* 1280x600@60 Sync Polarity (GTF Mode) */
 566 #define M1280x600_R60_HSP       NEGATIVE
 567 #define M1280x600_R60_VSP       POSITIVE
 568
 569 /* 1280x720@50 Sync Polarity  (GTF Mode) */
 570 #define M1280X720_R50_HSP       NEGATIVE
 571 #define M1280X720_R50_VSP       POSITIVE
 572
 573 /* 1280x720@60 Sync Polarity  (CEA Mode) */
 574 #define M1280X720_CEA_R60_HSP       POSITIVE
 575 #define M1280X720_CEA_R60_VSP       POSITIVE
 576
 577 /* 1440x900@60 Sync Polarity (CVT Mode) */
 578 #define M1440X900_R60_HSP       NEGATIVE
 579 #define M1440X900_R60_VSP       POSITIVE
 580
 581 /* 1440x900@75 Sync Polarity (CVT Mode) */
 582 #define M1440X900_R75_HSP       NEGATIVE
 583 #define M1440X900_R75_VSP       POSITIVE
 584
 585 /* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
 586 #define M1440X900_RB_R60_HSP       POSITIVE
 587 #define M1440X900_RB_R60_VSP       NEGATIVE
 588
 589 /* 1600x900@60 Sync Polarity (CVT Mode) */
 590 #define M1600X900_R60_HSP       NEGATIVE
 591 #define M1600X900_R60_VSP       POSITIVE
 592
 593 /* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
 594 #define M1600X900_RB_R60_HSP       POSITIVE
 595 #define M1600X900_RB_R60_VSP       NEGATIVE
 596
 597 /* 1600x1024@60 Sync Polarity (GTF Mode) */
 598 #define M1600X1024_R60_HSP      NEGATIVE
 599 #define M1600X1024_R60_VSP      POSITIVE
 600
 601 /* 1792x1344@60 Sync Polarity (DMT Mode) */
 602 #define M1792x1344_R60_HSP      NEGATIVE
 603 #define M1792x1344_R60_VSP      POSITIVE
 604
 605 /* 1856x1392@60 Sync Polarity (DMT Mode) */
 606 #define M1856x1392_R60_HSP      NEGATIVE
 607 #define M1856x1392_R60_VSP      POSITIVE
 608
 609 /* 1920x1200@60 Sync Polarity (CVT Mode) */
 610 #define M1920X1200_R60_HSP      NEGATIVE
 611 #define M1920X1200_R60_VSP      POSITIVE
 612
 613 /* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
 614 #define M1920X1200_RB_R60_HSP  POSITIVE
 615 #define M1920X1200_RB_R60_VSP  NEGATIVE
 616
 617 /* 1920x1080@60 Sync Polarity  (CEA Mode) */
 618 #define M1920X1080_CEA_R60_HSP       POSITIVE
 619 #define M1920X1080_CEA_R60_VSP       POSITIVE
 620
 621 /* 2048x1536@60 Sync Polarity (CVT Mode) */
 622 #define M2048x1536_R60_HSP      NEGATIVE
 623 #define M2048x1536_R60_VSP      POSITIVE
 624
 625 /* define PLL index: */
 626 #define CLK_25_175M     25175000
 627 #define CLK_26_880M     26880000
 628 #define CLK_29_581M     29581000
 629 #define CLK_31_500M     31500000
 630 #define CLK_31_728M     31728000
 631 #define CLK_32_668M     32688000
 632 #define CLK_36_000M     36000000
 633 #define CLK_40_000M     40000000
 634 #define CLK_41_291M     41291000
 635 #define CLK_43_163M     43163000
 636 #define CLK_45_250M     45250000        /* 45.46MHz */
 637 #define CLK_46_000M     46000000
 638 #define CLK_46_996M     46996000
 639 #define CLK_48_000M     48000000
 640 #define CLK_48_875M     48875000
 641 #define CLK_49_500M     49500000
 642 #define CLK_52_406M     52406000
 643 #define CLK_52_977M     52977000
 644 #define CLK_56_250M     56250000
 645 #define CLK_57_275M     57275000
 646 #define CLK_60_466M     60466000
 647 #define CLK_61_500M     61500000
 648 #define CLK_65_000M     65000000
 649 #define CLK_65_178M     65178000
 650 #define CLK_66_750M     66750000        /* 67.116MHz */
 651 #define CLK_68_179M     68179000
 652 #define CLK_69_924M     69924000
 653 #define CLK_70_159M     70159000
 654 #define CLK_72_000M     72000000
 655 #define CLK_74_270M     74270000
 656 #define CLK_78_750M     78750000
 657 #define CLK_80_136M     80136000
 658 #define CLK_83_375M     83375000
 659 #define CLK_83_950M     83950000
 660 #define CLK_84_750M     84750000        /* 84.537Mhz */
 661 #define CLK_85_860M     85860000
 662 #define CLK_88_750M     88750000
 663 #define CLK_94_500M     94500000
 664 #define CLK_97_750M     97750000
 665 #define CLK_101_000M    101000000
 666 #define CLK_106_500M    106500000
 667 #define CLK_108_000M    108000000
 668 #define CLK_113_309M    113309000
 669 #define CLK_118_840M    118840000
 670 #define CLK_119_000M    119000000
 671 #define CLK_121_750M    121750000       /* 121.704MHz */
 672 #define CLK_125_104M    125104000
 673 #define CLK_135_000M    135000000
 674 #define CLK_136_700M    136700000
 675 #define CLK_138_400M    138400000
 676 #define CLK_146_760M    146760000
 677 #define CLK_148_500M    148500000
 678
 679 #define CLK_153_920M    153920000
 680 #define CLK_156_000M    156000000
 681 #define CLK_157_500M    157500000
 682 #define CLK_162_000M    162000000
 683 #define CLK_187_000M    187000000
 684 #define CLK_193_295M    193295000
 685 #define CLK_202_500M    202500000
 686 #define CLK_204_000M    204000000
 687 #define CLK_218_500M    218500000
 688 #define CLK_234_000M    234000000
 689 #define CLK_267_250M    267250000
 690 #define CLK_297_500M    297500000
 691 #define CLK_74_481M     74481000
 692 #define CLK_172_798M    172798000
 693 #define CLK_122_614M    122614000
 694
 695
 696 /* Definition CRTC Timing Index */
 697 #define H_TOTAL_INDEX               0
 698 #define H_ADDR_INDEX                1
 699 #define H_BLANK_START_INDEX         2
 700 #define H_BLANK_END_INDEX           3
 701 #define H_SYNC_START_INDEX          4
 702 #define H_SYNC_END_INDEX            5
 703 #define V_TOTAL_INDEX               6
 704 #define V_ADDR_INDEX                7
 705 #define V_BLANK_START_INDEX         8
 706 #define V_BLANK_END_INDEX           9
 707 #define V_SYNC_START_INDEX          10
 708 #define V_SYNC_END_INDEX            11
 709 #define H_TOTAL_SHADOW_INDEX        12
 710 #define H_BLANK_END_SHADOW_INDEX    13
 711 #define V_TOTAL_SHADOW_INDEX        14
 712 #define V_ADDR_SHADOW_INDEX         15
 713 #define V_BLANK_SATRT_SHADOW_INDEX  16
 714 #define V_BLANK_END_SHADOW_INDEX    17
 715 #define V_SYNC_SATRT_SHADOW_INDEX   18
 716 #define V_SYNC_END_SHADOW_INDEX     19
 717
 718 /* Definition Video Mode Pixel Clock (picoseconds)
 719 */
 720 #define RES_480X640_60HZ_PIXCLOCK    39722
 721 #define RES_640X480_60HZ_PIXCLOCK    39722
 722 #define RES_640X480_75HZ_PIXCLOCK    31747
 723 #define RES_640X480_85HZ_PIXCLOCK    27777
 724 #define RES_640X480_100HZ_PIXCLOCK   23168
 725 #define RES_640X480_120HZ_PIXCLOCK   19081
 726 #define RES_720X480_60HZ_PIXCLOCK    37020
 727 #define RES_720X576_60HZ_PIXCLOCK    30611
 728 #define RES_800X600_60HZ_PIXCLOCK    25000
 729 #define RES_800X600_75HZ_PIXCLOCK    20203
 730 #define RES_800X600_85HZ_PIXCLOCK    17777
 731 #define RES_800X600_100HZ_PIXCLOCK   14667
 732 #define RES_800X600_120HZ_PIXCLOCK   11912
 733 #define RES_800X480_60HZ_PIXCLOCK    33805
 734 #define RES_848X480_60HZ_PIXCLOCK    31756
 735 #define RES_856X480_60HZ_PIXCLOCK    31518
 736 #define RES_1024X512_60HZ_PIXCLOCK   24218
 737 #define RES_1024X600_60HZ_PIXCLOCK   20460
 738 #define RES_1024X768_60HZ_PIXCLOCK   15385
 739 #define RES_1024X768_75HZ_PIXCLOCK   12699
 740 #define RES_1024X768_85HZ_PIXCLOCK   10582
 741 #define RES_1024X768_100HZ_PIXCLOCK  8825
 742 #define RES_1152X864_75HZ_PIXCLOCK   9259
 743 #define RES_1280X768_60HZ_PIXCLOCK   12480
 744 #define RES_1280X800_60HZ_PIXCLOCK   11994
 745 #define RES_1280X960_60HZ_PIXCLOCK   9259
 746 #define RES_1280X1024_60HZ_PIXCLOCK  9260
 747 #define RES_1280X1024_75HZ_PIXCLOCK  7408
 748 #define RES_1280X768_85HZ_PIXCLOCK   6349
 749 #define RES_1440X1050_60HZ_PIXCLOCK  7993
 750 #define RES_1600X1200_60HZ_PIXCLOCK  6172
 751 #define RES_1600X1200_75HZ_PIXCLOCK  4938
 752 #define RES_1280X720_60HZ_PIXCLOCK   13426
 753 #define RES_1200X900_60HZ_PIXCLOCK   17459
 754 #define RES_1920X1080_60HZ_PIXCLOCK  5787
 755 #define RES_1400X1050_60HZ_PIXCLOCK  8214
 756 #define RES_1400X1050_75HZ_PIXCLOCK  6410
 757 #define RES_1368X768_60HZ_PIXCLOCK   11647
 758 #define RES_960X600_60HZ_PIXCLOCK      22099
 759 #define RES_1000X600_60HZ_PIXCLOCK    20834
 760 #define RES_1024X576_60HZ_PIXCLOCK    21278
 761 #define RES_1088X612_60HZ_PIXCLOCK    18877
 762 #define RES_1152X720_60HZ_PIXCLOCK    14981
 763 #define RES_1200X720_60HZ_PIXCLOCK    14253
 764 #define RES_1280X600_60HZ_PIXCLOCK    16260
 765 #define RES_1280X720_50HZ_PIXCLOCK    16538
 766 #define RES_1280X768_50HZ_PIXCLOCK    15342
 767 #define RES_1366X768_50HZ_PIXCLOCK    14301
 768 #define RES_1366X768_60HZ_PIXCLOCK    11646
 769 #define RES_1360X768_60HZ_PIXCLOCK    11799
 770 #define RES_1440X900_60HZ_PIXCLOCK    9390
 771 #define RES_1440X900_75HZ_PIXCLOCK    7315
 772 #define RES_1600X900_60HZ_PIXCLOCK    8415
 773 #define RES_1600X1024_60HZ_PIXCLOCK   7315
 774 #define RES_1680X1050_60HZ_PIXCLOCK   6814
 775 #define RES_1680X1050_75HZ_PIXCLOCK   5348
 776 #define RES_1792X1344_60HZ_PIXCLOCK   4902
 777 #define RES_1856X1392_60HZ_PIXCLOCK   4577
 778 #define RES_1920X1200_60HZ_PIXCLOCK   5173
 779 #define RES_1920X1440_60HZ_PIXCLOCK   4274
 780 #define RES_1920X1440_75HZ_PIXCLOCK   3367
 781 #define RES_2048X1536_60HZ_PIXCLOCK   3742
 782
 783 #define RES_1360X768_RB_60HZ_PIXCLOCK 13889
 784 #define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
 785 #define RES_1440X900_RB_60HZ_PIXCLOCK   11268
 786 #define RES_1600X900_RB_60HZ_PIXCLOCK   10230
 787 #define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
 788 #define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
 789 #define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
 790
 791 /* LCD display method
 792 */
 793 #define     LCD_EXPANDSION              0x00
 794 #define     LCD_CENTERING               0x01
 795
 796 /* LCD mode
 797 */
 798 #define     LCD_OPENLDI               0x00
 799 #define     LCD_SPWG                  0x01
 800
 801 /* Define display timing
 802 */
 803 struct display_timing {
 804         u16 hor_total;
 805         u16 hor_addr;
 806         u16 hor_blank_start;
 807         u16 hor_blank_end;
 808         u16 hor_sync_start;
 809         u16 hor_sync_end;
 810         u16 ver_total;
 811         u16 ver_addr;
 812         u16 ver_blank_start;
 813         u16 ver_blank_end;
 814         u16 ver_sync_start;
 815         u16 ver_sync_end;
 816 };
 817
 818 struct crt_mode_table {
 819         int refresh_rate;
 820         unsigned long clk;
 821         int h_sync_polarity;
 822         int v_sync_polarity;
 823         struct display_timing crtc;
 824 };
 825
 826 struct io_reg {
 827         int port;
 828         u8 index;
 829         u8 mask;
 830         u8 value;
 831 };
 832
 833 #endif /* __SHARE_H__ */