2 * OMAP1 internal LCD controller
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/err.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/vmalloc.h>
30 #include <linux/clk.h>
31 #include <linux/gfp.h>
33 #include <mach/lcdc.h>
36 #include <asm/mach-types.h>
42 #define MODULE_NAME "lcdc"
44 #define MAX_PALETTE_SIZE PAGE_SIZE
47 OMAP_LCDC_LOAD_PALETTE
,
49 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
52 static struct omap_lcd_controller
{
53 enum omapfb_update_mode update_mode
;
56 unsigned long frame_offset
;
61 enum omapfb_color_format color_mode
;
64 dma_addr_t palette_phys
;
68 unsigned int irq_mask
;
69 struct completion last_frame_complete
;
70 struct completion palette_load_complete
;
72 struct omapfb_device
*fbdev
;
74 void (*dma_callback
)(void *data
);
75 void *dma_callback_data
;
80 unsigned long vram_size
;
83 static void inline enable_irqs(int mask
)
85 lcdc
.irq_mask
|= mask
;
88 static void inline disable_irqs(int mask
)
90 lcdc
.irq_mask
&= ~mask
;
93 static void set_load_mode(enum lcdc_load_mode mode
)
97 l
= omap_readl(OMAP_LCDC_CONTROL
);
100 case OMAP_LCDC_LOAD_PALETTE
:
103 case OMAP_LCDC_LOAD_FRAME
:
106 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME
:
111 omap_writel(l
, OMAP_LCDC_CONTROL
);
114 static void enable_controller(void)
118 l
= omap_readl(OMAP_LCDC_CONTROL
);
119 l
|= OMAP_LCDC_CTRL_LCD_EN
;
120 l
&= ~OMAP_LCDC_IRQ_MASK
;
121 l
|= lcdc
.irq_mask
| OMAP_LCDC_IRQ_DONE
; /* enabled IRQs */
122 omap_writel(l
, OMAP_LCDC_CONTROL
);
125 static void disable_controller_async(void)
130 l
= omap_readl(OMAP_LCDC_CONTROL
);
131 mask
= OMAP_LCDC_CTRL_LCD_EN
| OMAP_LCDC_IRQ_MASK
;
133 * Preserve the DONE mask, since we still want to get the
134 * final DONE irq. It will be disabled in the IRQ handler.
136 mask
&= ~OMAP_LCDC_IRQ_DONE
;
138 omap_writel(l
, OMAP_LCDC_CONTROL
);
141 static void disable_controller(void)
143 init_completion(&lcdc
.last_frame_complete
);
144 disable_controller_async();
145 if (!wait_for_completion_timeout(&lcdc
.last_frame_complete
,
146 msecs_to_jiffies(500)))
147 dev_err(lcdc
.fbdev
->dev
, "timeout waiting for FRAME DONE\n");
150 static void reset_controller(u32 status
)
152 static unsigned long reset_count
;
153 static unsigned long last_jiffies
;
155 disable_controller_async();
157 if (reset_count
== 1 || time_after(jiffies
, last_jiffies
+ HZ
)) {
158 dev_err(lcdc
.fbdev
->dev
,
159 "resetting (status %#010x,reset count %lu)\n",
160 status
, reset_count
);
161 last_jiffies
= jiffies
;
163 if (reset_count
< 100) {
167 dev_err(lcdc
.fbdev
->dev
,
168 "too many reset attempts, giving up.\n");
173 * Configure the LCD DMA according to the current mode specified by parameters
174 * in lcdc.fbdev and fbdev->var.
176 static void setup_lcd_dma(void)
178 static const int dma_elem_type
[] = {
180 OMAP_DMA_DATA_TYPE_S8
,
181 OMAP_DMA_DATA_TYPE_S16
,
183 OMAP_DMA_DATA_TYPE_S32
,
185 struct omapfb_plane_struct
*plane
= lcdc
.fbdev
->fb_info
[0]->par
;
186 struct fb_var_screeninfo
*var
= &lcdc
.fbdev
->fb_info
[0]->var
;
188 int esize
, xelem
, yelem
;
190 src
= lcdc
.vram_phys
+ lcdc
.frame_offset
;
192 switch (var
->rotate
) {
194 if (plane
->info
.mirror
|| (src
& 3) ||
195 lcdc
.color_mode
== OMAPFB_COLOR_YUV420
||
200 xelem
= lcdc
.xres
* lcdc
.bpp
/ 8 / esize
;
206 if (cpu_is_omap15xx()) {
210 xelem
= lcdc
.yres
* lcdc
.bpp
/ 16;
218 dev_dbg(lcdc
.fbdev
->dev
,
219 "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
220 src
, esize
, xelem
, yelem
);
222 omap_set_lcd_dma_b1(src
, xelem
, yelem
, dma_elem_type
[esize
]);
223 if (!cpu_is_omap15xx()) {
227 * YUV support is only for external mode when we have the
228 * YUV window embedded in a 16bpp frame buffer.
230 if (lcdc
.color_mode
== OMAPFB_COLOR_YUV420
)
232 /* Set virtual xres elem size */
233 omap_set_lcd_dma_b1_vxres(
234 lcdc
.screen_width
* bpp
/ 8 / esize
);
235 /* Setup transformations */
236 omap_set_lcd_dma_b1_rotation(var
->rotate
);
237 omap_set_lcd_dma_b1_mirror(plane
->info
.mirror
);
239 omap_setup_lcd_dma();
242 static irqreturn_t
lcdc_irq_handler(int irq
, void *dev_id
)
246 status
= omap_readl(OMAP_LCDC_STATUS
);
248 if (status
& (OMAP_LCDC_STAT_FUF
| OMAP_LCDC_STAT_SYNC_LOST
))
249 reset_controller(status
);
251 if (status
& OMAP_LCDC_STAT_DONE
) {
255 * Disable IRQ_DONE. The status bit will be cleared
256 * only when the controller is reenabled and we don't
257 * want to get more interrupts.
259 l
= omap_readl(OMAP_LCDC_CONTROL
);
260 l
&= ~OMAP_LCDC_IRQ_DONE
;
261 omap_writel(l
, OMAP_LCDC_CONTROL
);
262 complete(&lcdc
.last_frame_complete
);
264 if (status
& OMAP_LCDC_STAT_LOADED_PALETTE
) {
265 disable_controller_async();
266 complete(&lcdc
.palette_load_complete
);
271 * Clear these interrupt status bits.
272 * Sync_lost, FUF bits were cleared by disabling the LCD controller
273 * LOADED_PALETTE can be cleared this way only in palette only
274 * load mode. In other load modes it's cleared by disabling the
277 status
&= ~(OMAP_LCDC_STAT_VSYNC
|
278 OMAP_LCDC_STAT_LOADED_PALETTE
|
280 OMAP_LCDC_STAT_LINE_INT
);
281 omap_writel(status
, OMAP_LCDC_STATUS
);
286 * Change to a new video mode. We defer this to a later time to avoid any
287 * flicker and not to mess up the current LCD DMA context. For this we disable
288 * the LCD controller, which will generate a DONE irq after the last frame has
289 * been transferred. Then it'll be safe to reconfigure both the LCD controller
290 * as well as the LCD DMA.
292 static int omap_lcdc_setup_plane(int plane
, int channel_out
,
293 unsigned long offset
, int screen_width
,
294 int pos_x
, int pos_y
, int width
, int height
,
297 struct fb_var_screeninfo
*var
= &lcdc
.fbdev
->fb_info
[0]->var
;
298 struct lcd_panel
*panel
= lcdc
.fbdev
->panel
;
301 if (var
->rotate
== 0) {
302 rot_x
= panel
->x_res
;
303 rot_y
= panel
->y_res
;
305 rot_x
= panel
->y_res
;
306 rot_y
= panel
->x_res
;
308 if (plane
!= 0 || channel_out
!= 0 || pos_x
!= 0 || pos_y
!= 0 ||
309 width
> rot_x
|| height
> rot_y
) {
311 dev_dbg(lcdc
.fbdev
->dev
,
312 "invalid plane params plane %d pos_x %d pos_y %d "
313 "w %d h %d\n", plane
, pos_x
, pos_y
, width
, height
);
318 lcdc
.frame_offset
= offset
;
321 lcdc
.screen_width
= screen_width
;
322 lcdc
.color_mode
= color_mode
;
324 switch (color_mode
) {
325 case OMAPFB_COLOR_CLUT_8BPP
:
327 lcdc
.palette_code
= 0x3000;
328 lcdc
.palette_size
= 512;
330 case OMAPFB_COLOR_RGB565
:
332 lcdc
.palette_code
= 0x4000;
333 lcdc
.palette_size
= 32;
335 case OMAPFB_COLOR_RGB444
:
337 lcdc
.palette_code
= 0x4000;
338 lcdc
.palette_size
= 32;
340 case OMAPFB_COLOR_YUV420
:
346 case OMAPFB_COLOR_YUV422
:
353 dev_dbg(lcdc
.fbdev
->dev
, "invalid color mode %d\n", color_mode
);
363 if (lcdc
.update_mode
== OMAPFB_AUTO_UPDATE
) {
364 disable_controller();
373 static int omap_lcdc_enable_plane(int plane
, int enable
)
375 dev_dbg(lcdc
.fbdev
->dev
,
376 "plane %d enable %d update_mode %d ext_mode %d\n",
377 plane
, enable
, lcdc
.update_mode
, lcdc
.ext_mode
);
378 if (plane
!= OMAPFB_PLANE_GFX
)
385 * Configure the LCD DMA for a palette load operation and do the palette
386 * downloading synchronously. We don't use the frame+palette load mode of
387 * the controller, since the palette can always be downloaded separately.
389 static void load_palette(void)
393 palette
= (u16
*)lcdc
.palette_virt
;
395 *(u16
*)palette
&= 0x0fff;
396 *(u16
*)palette
|= lcdc
.palette_code
;
398 omap_set_lcd_dma_b1(lcdc
.palette_phys
,
399 lcdc
.palette_size
/ 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32
);
401 omap_set_lcd_dma_single_transfer(1);
402 omap_setup_lcd_dma();
404 init_completion(&lcdc
.palette_load_complete
);
405 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE
);
406 set_load_mode(OMAP_LCDC_LOAD_PALETTE
);
408 if (!wait_for_completion_timeout(&lcdc
.palette_load_complete
,
409 msecs_to_jiffies(500)))
410 dev_err(lcdc
.fbdev
->dev
, "timeout waiting for FRAME DONE\n");
411 /* The controller gets disabled in the irq handler */
412 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE
);
415 omap_set_lcd_dma_single_transfer(lcdc
.ext_mode
);
418 /* Used only in internal controller mode */
419 static int omap_lcdc_setcolreg(u_int regno
, u16 red
, u16 green
, u16 blue
,
420 u16 transp
, int update_hw_pal
)
424 if (lcdc
.color_mode
!= OMAPFB_COLOR_CLUT_8BPP
|| regno
> 255)
427 palette
= (u16
*)lcdc
.palette_virt
;
429 palette
[regno
] &= ~0x0fff;
430 palette
[regno
] |= ((red
>> 12) << 8) | ((green
>> 12) << 4 ) |
434 disable_controller();
438 set_load_mode(OMAP_LCDC_LOAD_FRAME
);
445 static void calc_ck_div(int is_tft
, int pck
, int *pck_div
)
450 lck
= clk_get_rate(lcdc
.lcd_ck
);
451 *pck_div
= (lck
+ pck
- 1) / pck
;
453 *pck_div
= max(2, *pck_div
);
455 *pck_div
= max(3, *pck_div
);
456 if (*pck_div
> 255) {
458 dev_warn(lcdc
.fbdev
->dev
, "pixclock %d kHz too low.\n",
463 static void inline setup_regs(void)
466 struct lcd_panel
*panel
= lcdc
.fbdev
->panel
;
467 int is_tft
= panel
->config
& OMAP_LCDC_PANEL_TFT
;
471 l
= omap_readl(OMAP_LCDC_CONTROL
);
472 l
&= ~OMAP_LCDC_CTRL_LCD_TFT
;
473 l
|= is_tft
? OMAP_LCDC_CTRL_LCD_TFT
: 0;
474 #ifdef CONFIG_MACH_OMAP_PALMTE
475 /* PalmTE uses alternate TFT setting in 8BPP mode */
476 l
|= (is_tft
&& panel
->bpp
== 8) ? 0x810000 : 0;
479 omap_writel(l
, OMAP_LCDC_CONTROL
);
481 l
= omap_readl(OMAP_LCDC_TIMING2
);
482 l
&= ~(((1 << 6) - 1) << 20);
483 l
|= (panel
->config
& OMAP_LCDC_SIGNAL_MASK
) << 20;
484 omap_writel(l
, OMAP_LCDC_TIMING2
);
486 l
= panel
->x_res
- 1;
487 l
|= (panel
->hsw
- 1) << 10;
488 l
|= (panel
->hfp
- 1) << 16;
489 l
|= (panel
->hbp
- 1) << 24;
490 omap_writel(l
, OMAP_LCDC_TIMING0
);
492 l
= panel
->y_res
- 1;
493 l
|= (panel
->vsw
- 1) << 10;
494 l
|= panel
->vfp
<< 16;
495 l
|= panel
->vbp
<< 24;
496 omap_writel(l
, OMAP_LCDC_TIMING1
);
498 l
= omap_readl(OMAP_LCDC_TIMING2
);
501 lck
= clk_get_rate(lcdc
.lcd_ck
);
504 calc_ck_div(is_tft
, panel
->pixel_clock
* 1000, &pcd
);
506 dev_warn(lcdc
.fbdev
->dev
,
507 "Pixel clock divider value is obsolete.\n"
508 "Try to set pixel_clock to %lu and pcd to 0 "
509 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
510 lck
/ panel
->pcd
/ 1000, panel
->name
);
515 l
|= panel
->acb
<< 8;
516 omap_writel(l
, OMAP_LCDC_TIMING2
);
518 /* update panel info with the exact clock */
519 panel
->pixel_clock
= lck
/ pcd
/ 1000;
523 * Configure the LCD controller, download the color palette and start a looped
524 * DMA transfer of the frame image data. Called only in internal
527 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode
)
531 if (mode
!= lcdc
.update_mode
) {
533 case OMAPFB_AUTO_UPDATE
:
537 /* Setup and start LCD DMA */
540 set_load_mode(OMAP_LCDC_LOAD_FRAME
);
541 enable_irqs(OMAP_LCDC_IRQ_DONE
);
542 /* This will start the actual DMA transfer */
544 lcdc
.update_mode
= mode
;
546 case OMAPFB_UPDATE_DISABLED
:
547 disable_controller();
549 lcdc
.update_mode
= mode
;
559 static enum omapfb_update_mode
omap_lcdc_get_update_mode(void)
561 return lcdc
.update_mode
;
564 /* PM code called only in internal controller mode */
565 static void omap_lcdc_suspend(void)
567 omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED
);
570 static void omap_lcdc_resume(void)
572 omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE
);
575 static void omap_lcdc_get_caps(int plane
, struct omapfb_caps
*caps
)
580 int omap_lcdc_set_dma_callback(void (*callback
)(void *data
), void *data
)
582 BUG_ON(callback
== NULL
);
584 if (lcdc
.dma_callback
)
587 lcdc
.dma_callback
= callback
;
588 lcdc
.dma_callback_data
= data
;
592 EXPORT_SYMBOL(omap_lcdc_set_dma_callback
);
594 void omap_lcdc_free_dma_callback(void)
596 lcdc
.dma_callback
= NULL
;
598 EXPORT_SYMBOL(omap_lcdc_free_dma_callback
);
600 static void lcdc_dma_handler(u16 status
, void *data
)
602 if (lcdc
.dma_callback
)
603 lcdc
.dma_callback(lcdc
.dma_callback_data
);
606 static int mmap_kern(void)
608 struct vm_struct
*kvma
;
609 struct vm_area_struct vma
;
613 kvma
= get_vm_area(lcdc
.vram_size
, VM_IOREMAP
);
615 dev_err(lcdc
.fbdev
->dev
, "can't get kernel vm area\n");
618 vma
.vm_mm
= &init_mm
;
620 vaddr
= (unsigned long)kvma
->addr
;
621 vma
.vm_start
= vaddr
;
622 vma
.vm_end
= vaddr
+ lcdc
.vram_size
;
624 pgprot
= pgprot_writecombine(pgprot_kernel
);
625 if (io_remap_pfn_range(&vma
, vaddr
,
626 lcdc
.vram_phys
>> PAGE_SHIFT
,
627 lcdc
.vram_size
, pgprot
) < 0) {
628 dev_err(lcdc
.fbdev
->dev
, "kernel mmap for FB memory failed\n");
632 lcdc
.vram_virt
= (void *)vaddr
;
637 static void unmap_kern(void)
639 vunmap(lcdc
.vram_virt
);
642 static int alloc_palette_ram(void)
644 lcdc
.palette_virt
= dma_alloc_writecombine(lcdc
.fbdev
->dev
,
645 MAX_PALETTE_SIZE
, &lcdc
.palette_phys
, GFP_KERNEL
);
646 if (lcdc
.palette_virt
== NULL
) {
647 dev_err(lcdc
.fbdev
->dev
, "failed to alloc palette memory\n");
650 memset(lcdc
.palette_virt
, 0, MAX_PALETTE_SIZE
);
655 static void free_palette_ram(void)
657 dma_free_writecombine(lcdc
.fbdev
->dev
, MAX_PALETTE_SIZE
,
658 lcdc
.palette_virt
, lcdc
.palette_phys
);
661 static int alloc_fbmem(struct omapfb_mem_region
*region
)
665 struct lcd_panel
*panel
= lcdc
.fbdev
->panel
;
670 frame_size
= PAGE_ALIGN(panel
->x_res
* bpp
/ 8 * panel
->y_res
);
671 if (region
->size
> frame_size
)
672 frame_size
= region
->size
;
673 lcdc
.vram_size
= frame_size
;
674 lcdc
.vram_virt
= dma_alloc_writecombine(lcdc
.fbdev
->dev
,
675 lcdc
.vram_size
, &lcdc
.vram_phys
, GFP_KERNEL
);
676 if (lcdc
.vram_virt
== NULL
) {
677 dev_err(lcdc
.fbdev
->dev
, "unable to allocate FB DMA memory\n");
680 region
->size
= frame_size
;
681 region
->paddr
= lcdc
.vram_phys
;
682 region
->vaddr
= lcdc
.vram_virt
;
685 memset(lcdc
.vram_virt
, 0, lcdc
.vram_size
);
690 static void free_fbmem(void)
692 dma_free_writecombine(lcdc
.fbdev
->dev
, lcdc
.vram_size
,
693 lcdc
.vram_virt
, lcdc
.vram_phys
);
696 static int setup_fbmem(struct omapfb_mem_desc
*req_md
)
700 if (!req_md
->region_cnt
) {
701 dev_err(lcdc
.fbdev
->dev
, "no memory regions defined\n");
705 if (req_md
->region_cnt
> 1) {
706 dev_err(lcdc
.fbdev
->dev
, "only one plane is supported\n");
707 req_md
->region_cnt
= 1;
710 if (req_md
->region
[0].paddr
== 0) {
711 lcdc
.fbmem_allocated
= 1;
712 if ((r
= alloc_fbmem(&req_md
->region
[0])) < 0)
717 lcdc
.vram_phys
= req_md
->region
[0].paddr
;
718 lcdc
.vram_size
= req_md
->region
[0].size
;
720 if ((r
= mmap_kern()) < 0)
723 dev_dbg(lcdc
.fbdev
->dev
, "vram at %08x size %08lx mapped to 0x%p\n",
724 lcdc
.vram_phys
, lcdc
.vram_size
, lcdc
.vram_virt
);
729 static void cleanup_fbmem(void)
731 if (lcdc
.fbmem_allocated
)
737 static int omap_lcdc_init(struct omapfb_device
*fbdev
, int ext_mode
,
738 struct omapfb_mem_desc
*req_vram
)
748 lcdc
.ext_mode
= ext_mode
;
751 omap_writel(l
, OMAP_LCDC_CONTROL
);
753 lcdc
.lcd_ck
= clk_get(fbdev
->dev
, "lcd_ck");
754 if (IS_ERR(lcdc
.lcd_ck
)) {
755 dev_err(fbdev
->dev
, "unable to access LCD clock\n");
756 r
= PTR_ERR(lcdc
.lcd_ck
);
760 tc_ck
= clk_get(fbdev
->dev
, "tc_ck");
762 dev_err(fbdev
->dev
, "unable to access TC clock\n");
767 rate
= clk_get_rate(tc_ck
);
770 if (machine_is_ams_delta())
772 if (machine_is_omap_h3())
774 r
= clk_set_rate(lcdc
.lcd_ck
, rate
);
776 dev_err(fbdev
->dev
, "failed to adjust LCD rate\n");
779 clk_enable(lcdc
.lcd_ck
);
781 r
= request_irq(OMAP_LCDC_IRQ
, lcdc_irq_handler
, 0, MODULE_NAME
, fbdev
);
783 dev_err(fbdev
->dev
, "unable to get IRQ\n");
787 r
= omap_request_lcd_dma(lcdc_dma_handler
, NULL
);
789 dev_err(fbdev
->dev
, "unable to get LCD DMA\n");
793 omap_set_lcd_dma_single_transfer(ext_mode
);
794 omap_set_lcd_dma_ext_controller(ext_mode
);
797 if ((r
= alloc_palette_ram()) < 0)
800 if ((r
= setup_fbmem(req_vram
)) < 0)
803 pr_info("omapfb: LCDC initialized\n");
812 free_irq(OMAP_LCDC_IRQ
, lcdc
.fbdev
);
814 clk_disable(lcdc
.lcd_ck
);
816 clk_put(lcdc
.lcd_ck
);
821 static void omap_lcdc_cleanup(void)
827 free_irq(OMAP_LCDC_IRQ
, lcdc
.fbdev
);
828 clk_disable(lcdc
.lcd_ck
);
829 clk_put(lcdc
.lcd_ck
);
832 const struct lcd_ctrl omap1_int_ctrl
= {
834 .init
= omap_lcdc_init
,
835 .cleanup
= omap_lcdc_cleanup
,
836 .get_caps
= omap_lcdc_get_caps
,
837 .set_update_mode
= omap_lcdc_set_update_mode
,
838 .get_update_mode
= omap_lcdc_get_update_mode
,
839 .update_window
= NULL
,
840 .suspend
= omap_lcdc_suspend
,
841 .resume
= omap_lcdc_resume
,
842 .setup_plane
= omap_lcdc_setup_plane
,
843 .enable_plane
= omap_lcdc_enable_plane
,
844 .setcolreg
= omap_lcdc_setcolreg
,