2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2009 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
7 #include <linux/delay.h>
13 #define MASK(n) DMA_BIT_MASK(n)
14 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
15 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
16 #define MS_WIN(addr) (addr & 0x0ffc0000)
17 #define QLA82XX_PCI_MN_2M (0)
18 #define QLA82XX_PCI_MS_2M (0x80000)
19 #define QLA82XX_PCI_OCM0_2M (0xc0000)
20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
23 /* CRB window related */
24 #define CRB_BLK(off) ((off >> 20) & 0x3f)
25 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
26 #define CRB_WINDOW_2M (0x130060)
27 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
29 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
30 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
31 #define CRB_INDIRECT_2M (0x1e0000UL)
33 static inline void __iomem
*
34 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host
*ha
, unsigned long off
)
36 if ((off
< ha
->first_page_group_end
) &&
37 (off
>= ha
->first_page_group_start
))
38 return (void __iomem
*)(ha
->nx_pcibase
+ off
);
43 #define MAX_CRB_XFORM 60
44 static unsigned long crb_addr_xform
[MAX_CRB_XFORM
];
45 static int qla4_8xxx_crb_table_initialized
;
47 #define qla4_8xxx_crb_addr_transform(name) \
48 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
49 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
51 qla4_8xxx_crb_addr_transform_setup(void)
53 qla4_8xxx_crb_addr_transform(XDMA
);
54 qla4_8xxx_crb_addr_transform(TIMR
);
55 qla4_8xxx_crb_addr_transform(SRE
);
56 qla4_8xxx_crb_addr_transform(SQN3
);
57 qla4_8xxx_crb_addr_transform(SQN2
);
58 qla4_8xxx_crb_addr_transform(SQN1
);
59 qla4_8xxx_crb_addr_transform(SQN0
);
60 qla4_8xxx_crb_addr_transform(SQS3
);
61 qla4_8xxx_crb_addr_transform(SQS2
);
62 qla4_8xxx_crb_addr_transform(SQS1
);
63 qla4_8xxx_crb_addr_transform(SQS0
);
64 qla4_8xxx_crb_addr_transform(RPMX7
);
65 qla4_8xxx_crb_addr_transform(RPMX6
);
66 qla4_8xxx_crb_addr_transform(RPMX5
);
67 qla4_8xxx_crb_addr_transform(RPMX4
);
68 qla4_8xxx_crb_addr_transform(RPMX3
);
69 qla4_8xxx_crb_addr_transform(RPMX2
);
70 qla4_8xxx_crb_addr_transform(RPMX1
);
71 qla4_8xxx_crb_addr_transform(RPMX0
);
72 qla4_8xxx_crb_addr_transform(ROMUSB
);
73 qla4_8xxx_crb_addr_transform(SN
);
74 qla4_8xxx_crb_addr_transform(QMN
);
75 qla4_8xxx_crb_addr_transform(QMS
);
76 qla4_8xxx_crb_addr_transform(PGNI
);
77 qla4_8xxx_crb_addr_transform(PGND
);
78 qla4_8xxx_crb_addr_transform(PGN3
);
79 qla4_8xxx_crb_addr_transform(PGN2
);
80 qla4_8xxx_crb_addr_transform(PGN1
);
81 qla4_8xxx_crb_addr_transform(PGN0
);
82 qla4_8xxx_crb_addr_transform(PGSI
);
83 qla4_8xxx_crb_addr_transform(PGSD
);
84 qla4_8xxx_crb_addr_transform(PGS3
);
85 qla4_8xxx_crb_addr_transform(PGS2
);
86 qla4_8xxx_crb_addr_transform(PGS1
);
87 qla4_8xxx_crb_addr_transform(PGS0
);
88 qla4_8xxx_crb_addr_transform(PS
);
89 qla4_8xxx_crb_addr_transform(PH
);
90 qla4_8xxx_crb_addr_transform(NIU
);
91 qla4_8xxx_crb_addr_transform(I2Q
);
92 qla4_8xxx_crb_addr_transform(EG
);
93 qla4_8xxx_crb_addr_transform(MN
);
94 qla4_8xxx_crb_addr_transform(MS
);
95 qla4_8xxx_crb_addr_transform(CAS2
);
96 qla4_8xxx_crb_addr_transform(CAS1
);
97 qla4_8xxx_crb_addr_transform(CAS0
);
98 qla4_8xxx_crb_addr_transform(CAM
);
99 qla4_8xxx_crb_addr_transform(C2C1
);
100 qla4_8xxx_crb_addr_transform(C2C0
);
101 qla4_8xxx_crb_addr_transform(SMB
);
102 qla4_8xxx_crb_addr_transform(OCM0
);
103 qla4_8xxx_crb_addr_transform(I2C0
);
105 qla4_8xxx_crb_table_initialized
= 1;
108 static struct crb_128M_2M_block_map crb_128M_2M_map
[64] = {
109 {{{0, 0, 0, 0} } }, /* 0: PCI */
110 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
111 {1, 0x0110000, 0x0120000, 0x130000},
112 {1, 0x0120000, 0x0122000, 0x124000},
113 {1, 0x0130000, 0x0132000, 0x126000},
114 {1, 0x0140000, 0x0142000, 0x128000},
115 {1, 0x0150000, 0x0152000, 0x12a000},
116 {1, 0x0160000, 0x0170000, 0x110000},
117 {1, 0x0170000, 0x0172000, 0x12e000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x01e0000, 0x01e0800, 0x122000},
125 {0, 0x0000000, 0x0000000, 0x000000} } },
126 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
127 {{{0, 0, 0, 0} } }, /* 3: */
128 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
129 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
130 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
131 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
132 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x08f0000, 0x08f2000, 0x172000} } },
148 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x09f0000, 0x09f2000, 0x176000} } },
164 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
180 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
196 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
197 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
198 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
199 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
200 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
201 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
202 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
203 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
204 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
205 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
206 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
207 {{{0, 0, 0, 0} } }, /* 23: */
208 {{{0, 0, 0, 0} } }, /* 24: */
209 {{{0, 0, 0, 0} } }, /* 25: */
210 {{{0, 0, 0, 0} } }, /* 26: */
211 {{{0, 0, 0, 0} } }, /* 27: */
212 {{{0, 0, 0, 0} } }, /* 28: */
213 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
214 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
215 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
216 {{{0} } }, /* 32: PCI */
217 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
218 {1, 0x2110000, 0x2120000, 0x130000},
219 {1, 0x2120000, 0x2122000, 0x124000},
220 {1, 0x2130000, 0x2132000, 0x126000},
221 {1, 0x2140000, 0x2142000, 0x128000},
222 {1, 0x2150000, 0x2152000, 0x12a000},
223 {1, 0x2160000, 0x2170000, 0x110000},
224 {1, 0x2170000, 0x2172000, 0x12e000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000} } },
233 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
239 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
240 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
241 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
242 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
243 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
244 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
245 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
246 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
247 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
248 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
249 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
250 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
252 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
253 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
254 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
255 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
256 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
257 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
258 {{{0} } }, /* 59: I2C0 */
259 {{{0} } }, /* 60: I2C1 */
260 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
261 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
262 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
266 * top 12 bits of crb internal address (hub, agent)
268 static unsigned qla4_8xxx_crb_hub_agt
[64] = {
270 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_MN
,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_MS
,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE
,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU
,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN
,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0
,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1
,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2
,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3
,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4
,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0
,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1
,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2
,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3
,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND
,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI
,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0
,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1
,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2
,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3
,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI
,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_SN
,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_EG
,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM
,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1
,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2
,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3
,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4
,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5
,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6
,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7
,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0
,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8
,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9
,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0
,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB
,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0
,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1
,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC
,
336 static char *qdev_state
[] = {
348 * In: 'off' is offset from CRB space in 128M pci map
349 * Out: 'off' is 2M pci map addr
350 * side effect: lock crb window
353 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host
*ha
, ulong
*off
)
357 ha
->crb_win
= CRB_HI(*off
);
359 (void __iomem
*)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
361 /* Read back value to make sure write has gone through before trying
363 win_read
= readl((void __iomem
*)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
364 if (win_read
!= ha
->crb_win
) {
365 DEBUG2(ql4_printk(KERN_INFO
, ha
,
366 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
367 " off=0x%lx\n", __func__
, ha
->crb_win
, win_read
, *off
));
369 *off
= (*off
& MASK(16)) + CRB_INDIRECT_2M
+ ha
->nx_pcibase
;
373 qla4_8xxx_wr_32(struct scsi_qla_host
*ha
, ulong off
, u32 data
)
375 unsigned long flags
= 0;
378 rv
= qla4_8xxx_pci_get_crb_addr_2M(ha
, &off
);
383 write_lock_irqsave(&ha
->hw_lock
, flags
);
384 qla4_8xxx_crb_win_lock(ha
);
385 qla4_8xxx_pci_set_crbwindow_2M(ha
, &off
);
388 writel(data
, (void __iomem
*)off
);
391 qla4_8xxx_crb_win_unlock(ha
);
392 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
397 qla4_8xxx_rd_32(struct scsi_qla_host
*ha
, ulong off
)
399 unsigned long flags
= 0;
403 rv
= qla4_8xxx_pci_get_crb_addr_2M(ha
, &off
);
408 write_lock_irqsave(&ha
->hw_lock
, flags
);
409 qla4_8xxx_crb_win_lock(ha
);
410 qla4_8xxx_pci_set_crbwindow_2M(ha
, &off
);
412 data
= readl((void __iomem
*)off
);
415 qla4_8xxx_crb_win_unlock(ha
);
416 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
421 #define CRB_WIN_LOCK_TIMEOUT 100000000
423 int qla4_8xxx_crb_win_lock(struct scsi_qla_host
*ha
)
426 int done
= 0, timeout
= 0;
429 /* acquire semaphore3 from PCI HW block */
430 done
= qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK
));
433 if (timeout
>= CRB_WIN_LOCK_TIMEOUT
)
442 for (i
= 0; i
< 20; i
++)
443 cpu_relax(); /*This a nop instr on i386*/
446 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_WIN_LOCK_ID
, ha
->func_num
);
450 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host
*ha
)
452 qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
455 #define IDC_LOCK_TIMEOUT 100000000
458 * qla4_8xxx_idc_lock - hw_lock
459 * @ha: pointer to adapter structure
461 * General purpose lock used to synchronize access to
462 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
464 int qla4_8xxx_idc_lock(struct scsi_qla_host
*ha
)
467 int done
= 0, timeout
= 0;
470 /* acquire semaphore5 from PCI HW block */
471 done
= qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK
));
474 if (timeout
>= IDC_LOCK_TIMEOUT
)
483 for (i
= 0; i
< 20; i
++)
484 cpu_relax(); /*This a nop instr on i386*/
490 void qla4_8xxx_idc_unlock(struct scsi_qla_host
*ha
)
492 qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK
));
496 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host
*ha
, ulong
*off
)
498 struct crb_128M_2M_sub_block_map
*m
;
500 if (*off
>= QLA82XX_CRB_MAX
)
503 if (*off
>= QLA82XX_PCI_CAMQM
&& (*off
< QLA82XX_PCI_CAMQM_2M_END
)) {
504 *off
= (*off
- QLA82XX_PCI_CAMQM
) +
505 QLA82XX_PCI_CAMQM_2M_BASE
+ ha
->nx_pcibase
;
509 if (*off
< QLA82XX_PCI_CRBSPACE
)
512 *off
-= QLA82XX_PCI_CRBSPACE
;
517 m
= &crb_128M_2M_map
[CRB_BLK(*off
)].sub_block
[CRB_SUBBLK(*off
)];
519 if (m
->valid
&& (m
->start_128M
<= *off
) && (m
->end_128M
> *off
)) {
520 *off
= *off
+ m
->start_2M
- m
->start_128M
+ ha
->nx_pcibase
;
525 * Not in direct map, use crb window
530 /* PCI Windowing for DDR regions. */
531 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
532 (((addr) <= (high)) && ((addr) >= (low)))
535 * check memory access boundary.
536 * used by test agent. support ddr access only for now
539 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host
*ha
,
540 unsigned long long addr
, int size
)
542 if (!QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
543 QLA82XX_ADDR_DDR_NET_MAX
) ||
544 !QLA82XX_ADDR_IN_RANGE(addr
+ size
- 1,
545 QLA82XX_ADDR_DDR_NET
, QLA82XX_ADDR_DDR_NET_MAX
) ||
546 ((size
!= 1) && (size
!= 2) && (size
!= 4) && (size
!= 8))) {
552 static int qla4_8xxx_pci_set_window_warning_count
;
555 qla4_8xxx_pci_set_window(struct scsi_qla_host
*ha
, unsigned long long addr
)
560 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
561 QLA82XX_ADDR_DDR_NET_MAX
)) {
562 /* DDR network side */
563 window
= MN_WIN(addr
);
564 ha
->ddr_mn_window
= window
;
565 qla4_8xxx_wr_32(ha
, ha
->mn_win_crb
|
566 QLA82XX_PCI_CRBSPACE
, window
);
567 win_read
= qla4_8xxx_rd_32(ha
, ha
->mn_win_crb
|
568 QLA82XX_PCI_CRBSPACE
);
569 if ((win_read
<< 17) != window
) {
570 ql4_printk(KERN_WARNING
, ha
,
571 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
572 __func__
, window
, win_read
);
574 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_DDR_NET
;
575 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
576 QLA82XX_ADDR_OCM0_MAX
)) {
578 /* if bits 19:18&17:11 are on */
579 if ((addr
& 0x00ff800) == 0xff800) {
580 printk("%s: QM access not handled.\n", __func__
);
584 window
= OCM_WIN(addr
);
585 ha
->ddr_mn_window
= window
;
586 qla4_8xxx_wr_32(ha
, ha
->mn_win_crb
|
587 QLA82XX_PCI_CRBSPACE
, window
);
588 win_read
= qla4_8xxx_rd_32(ha
, ha
->mn_win_crb
|
589 QLA82XX_PCI_CRBSPACE
);
590 temp1
= ((window
& 0x1FF) << 7) |
591 ((window
& 0x0FFFE0000) >> 17);
592 if (win_read
!= temp1
) {
593 printk("%s: Written OCMwin (0x%x) != Read"
594 " OCMwin (0x%x)\n", __func__
, temp1
, win_read
);
596 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_OCM0_2M
;
598 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
,
599 QLA82XX_P3_ADDR_QDR_NET_MAX
)) {
600 /* QDR network side */
601 window
= MS_WIN(addr
);
602 ha
->qdr_sn_window
= window
;
603 qla4_8xxx_wr_32(ha
, ha
->ms_win_crb
|
604 QLA82XX_PCI_CRBSPACE
, window
);
605 win_read
= qla4_8xxx_rd_32(ha
,
606 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
);
607 if (win_read
!= window
) {
608 printk("%s: Written MSwin (0x%x) != Read "
609 "MSwin (0x%x)\n", __func__
, window
, win_read
);
611 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_QDR_NET
;
615 * peg gdb frequently accesses memory that doesn't exist,
616 * this limits the chit chat so debugging isn't slowed down.
618 if ((qla4_8xxx_pci_set_window_warning_count
++ < 8) ||
619 (qla4_8xxx_pci_set_window_warning_count
%64 == 0)) {
620 printk("%s: Warning:%s Unknown address range!\n",
621 __func__
, DRIVER_NAME
);
628 /* check if address is in the same windows as the previous access */
629 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host
*ha
,
630 unsigned long long addr
)
633 unsigned long long qdr_max
;
635 qdr_max
= QLA82XX_P3_ADDR_QDR_NET_MAX
;
637 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
638 QLA82XX_ADDR_DDR_NET_MAX
)) {
639 /* DDR network side */
640 BUG(); /* MN access can not come here */
641 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
642 QLA82XX_ADDR_OCM0_MAX
)) {
644 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM1
,
645 QLA82XX_ADDR_OCM1_MAX
)) {
647 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
,
649 /* QDR network side */
650 window
= ((addr
- QLA82XX_ADDR_QDR_NET
) >> 22) & 0x3f;
651 if (ha
->qdr_sn_window
== window
)
658 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host
*ha
,
659 u64 off
, void *data
, int size
)
665 void __iomem
*mem_ptr
= NULL
;
666 unsigned long mem_base
;
667 unsigned long mem_page
;
669 write_lock_irqsave(&ha
->hw_lock
, flags
);
672 * If attempting to access unknown address or straddle hw windows,
675 start
= qla4_8xxx_pci_set_window(ha
, off
);
676 if ((start
== -1UL) ||
677 (qla4_8xxx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
678 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
679 printk(KERN_ERR
"%s out of bound pci memory access. "
680 "offset is 0x%llx\n", DRIVER_NAME
, off
);
684 addr
= qla4_8xxx_pci_base_offsetfset(ha
, start
);
686 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
687 mem_base
= pci_resource_start(ha
->pdev
, 0);
688 mem_page
= start
& PAGE_MASK
;
689 /* Map two pages whenever user tries to access addresses in two
692 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
693 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
* 2);
695 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
697 if (mem_ptr
== NULL
) {
702 addr
+= start
& (PAGE_SIZE
- 1);
703 write_lock_irqsave(&ha
->hw_lock
, flags
);
708 *(u8
*)data
= readb(addr
);
711 *(u16
*)data
= readw(addr
);
714 *(u32
*)data
= readl(addr
);
717 *(u64
*)data
= readq(addr
);
723 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
731 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host
*ha
, u64 off
,
732 void *data
, int size
)
738 void __iomem
*mem_ptr
= NULL
;
739 unsigned long mem_base
;
740 unsigned long mem_page
;
742 write_lock_irqsave(&ha
->hw_lock
, flags
);
745 * If attempting to access unknown address or straddle hw windows,
748 start
= qla4_8xxx_pci_set_window(ha
, off
);
749 if ((start
== -1UL) ||
750 (qla4_8xxx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
751 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
752 printk(KERN_ERR
"%s out of bound pci memory access. "
753 "offset is 0x%llx\n", DRIVER_NAME
, off
);
757 addr
= qla4_8xxx_pci_base_offsetfset(ha
, start
);
759 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
760 mem_base
= pci_resource_start(ha
->pdev
, 0);
761 mem_page
= start
& PAGE_MASK
;
762 /* Map two pages whenever user tries to access addresses in two
765 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
766 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
*2);
768 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
773 addr
+= start
& (PAGE_SIZE
- 1);
774 write_lock_irqsave(&ha
->hw_lock
, flags
);
779 writeb(*(u8
*)data
, addr
);
782 writew(*(u16
*)data
, addr
);
785 writel(*(u32
*)data
, addr
);
788 writeq(*(u64
*)data
, addr
);
794 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
800 #define MTU_FUDGE_FACTOR 100
803 qla4_8xxx_decode_crb_addr(unsigned long addr
)
806 unsigned long base_addr
, offset
, pci_base
;
808 if (!qla4_8xxx_crb_table_initialized
)
809 qla4_8xxx_crb_addr_transform_setup();
811 pci_base
= ADDR_ERROR
;
812 base_addr
= addr
& 0xfff00000;
813 offset
= addr
& 0x000fffff;
815 for (i
= 0; i
< MAX_CRB_XFORM
; i
++) {
816 if (crb_addr_xform
[i
] == base_addr
) {
821 if (pci_base
== ADDR_ERROR
)
824 return pci_base
+ offset
;
827 static long rom_max_timeout
= 100;
828 static long qla4_8xxx_rom_lock_timeout
= 100;
831 qla4_8xxx_rom_lock(struct scsi_qla_host
*ha
)
834 int done
= 0, timeout
= 0;
837 /* acquire semaphore2 from PCI HW block */
839 done
= qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK
));
842 if (timeout
>= qla4_8xxx_rom_lock_timeout
)
851 for (i
= 0; i
< 20; i
++)
852 cpu_relax(); /*This a nop instr on i386*/
855 qla4_8xxx_wr_32(ha
, QLA82XX_ROM_LOCK_ID
, ROM_LOCK_DRIVER
);
860 qla4_8xxx_rom_unlock(struct scsi_qla_host
*ha
)
862 qla4_8xxx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
866 qla4_8xxx_wait_rom_done(struct scsi_qla_host
*ha
)
872 done
= qla4_8xxx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
875 if (timeout
>= rom_max_timeout
) {
876 printk("%s: Timeout reached waiting for rom done",
885 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host
*ha
, int addr
, int *valp
)
887 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
888 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
889 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
890 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0xb);
891 if (qla4_8xxx_wait_rom_done(ha
)) {
892 printk("%s: Error waiting for rom done\n", DRIVER_NAME
);
895 /* reset abyte_cnt and dummy_byte_cnt */
896 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
898 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
900 *valp
= qla4_8xxx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
905 qla4_8xxx_rom_fast_read(struct scsi_qla_host
*ha
, int addr
, int *valp
)
909 while ((qla4_8xxx_rom_lock(ha
) != 0) && (loops
< 50000)) {
913 if (loops
>= 50000) {
914 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME
);
917 ret
= qla4_8xxx_do_rom_fast_read(ha
, addr
, valp
);
918 qla4_8xxx_rom_unlock(ha
);
923 * This routine does CRB initialize sequence
924 * to put the ISP into operational state
927 qla4_8xxx_pinit_from_rom(struct scsi_qla_host
*ha
, int verbose
)
931 struct crb_addr_pair
*buf
;
935 struct crb_addr_pair
{
940 /* Halt all the indiviual PEGs and other blocks of the ISP */
941 qla4_8xxx_rom_lock(ha
);
942 if (test_bit(DPC_RESET_HA
, &ha
->dpc_flags
))
943 /* don't reset CAM block on reset */
944 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xfeffffff);
946 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xffffffff);
948 qla4_8xxx_rom_unlock(ha
);
950 /* Read the signature value from the flash.
951 * Offset 0: Contain signature (0xcafecafe)
952 * Offset 4: Offset and number of addr/value pairs
953 * that present in CRB initialize sequence
955 if (qla4_8xxx_rom_fast_read(ha
, 0, &n
) != 0 || n
!= 0xcafecafeUL
||
956 qla4_8xxx_rom_fast_read(ha
, 4, &n
) != 0) {
957 ql4_printk(KERN_WARNING
, ha
,
958 "[ERROR] Reading crb_init area: n: %08x\n", n
);
962 /* Offset in flash = lower 16 bits
963 * Number of enteries = upper 16 bits
965 offset
= n
& 0xffffU
;
966 n
= (n
>> 16) & 0xffffU
;
968 /* number of addr/value pair should not exceed 1024 enteries */
970 ql4_printk(KERN_WARNING
, ha
,
971 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
972 DRIVER_NAME
, __func__
, n
);
976 ql4_printk(KERN_INFO
, ha
,
977 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME
, n
);
979 buf
= kmalloc(n
* sizeof(struct crb_addr_pair
), GFP_KERNEL
);
981 ql4_printk(KERN_WARNING
, ha
,
982 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME
);
986 for (i
= 0; i
< n
; i
++) {
987 if (qla4_8xxx_rom_fast_read(ha
, 8*i
+ 4*offset
, &val
) != 0 ||
988 qla4_8xxx_rom_fast_read(ha
, 8*i
+ 4*offset
+ 4, &addr
) !=
998 for (i
= 0; i
< n
; i
++) {
999 /* Translate internal CRB initialization
1000 * address to PCI bus address
1002 off
= qla4_8xxx_decode_crb_addr((unsigned long)buf
[i
].addr
) +
1003 QLA82XX_PCI_CRBSPACE
;
1004 /* Not all CRB addr/value pair to be written,
1005 * some of them are skipped
1008 /* skip if LS bit is set*/
1010 DEBUG2(ql4_printk(KERN_WARNING
, ha
,
1011 "Skip CRB init replay for offset = 0x%lx\n", off
));
1015 /* skipping cold reboot MAGIC */
1016 if (off
== QLA82XX_CAM_RAM(0x1fc))
1019 /* do not reset PCI */
1020 if (off
== (ROMUSB_GLB
+ 0xbc))
1023 /* skip core clock, so that firmware can increase the clock */
1024 if (off
== (ROMUSB_GLB
+ 0xc8))
1027 /* skip the function enable register */
1028 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION
))
1031 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2
))
1034 if ((off
& 0x0ff00000) == QLA82XX_CRB_SMB
)
1037 if ((off
& 0x0ff00000) == QLA82XX_CRB_DDR_NET
)
1040 if (off
== ADDR_ERROR
) {
1041 ql4_printk(KERN_WARNING
, ha
,
1042 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1043 DRIVER_NAME
, buf
[i
].addr
);
1047 qla4_8xxx_wr_32(ha
, off
, buf
[i
].data
);
1049 /* ISP requires much bigger delay to settle down,
1050 * else crb_window returns 0xffffffff
1052 if (off
== QLA82XX_ROMUSB_GLB_SW_RESET
)
1055 /* ISP requires millisec delay between
1056 * successive CRB register updation
1063 /* Resetting the data and instruction cache */
1064 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0xec, 0x1e);
1065 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0x4c, 8);
1066 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_I
+0x4c, 8);
1068 /* Clear all protocol processing engines */
1069 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0x8, 0);
1070 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0xc, 0);
1071 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0x8, 0);
1072 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0xc, 0);
1073 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0x8, 0);
1074 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0xc, 0);
1075 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0x8, 0);
1076 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0xc, 0);
1081 static int qla4_8xxx_check_for_bad_spd(struct scsi_qla_host
*ha
)
1084 val
= qla4_8xxx_rd_32(ha
, BOOT_LOADER_DIMM_STATUS
) ;
1085 val
&= QLA82XX_BOOT_LOADER_MN_ISSUE
;
1086 if (val
& QLA82XX_PEG_TUNE_MN_SPD_ZEROED
) {
1087 printk("Memory DIMM SPD not programmed. Assumed valid.\n");
1090 printk("Memory DIMM type incorrect. Info:%08X.\n", val
);
1097 qla4_8xxx_load_from_flash(struct scsi_qla_host
*ha
, uint32_t image_start
)
1101 long flashaddr
, memaddr
;
1105 flashaddr
= memaddr
= ha
->hw
.flt_region_bootload
;
1106 size
= (image_start
- flashaddr
)/8;
1108 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1109 ha
->host_no
, __func__
, flashaddr
, image_start
));
1111 for (i
= 0; i
< size
; i
++) {
1112 if ((qla4_8xxx_rom_fast_read(ha
, flashaddr
, (int *)&low
)) ||
1113 (qla4_8xxx_rom_fast_read(ha
, flashaddr
+ 4,
1117 data
= ((u64
)high
<< 32) | low
;
1118 qla4_8xxx_pci_mem_write_2M(ha
, memaddr
, &data
, 8);
1129 read_lock(&ha
->hw_lock
);
1130 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1131 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1132 read_unlock(&ha
->hw_lock
);
1137 static int qla4_8xxx_load_fw(struct scsi_qla_host
*ha
, uint32_t image_start
)
1141 qla4_8xxx_wr_32(ha
, CRB_CMDPEG_STATE
, 0);
1142 if (qla4_8xxx_pinit_from_rom(ha
, 0) != QLA_SUCCESS
) {
1143 printk(KERN_WARNING
"%s: Error during CRB Initialization\n",
1150 /* at this point, QM is in reset. This could be a problem if there are
1151 * incoming d* transition queue messages. QM/PCIE could wedge.
1152 * To get around this, QM is brought out of reset.
1155 rst
= qla4_8xxx_rd_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
);
1158 qla4_8xxx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, rst
);
1160 if (qla4_8xxx_load_from_flash(ha
, image_start
)) {
1161 printk("%s: Error trying to load fw from flash!\n", __func__
);
1169 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host
*ha
,
1170 u64 off
, void *data
, int size
)
1172 int i
, j
= 0, k
, start
, end
, loop
, sz
[2], off0
[2];
1175 uint64_t off8
, val
, mem_crb
, word
[2] = {0, 0};
1178 * If not MN, go check for MS or invalid.
1181 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1182 mem_crb
= QLA82XX_CRB_QDR_NET
;
1184 mem_crb
= QLA82XX_CRB_DDR_NET
;
1185 if (qla4_8xxx_pci_mem_bound_check(ha
, off
, size
) == 0)
1186 return qla4_8xxx_pci_mem_read_direct(ha
,
1191 off8
= off
& 0xfffffff0;
1192 off0
[0] = off
& 0xf;
1193 sz
[0] = (size
< (16 - off0
[0])) ? size
: (16 - off0
[0]);
1196 loop
= ((off0
[0] + size
- 1) >> shift_amount
) + 1;
1198 sz
[1] = size
- sz
[0];
1200 for (i
= 0; i
< loop
; i
++) {
1201 temp
= off8
+ (i
<< shift_amount
);
1202 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_LO
, temp
);
1204 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_HI
, temp
);
1205 temp
= MIU_TA_CTL_ENABLE
;
1206 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1207 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
1208 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1210 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1211 temp
= qla4_8xxx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1212 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1216 if (j
>= MAX_CTL_CHECK
) {
1217 if (printk_ratelimit())
1218 ql4_printk(KERN_ERR
, ha
,
1219 "failed to read through agent\n");
1223 start
= off0
[i
] >> 2;
1224 end
= (off0
[i
] + sz
[i
] - 1) >> 2;
1225 for (k
= start
; k
<= end
; k
++) {
1226 temp
= qla4_8xxx_rd_32(ha
,
1227 mem_crb
+ MIU_TEST_AGT_RDDATA(k
));
1228 word
[i
] |= ((uint64_t)temp
<< (32 * (k
& 1)));
1232 if (j
>= MAX_CTL_CHECK
)
1235 if ((off0
[0] & 7) == 0) {
1238 val
= ((word
[0] >> (off0
[0] * 8)) & (~(~0ULL << (sz
[0] * 8)))) |
1239 ((word
[1] & (~(~0ULL << (sz
[1] * 8)))) << (sz
[0] * 8));
1244 *(uint8_t *)data
= val
;
1247 *(uint16_t *)data
= val
;
1250 *(uint32_t *)data
= val
;
1253 *(uint64_t *)data
= val
;
1260 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host
*ha
,
1261 u64 off
, void *data
, int size
)
1263 int i
, j
, ret
= 0, loop
, sz
[2], off0
;
1264 int scale
, shift_amount
, startword
;
1266 uint64_t off8
, mem_crb
, tmpw
, word
[2] = {0, 0};
1269 * If not MN, go check for MS or invalid.
1271 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1272 mem_crb
= QLA82XX_CRB_QDR_NET
;
1274 mem_crb
= QLA82XX_CRB_DDR_NET
;
1275 if (qla4_8xxx_pci_mem_bound_check(ha
, off
, size
) == 0)
1276 return qla4_8xxx_pci_mem_write_direct(ha
,
1281 sz
[0] = (size
< (8 - off0
)) ? size
: (8 - off0
);
1282 sz
[1] = size
- sz
[0];
1284 off8
= off
& 0xfffffff0;
1285 loop
= (((off
& 0xf) + size
- 1) >> 4) + 1;
1288 startword
= (off
& 0xf)/8;
1290 for (i
= 0; i
< loop
; i
++) {
1291 if (qla4_8xxx_pci_mem_read_2M(ha
, off8
+
1292 (i
<< shift_amount
), &word
[i
* scale
], 8))
1298 tmpw
= *((uint8_t *)data
);
1301 tmpw
= *((uint16_t *)data
);
1304 tmpw
= *((uint32_t *)data
);
1308 tmpw
= *((uint64_t *)data
);
1313 word
[startword
] = tmpw
;
1316 ~((~(~0ULL << (sz
[0] * 8))) << (off0
* 8));
1317 word
[startword
] |= tmpw
<< (off0
* 8);
1321 word
[startword
+1] &= ~(~0ULL << (sz
[1] * 8));
1322 word
[startword
+1] |= tmpw
>> (sz
[0] * 8);
1325 for (i
= 0; i
< loop
; i
++) {
1326 temp
= off8
+ (i
<< shift_amount
);
1327 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_LO
, temp
);
1329 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_HI
, temp
);
1330 temp
= word
[i
* scale
] & 0xffffffff;
1331 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_LO
, temp
);
1332 temp
= (word
[i
* scale
] >> 32) & 0xffffffff;
1333 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_HI
, temp
);
1334 temp
= word
[i
*scale
+ 1] & 0xffffffff;
1335 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_WRDATA_UPPER_LO
,
1337 temp
= (word
[i
*scale
+ 1] >> 32) & 0xffffffff;
1338 qla4_8xxx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_WRDATA_UPPER_HI
,
1341 temp
= MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1342 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_CTRL
, temp
);
1343 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1344 qla4_8xxx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_CTRL
, temp
);
1346 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1347 temp
= qla4_8xxx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1348 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1352 if (j
>= MAX_CTL_CHECK
) {
1353 if (printk_ratelimit())
1354 ql4_printk(KERN_ERR
, ha
,
1355 "failed to write through agent\n");
1364 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host
*ha
, int pegtune_val
)
1371 val
= qla4_8xxx_rd_32(ha
, CRB_CMDPEG_STATE
);
1372 if ((val
== PHAN_INITIALIZE_COMPLETE
) ||
1373 (val
== PHAN_INITIALIZE_ACK
))
1375 set_current_state(TASK_UNINTERRUPTIBLE
);
1376 schedule_timeout(500);
1378 } while (--retries
);
1380 qla4_8xxx_check_for_bad_spd(ha
);
1383 pegtune_val
= qla4_8xxx_rd_32(ha
,
1384 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE
);
1385 printk(KERN_WARNING
"%s: init failed, "
1386 "pegtune_val = %x\n", __func__
, pegtune_val
);
1393 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host
*ha
)
1399 read_lock(&ha
->hw_lock
);
1400 state
= qla4_8xxx_rd_32(ha
, CRB_RCVPEG_STATE
);
1401 read_unlock(&ha
->hw_lock
);
1403 while ((state
!= PHAN_PEG_RCV_INITIALIZED
) && (loops
< 30000)) {
1406 read_lock(&ha
->hw_lock
);
1407 state
= qla4_8xxx_rd_32(ha
, CRB_RCVPEG_STATE
);
1408 read_unlock(&ha
->hw_lock
);
1413 if (loops
>= 30000) {
1414 DEBUG2(ql4_printk(KERN_INFO
, ha
,
1415 "Receive Peg initialization not complete: 0x%x.\n", state
));
1423 qla4_8xxx_set_drv_active(struct scsi_qla_host
*ha
)
1425 uint32_t drv_active
;
1427 drv_active
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
1428 drv_active
|= (1 << (ha
->func_num
* 4));
1429 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
1433 qla4_8xxx_clear_drv_active(struct scsi_qla_host
*ha
)
1435 uint32_t drv_active
;
1437 drv_active
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
1438 drv_active
&= ~(1 << (ha
->func_num
* 4));
1439 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
1443 qla4_8xxx_need_reset(struct scsi_qla_host
*ha
)
1445 uint32_t drv_state
, drv_active
;
1448 drv_active
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
1449 drv_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1450 rval
= drv_state
& (1 << (ha
->func_num
* 4));
1451 if ((test_bit(AF_EEH_BUSY
, &ha
->flags
)) && drv_active
)
1458 qla4_8xxx_set_rst_ready(struct scsi_qla_host
*ha
)
1462 drv_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1463 drv_state
|= (1 << (ha
->func_num
* 4));
1464 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
1468 qla4_8xxx_clear_rst_ready(struct scsi_qla_host
*ha
)
1472 drv_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1473 drv_state
&= ~(1 << (ha
->func_num
* 4));
1474 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
1478 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host
*ha
)
1480 uint32_t qsnt_state
;
1482 qsnt_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1483 qsnt_state
|= (2 << (ha
->func_num
* 4));
1484 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
1489 qla4_8xxx_start_firmware(struct scsi_qla_host
*ha
, uint32_t image_start
)
1494 /* scrub dma mask expansion register */
1495 qla4_8xxx_wr_32(ha
, CRB_DMA_SHIFT
, 0x55555555);
1497 /* Overwrite stale initialization register values */
1498 qla4_8xxx_wr_32(ha
, CRB_CMDPEG_STATE
, 0);
1499 qla4_8xxx_wr_32(ha
, CRB_RCVPEG_STATE
, 0);
1500 qla4_8xxx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS1
, 0);
1501 qla4_8xxx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS2
, 0);
1503 if (qla4_8xxx_load_fw(ha
, image_start
) != QLA_SUCCESS
) {
1504 printk("%s: Error trying to start fw!\n", __func__
);
1508 /* Handshake with the card before we register the devices. */
1509 if (qla4_8xxx_cmdpeg_ready(ha
, 0) != QLA_SUCCESS
) {
1510 printk("%s: Error during card handshake!\n", __func__
);
1514 /* Negotiated Link width */
1515 pcie_cap
= pci_find_capability(ha
->pdev
, PCI_CAP_ID_EXP
);
1516 pci_read_config_word(ha
->pdev
, pcie_cap
+ PCI_EXP_LNKSTA
, &lnk
);
1517 ha
->link_width
= (lnk
>> 4) & 0x3f;
1519 /* Synchronize with Receive peg */
1520 return qla4_8xxx_rcvpeg_ready(ha
);
1524 qla4_8xxx_try_start_fw(struct scsi_qla_host
*ha
)
1526 int rval
= QLA_ERROR
;
1530 * 1) Operational firmware residing in flash.
1534 ql4_printk(KERN_INFO
, ha
,
1535 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1536 rval
= qla4_8xxx_get_flash_info(ha
);
1537 if (rval
!= QLA_SUCCESS
)
1540 ql4_printk(KERN_INFO
, ha
,
1541 "FW: Attempting to load firmware from flash...\n");
1542 rval
= qla4_8xxx_start_firmware(ha
, ha
->hw
.flt_region_fw
);
1543 if (rval
== QLA_SUCCESS
)
1546 ql4_printk(KERN_ERR
, ha
, "FW: Load firmware from flash FAILED...\n");
1552 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1553 * @ha: pointer to adapter structure
1555 * Note: IDC lock must be held upon entry
1558 qla4_8xxx_device_bootstrap(struct scsi_qla_host
*ha
)
1560 int rval
, i
, timeout
;
1561 uint32_t old_count
, count
;
1563 if (qla4_8xxx_need_reset(ha
))
1564 goto dev_initialize
;
1566 old_count
= qla4_8xxx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
1568 for (i
= 0; i
< 10; i
++) {
1569 timeout
= msleep_interruptible(200);
1571 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
1572 QLA82XX_DEV_FAILED
);
1576 count
= qla4_8xxx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
1577 if (count
!= old_count
)
1582 /* set to DEV_INITIALIZING */
1583 ql4_printk(KERN_INFO
, ha
, "HW State: INITIALIZING\n");
1584 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_INITIALIZING
);
1586 /* Driver that sets device state to initializating sets IDC version */
1587 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DRV_IDC_VERSION
, QLA82XX_IDC_VERSION
);
1589 qla4_8xxx_idc_unlock(ha
);
1590 rval
= qla4_8xxx_try_start_fw(ha
);
1591 qla4_8xxx_idc_lock(ha
);
1593 if (rval
!= QLA_SUCCESS
) {
1594 ql4_printk(KERN_INFO
, ha
, "HW State: FAILED\n");
1595 qla4_8xxx_clear_drv_active(ha
);
1596 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_FAILED
);
1601 ql4_printk(KERN_INFO
, ha
, "HW State: READY\n");
1602 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_READY
);
1608 * qla4_8xxx_need_reset_handler - Code to start reset sequence
1609 * @ha: pointer to adapter structure
1611 * Note: IDC lock must be held upon entry
1614 qla4_8xxx_need_reset_handler(struct scsi_qla_host
*ha
)
1616 uint32_t dev_state
, drv_state
, drv_active
;
1617 unsigned long reset_timeout
;
1619 ql4_printk(KERN_INFO
, ha
,
1620 "Performing ISP error recovery\n");
1622 if (test_and_clear_bit(AF_ONLINE
, &ha
->flags
)) {
1623 qla4_8xxx_idc_unlock(ha
);
1624 ha
->isp_ops
->disable_intrs(ha
);
1625 qla4_8xxx_idc_lock(ha
);
1628 qla4_8xxx_set_rst_ready(ha
);
1630 /* wait for 10 seconds for reset ack from all functions */
1631 reset_timeout
= jiffies
+ (ha
->nx_reset_timeout
* HZ
);
1633 drv_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1634 drv_active
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
1636 ql4_printk(KERN_INFO
, ha
,
1637 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1638 __func__
, ha
->host_no
, drv_state
, drv_active
);
1640 while (drv_state
!= drv_active
) {
1641 if (time_after_eq(jiffies
, reset_timeout
)) {
1642 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME
);
1646 qla4_8xxx_idc_unlock(ha
);
1648 qla4_8xxx_idc_lock(ha
);
1650 drv_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
1651 drv_active
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
1654 dev_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
1655 ql4_printk(KERN_INFO
, ha
, "3:Device state is 0x%x = %s\n", dev_state
,
1656 dev_state
< MAX_STATES
? qdev_state
[dev_state
] : "Unknown");
1658 /* Force to DEV_COLD unless someone else is starting a reset */
1659 if (dev_state
!= QLA82XX_DEV_INITIALIZING
) {
1660 ql4_printk(KERN_INFO
, ha
, "HW State: COLD/RE-INIT\n");
1661 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_COLD
);
1666 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1667 * @ha: pointer to adapter structure
1670 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host
*ha
)
1672 qla4_8xxx_idc_lock(ha
);
1673 qla4_8xxx_set_qsnt_ready(ha
);
1674 qla4_8xxx_idc_unlock(ha
);
1678 * qla4_8xxx_device_state_handler - Adapter state machine
1679 * @ha: pointer to host adapter structure.
1681 * Note: IDC lock must be UNLOCKED upon entry
1683 int qla4_8xxx_device_state_handler(struct scsi_qla_host
*ha
)
1686 int rval
= QLA_SUCCESS
;
1687 unsigned long dev_init_timeout
;
1689 if (!test_bit(AF_INIT_DONE
, &ha
->flags
))
1690 qla4_8xxx_set_drv_active(ha
);
1692 dev_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
1693 ql4_printk(KERN_INFO
, ha
, "1:Device state is 0x%x = %s\n", dev_state
,
1694 dev_state
< MAX_STATES
? qdev_state
[dev_state
] : "Unknown");
1696 /* wait for 30 seconds for device to go ready */
1697 dev_init_timeout
= jiffies
+ (ha
->nx_dev_init_timeout
* HZ
);
1700 qla4_8xxx_idc_lock(ha
);
1702 if (time_after_eq(jiffies
, dev_init_timeout
)) {
1703 ql4_printk(KERN_WARNING
, ha
, "Device init failed!\n");
1704 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
1705 QLA82XX_DEV_FAILED
);
1708 dev_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
1709 ql4_printk(KERN_INFO
, ha
,
1710 "2:Device state is 0x%x = %s\n", dev_state
,
1711 dev_state
< MAX_STATES
? qdev_state
[dev_state
] : "Unknown");
1713 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1714 switch (dev_state
) {
1715 case QLA82XX_DEV_READY
:
1716 qla4_8xxx_idc_unlock(ha
);
1718 case QLA82XX_DEV_COLD
:
1719 rval
= qla4_8xxx_device_bootstrap(ha
);
1720 qla4_8xxx_idc_unlock(ha
);
1722 case QLA82XX_DEV_INITIALIZING
:
1723 qla4_8xxx_idc_unlock(ha
);
1726 case QLA82XX_DEV_NEED_RESET
:
1727 if (!ql4xdontresethba
) {
1728 qla4_8xxx_need_reset_handler(ha
);
1729 /* Update timeout value after need
1731 dev_init_timeout
= jiffies
+
1732 (ha
->nx_dev_init_timeout
* HZ
);
1734 qla4_8xxx_idc_unlock(ha
);
1736 case QLA82XX_DEV_NEED_QUIESCENT
:
1737 qla4_8xxx_idc_unlock(ha
);
1738 /* idc locked/unlocked in handler */
1739 qla4_8xxx_need_qsnt_handler(ha
);
1740 qla4_8xxx_idc_lock(ha
);
1741 /* fall thru needs idc_locked */
1742 case QLA82XX_DEV_QUIESCENT
:
1743 qla4_8xxx_idc_unlock(ha
);
1746 case QLA82XX_DEV_FAILED
:
1747 qla4_8xxx_idc_unlock(ha
);
1748 qla4xxx_dead_adapter_cleanup(ha
);
1752 qla4_8xxx_idc_unlock(ha
);
1753 qla4xxx_dead_adapter_cleanup(ha
);
1762 int qla4_8xxx_load_risc(struct scsi_qla_host
*ha
)
1765 retval
= qla4_8xxx_device_state_handler(ha
);
1767 if (retval
== QLA_SUCCESS
&&
1768 !test_bit(AF_INIT_DONE
, &ha
->flags
)) {
1769 retval
= qla4xxx_request_irqs(ha
);
1770 if (retval
!= QLA_SUCCESS
) {
1771 ql4_printk(KERN_WARNING
, ha
,
1772 "Failed to reserve interrupt %d already in use.\n",
1775 set_bit(AF_IRQ_ATTACHED
, &ha
->flags
);
1776 ha
->host
->irq
= ha
->pdev
->irq
;
1777 ql4_printk(KERN_INFO
, ha
, "%s: irq %d attached\n",
1778 __func__
, ha
->pdev
->irq
);
1784 /*****************************************************************************/
1785 /* Flash Manipulation Routines */
1786 /*****************************************************************************/
1788 #define OPTROM_BURST_SIZE 0x1000
1789 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
1791 #define FARX_DATA_FLAG BIT_31
1792 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1793 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1795 static inline uint32_t
1796 flash_conf_addr(struct ql82xx_hw_data
*hw
, uint32_t faddr
)
1798 return hw
->flash_conf_off
| faddr
;
1801 static inline uint32_t
1802 flash_data_addr(struct ql82xx_hw_data
*hw
, uint32_t faddr
)
1804 return hw
->flash_data_off
| faddr
;
1808 qla4_8xxx_read_flash_data(struct scsi_qla_host
*ha
, uint32_t *dwptr
,
1809 uint32_t faddr
, uint32_t length
)
1814 while ((qla4_8xxx_rom_lock(ha
) != 0) && (loops
< 50000)) {
1819 if (loops
>= 50000) {
1820 ql4_printk(KERN_WARNING
, ha
, "ROM lock failed\n");
1824 /* Dword reads to flash. */
1825 for (i
= 0; i
< length
/4; i
++, faddr
+= 4) {
1826 if (qla4_8xxx_do_rom_fast_read(ha
, faddr
, &val
)) {
1827 ql4_printk(KERN_WARNING
, ha
,
1828 "Do ROM fast read failed\n");
1831 dwptr
[i
] = __constant_cpu_to_le32(val
);
1835 qla4_8xxx_rom_unlock(ha
);
1840 * Address and length are byte address
1843 qla4_8xxx_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1844 uint32_t offset
, uint32_t length
)
1846 qla4_8xxx_read_flash_data(ha
, (uint32_t *)buf
, offset
, length
);
1851 qla4_8xxx_find_flt_start(struct scsi_qla_host
*ha
, uint32_t *start
)
1853 const char *loc
, *locations
[] = { "DEF", "PCI" };
1856 * FLT-location structure resides after the last PCI region.
1859 /* Begin with sane defaults. */
1861 *start
= FA_FLASH_LAYOUT_ADDR_82
;
1863 DEBUG2(ql4_printk(KERN_INFO
, ha
, "FLTL[%s] = 0x%x.\n", loc
, *start
));
1868 qla4_8xxx_get_flt_info(struct scsi_qla_host
*ha
, uint32_t flt_addr
)
1870 const char *loc
, *locations
[] = { "DEF", "FLT" };
1872 uint16_t cnt
, chksum
;
1874 struct qla_flt_header
*flt
;
1875 struct qla_flt_region
*region
;
1876 struct ql82xx_hw_data
*hw
= &ha
->hw
;
1878 hw
->flt_region_flt
= flt_addr
;
1879 wptr
= (uint16_t *)ha
->request_ring
;
1880 flt
= (struct qla_flt_header
*)ha
->request_ring
;
1881 region
= (struct qla_flt_region
*)&flt
[1];
1882 qla4_8xxx_read_optrom_data(ha
, (uint8_t *)ha
->request_ring
,
1883 flt_addr
<< 2, OPTROM_BURST_SIZE
);
1884 if (*wptr
== __constant_cpu_to_le16(0xffff))
1886 if (flt
->version
!= __constant_cpu_to_le16(1)) {
1887 DEBUG2(ql4_printk(KERN_INFO
, ha
, "Unsupported FLT detected: "
1888 "version=0x%x length=0x%x checksum=0x%x.\n",
1889 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
1890 le16_to_cpu(flt
->checksum
)));
1894 cnt
= (sizeof(struct qla_flt_header
) + le16_to_cpu(flt
->length
)) >> 1;
1895 for (chksum
= 0; cnt
; cnt
--)
1896 chksum
+= le16_to_cpu(*wptr
++);
1898 DEBUG2(ql4_printk(KERN_INFO
, ha
, "Inconsistent FLT detected: "
1899 "version=0x%x length=0x%x checksum=0x%x.\n",
1900 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
1906 cnt
= le16_to_cpu(flt
->length
) / sizeof(struct qla_flt_region
);
1907 for ( ; cnt
; cnt
--, region
++) {
1908 /* Store addresses as DWORD offsets. */
1909 start
= le32_to_cpu(region
->start
) >> 2;
1911 DEBUG3(ql4_printk(KERN_DEBUG
, ha
, "FLT[%02x]: start=0x%x "
1912 "end=0x%x size=0x%x.\n", le32_to_cpu(region
->code
), start
,
1913 le32_to_cpu(region
->end
) >> 2, le32_to_cpu(region
->size
)));
1915 switch (le32_to_cpu(region
->code
) & 0xff) {
1917 hw
->flt_region_fdt
= start
;
1919 case FLT_REG_BOOT_CODE_82
:
1920 hw
->flt_region_boot
= start
;
1923 hw
->flt_region_fw
= start
;
1925 case FLT_REG_BOOTLOAD_82
:
1926 hw
->flt_region_bootload
= start
;
1933 /* Use hardcoded defaults. */
1936 hw
->flt_region_fdt
= FA_FLASH_DESCR_ADDR_82
;
1937 hw
->flt_region_boot
= FA_BOOT_CODE_ADDR_82
;
1938 hw
->flt_region_bootload
= FA_BOOT_LOAD_ADDR_82
;
1939 hw
->flt_region_fw
= FA_RISC_CODE_ADDR_82
;
1941 DEBUG2(ql4_printk(KERN_INFO
, ha
, "FLT[%s]: flt=0x%x fdt=0x%x "
1942 "boot=0x%x bootload=0x%x fw=0x%x\n", loc
, hw
->flt_region_flt
,
1943 hw
->flt_region_fdt
, hw
->flt_region_boot
, hw
->flt_region_bootload
,
1944 hw
->flt_region_fw
));
1948 qla4_8xxx_get_fdt_info(struct scsi_qla_host
*ha
)
1950 #define FLASH_BLK_SIZE_4K 0x1000
1951 #define FLASH_BLK_SIZE_32K 0x8000
1952 #define FLASH_BLK_SIZE_64K 0x10000
1953 const char *loc
, *locations
[] = { "MID", "FDT" };
1954 uint16_t cnt
, chksum
;
1956 struct qla_fdt_layout
*fdt
;
1959 struct ql82xx_hw_data
*hw
= &ha
->hw
;
1961 hw
->flash_conf_off
= FARX_ACCESS_FLASH_CONF
;
1962 hw
->flash_data_off
= FARX_ACCESS_FLASH_DATA
;
1964 wptr
= (uint16_t *)ha
->request_ring
;
1965 fdt
= (struct qla_fdt_layout
*)ha
->request_ring
;
1966 qla4_8xxx_read_optrom_data(ha
, (uint8_t *)ha
->request_ring
,
1967 hw
->flt_region_fdt
<< 2, OPTROM_BURST_SIZE
);
1969 if (*wptr
== __constant_cpu_to_le16(0xffff))
1972 if (fdt
->sig
[0] != 'Q' || fdt
->sig
[1] != 'L' || fdt
->sig
[2] != 'I' ||
1976 for (cnt
= 0, chksum
= 0; cnt
< sizeof(struct qla_fdt_layout
) >> 1;
1978 chksum
+= le16_to_cpu(*wptr
++);
1981 DEBUG2(ql4_printk(KERN_INFO
, ha
, "Inconsistent FDT detected: "
1982 "checksum=0x%x id=%c version=0x%x.\n", chksum
, fdt
->sig
[0],
1983 le16_to_cpu(fdt
->version
)));
1988 mid
= le16_to_cpu(fdt
->man_id
);
1989 fid
= le16_to_cpu(fdt
->id
);
1990 hw
->fdt_wrt_disable
= fdt
->wrt_disable_bits
;
1991 hw
->fdt_erase_cmd
= flash_conf_addr(hw
, 0x0300 | fdt
->erase_cmd
);
1992 hw
->fdt_block_size
= le32_to_cpu(fdt
->block_size
);
1994 if (fdt
->unprotect_sec_cmd
) {
1995 hw
->fdt_unprotect_sec_cmd
= flash_conf_addr(hw
, 0x0300 |
1996 fdt
->unprotect_sec_cmd
);
1997 hw
->fdt_protect_sec_cmd
= fdt
->protect_sec_cmd
?
1998 flash_conf_addr(hw
, 0x0300 | fdt
->protect_sec_cmd
) :
1999 flash_conf_addr(hw
, 0x0336);
2005 hw
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
2007 DEBUG2(ql4_printk(KERN_INFO
, ha
, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2008 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc
, mid
, fid
,
2009 hw
->fdt_erase_cmd
, hw
->fdt_protect_sec_cmd
,
2010 hw
->fdt_unprotect_sec_cmd
, hw
->fdt_wrt_disable
,
2011 hw
->fdt_block_size
));
2015 qla4_8xxx_get_idc_param(struct scsi_qla_host
*ha
)
2017 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2020 if (!is_qla8022(ha
))
2022 wptr
= (uint32_t *)ha
->request_ring
;
2023 qla4_8xxx_read_optrom_data(ha
, (uint8_t *)ha
->request_ring
,
2024 QLA82XX_IDC_PARAM_ADDR
, 8);
2026 if (*wptr
== __constant_cpu_to_le32(0xffffffff)) {
2027 ha
->nx_dev_init_timeout
= ROM_DEV_INIT_TIMEOUT
;
2028 ha
->nx_reset_timeout
= ROM_DRV_RESET_ACK_TIMEOUT
;
2030 ha
->nx_dev_init_timeout
= le32_to_cpu(*wptr
++);
2031 ha
->nx_reset_timeout
= le32_to_cpu(*wptr
);
2034 DEBUG2(ql4_printk(KERN_DEBUG
, ha
,
2035 "ha->nx_dev_init_timeout = %d\n", ha
->nx_dev_init_timeout
));
2036 DEBUG2(ql4_printk(KERN_DEBUG
, ha
,
2037 "ha->nx_reset_timeout = %d\n", ha
->nx_reset_timeout
));
2042 qla4_8xxx_get_flash_info(struct scsi_qla_host
*ha
)
2047 ret
= qla4_8xxx_find_flt_start(ha
, &flt_addr
);
2048 if (ret
!= QLA_SUCCESS
)
2051 qla4_8xxx_get_flt_info(ha
, flt_addr
);
2052 qla4_8xxx_get_fdt_info(ha
);
2053 qla4_8xxx_get_idc_param(ha
);
2059 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2060 * @ha: pointer to host adapter structure.
2063 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2064 * not be available after successful return. Driver must cleanup potential
2065 * outstanding I/O's after calling this funcion.
2068 qla4_8xxx_stop_firmware(struct scsi_qla_host
*ha
)
2071 uint32_t mbox_cmd
[MBOX_REG_COUNT
];
2072 uint32_t mbox_sts
[MBOX_REG_COUNT
];
2074 memset(&mbox_cmd
, 0, sizeof(mbox_cmd
));
2075 memset(&mbox_sts
, 0, sizeof(mbox_sts
));
2077 mbox_cmd
[0] = MBOX_CMD_STOP_FW
;
2078 status
= qla4xxx_mailbox_command(ha
, MBOX_REG_COUNT
, 1,
2079 &mbox_cmd
[0], &mbox_sts
[0]);
2081 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha
->host_no
,
2087 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2088 * @ha: pointer to host adapter structure.
2091 qla4_8xxx_isp_reset(struct scsi_qla_host
*ha
)
2096 qla4_8xxx_idc_lock(ha
);
2097 dev_state
= qla4_8xxx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
2099 if (dev_state
== QLA82XX_DEV_READY
) {
2100 ql4_printk(KERN_INFO
, ha
, "HW State: NEED RESET\n");
2101 qla4_8xxx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
2102 QLA82XX_DEV_NEED_RESET
);
2104 ql4_printk(KERN_INFO
, ha
, "HW State: DEVICE INITIALIZING\n");
2106 qla4_8xxx_idc_unlock(ha
);
2108 rval
= qla4_8xxx_device_state_handler(ha
);
2110 qla4_8xxx_idc_lock(ha
);
2111 qla4_8xxx_clear_rst_ready(ha
);
2112 qla4_8xxx_idc_unlock(ha
);
2114 if (rval
== QLA_SUCCESS
)
2115 clear_bit(AF_FW_RECOVERY
, &ha
->flags
);
2121 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2122 * @ha: pointer to host adapter structure.
2125 int qla4_8xxx_get_sys_info(struct scsi_qla_host
*ha
)
2127 uint32_t mbox_cmd
[MBOX_REG_COUNT
];
2128 uint32_t mbox_sts
[MBOX_REG_COUNT
];
2129 struct mbx_sys_info
*sys_info
;
2130 dma_addr_t sys_info_dma
;
2131 int status
= QLA_ERROR
;
2133 sys_info
= dma_alloc_coherent(&ha
->pdev
->dev
, sizeof(*sys_info
),
2134 &sys_info_dma
, GFP_KERNEL
);
2135 if (sys_info
== NULL
) {
2136 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2137 ha
->host_no
, __func__
));
2141 memset(sys_info
, 0, sizeof(*sys_info
));
2142 memset(&mbox_cmd
, 0, sizeof(mbox_cmd
));
2143 memset(&mbox_sts
, 0, sizeof(mbox_sts
));
2145 mbox_cmd
[0] = MBOX_CMD_GET_SYS_INFO
;
2146 mbox_cmd
[1] = LSDW(sys_info_dma
);
2147 mbox_cmd
[2] = MSDW(sys_info_dma
);
2148 mbox_cmd
[4] = sizeof(*sys_info
);
2150 if (qla4xxx_mailbox_command(ha
, MBOX_REG_COUNT
, 6, &mbox_cmd
[0],
2151 &mbox_sts
[0]) != QLA_SUCCESS
) {
2152 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2153 ha
->host_no
, __func__
));
2154 goto exit_validate_mac82
;
2157 /* Make sure we receive the minimum required data to cache internally */
2158 if (mbox_sts
[4] < offsetof(struct mbx_sys_info
, reserved
)) {
2159 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2160 " error (%x)\n", ha
->host_no
, __func__
, mbox_sts
[4]));
2161 goto exit_validate_mac82
;
2165 /* Save M.A.C. address & serial_number */
2166 memcpy(ha
->my_mac
, &sys_info
->mac_addr
[0],
2167 min(sizeof(ha
->my_mac
), sizeof(sys_info
->mac_addr
)));
2168 memcpy(ha
->serial_number
, &sys_info
->serial_number
,
2169 min(sizeof(ha
->serial_number
), sizeof(sys_info
->serial_number
)));
2171 DEBUG2(printk("scsi%ld: %s: "
2172 "mac %02x:%02x:%02x:%02x:%02x:%02x "
2173 "serial %s\n", ha
->host_no
, __func__
,
2174 ha
->my_mac
[0], ha
->my_mac
[1], ha
->my_mac
[2],
2175 ha
->my_mac
[3], ha
->my_mac
[4], ha
->my_mac
[5],
2176 ha
->serial_number
));
2178 status
= QLA_SUCCESS
;
2180 exit_validate_mac82
:
2181 dma_free_coherent(&ha
->pdev
->dev
, sizeof(*sys_info
), sys_info
,
2186 /* Interrupt handling helpers. */
2189 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host
*ha
)
2191 uint32_t mbox_cmd
[MBOX_REG_COUNT
];
2192 uint32_t mbox_sts
[MBOX_REG_COUNT
];
2194 DEBUG2(ql4_printk(KERN_INFO
, ha
, "%s\n", __func__
));
2196 memset(&mbox_cmd
, 0, sizeof(mbox_cmd
));
2197 memset(&mbox_sts
, 0, sizeof(mbox_sts
));
2198 mbox_cmd
[0] = MBOX_CMD_ENABLE_INTRS
;
2199 mbox_cmd
[1] = INTR_ENABLE
;
2200 if (qla4xxx_mailbox_command(ha
, MBOX_REG_COUNT
, 1, &mbox_cmd
[0],
2201 &mbox_sts
[0]) != QLA_SUCCESS
) {
2202 DEBUG2(ql4_printk(KERN_INFO
, ha
,
2203 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2204 __func__
, mbox_sts
[0]));
2211 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host
*ha
)
2213 uint32_t mbox_cmd
[MBOX_REG_COUNT
];
2214 uint32_t mbox_sts
[MBOX_REG_COUNT
];
2216 DEBUG2(ql4_printk(KERN_INFO
, ha
, "%s\n", __func__
));
2218 memset(&mbox_cmd
, 0, sizeof(mbox_cmd
));
2219 memset(&mbox_sts
, 0, sizeof(mbox_sts
));
2220 mbox_cmd
[0] = MBOX_CMD_ENABLE_INTRS
;
2221 mbox_cmd
[1] = INTR_DISABLE
;
2222 if (qla4xxx_mailbox_command(ha
, MBOX_REG_COUNT
, 1, &mbox_cmd
[0],
2223 &mbox_sts
[0]) != QLA_SUCCESS
) {
2224 DEBUG2(ql4_printk(KERN_INFO
, ha
,
2225 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2226 __func__
, mbox_sts
[0]));
2234 qla4_8xxx_enable_intrs(struct scsi_qla_host
*ha
)
2236 qla4_8xxx_mbx_intr_enable(ha
);
2238 spin_lock_irq(&ha
->hardware_lock
);
2239 /* BIT 10 - reset */
2240 qla4_8xxx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2241 spin_unlock_irq(&ha
->hardware_lock
);
2242 set_bit(AF_INTERRUPTS_ON
, &ha
->flags
);
2246 qla4_8xxx_disable_intrs(struct scsi_qla_host
*ha
)
2248 if (test_bit(AF_INTERRUPTS_ON
, &ha
->flags
))
2249 qla4_8xxx_mbx_intr_disable(ha
);
2251 spin_lock_irq(&ha
->hardware_lock
);
2253 qla4_8xxx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0x0400);
2254 spin_unlock_irq(&ha
->hardware_lock
);
2255 clear_bit(AF_INTERRUPTS_ON
, &ha
->flags
);
2258 struct ql4_init_msix_entry
{
2262 irq_handler_t handler
;
2265 static struct ql4_init_msix_entry qla4_8xxx_msix_entries
[QLA_MSIX_ENTRIES
] = {
2266 { QLA_MSIX_DEFAULT
, QLA_MIDX_DEFAULT
,
2267 "qla4xxx (default)",
2268 (irq_handler_t
)qla4_8xxx_default_intr_handler
},
2269 { QLA_MSIX_RSP_Q
, QLA_MIDX_RSP_Q
,
2270 "qla4xxx (rsp_q)", (irq_handler_t
)qla4_8xxx_msix_rsp_q
},
2274 qla4_8xxx_disable_msix(struct scsi_qla_host
*ha
)
2277 struct ql4_msix_entry
*qentry
;
2279 for (i
= 0; i
< QLA_MSIX_ENTRIES
; i
++) {
2280 qentry
= &ha
->msix_entries
[qla4_8xxx_msix_entries
[i
].index
];
2281 if (qentry
->have_irq
) {
2282 free_irq(qentry
->msix_vector
, ha
);
2283 DEBUG2(ql4_printk(KERN_INFO
, ha
, "%s: %s\n",
2284 __func__
, qla4_8xxx_msix_entries
[i
].name
));
2287 pci_disable_msix(ha
->pdev
);
2288 clear_bit(AF_MSIX_ENABLED
, &ha
->flags
);
2292 qla4_8xxx_enable_msix(struct scsi_qla_host
*ha
)
2295 struct msix_entry entries
[QLA_MSIX_ENTRIES
];
2296 struct ql4_msix_entry
*qentry
;
2298 for (i
= 0; i
< QLA_MSIX_ENTRIES
; i
++)
2299 entries
[i
].entry
= qla4_8xxx_msix_entries
[i
].entry
;
2301 ret
= pci_enable_msix(ha
->pdev
, entries
, ARRAY_SIZE(entries
));
2303 ql4_printk(KERN_WARNING
, ha
,
2304 "MSI-X: Failed to enable support -- %d/%d\n",
2305 QLA_MSIX_ENTRIES
, ret
);
2308 set_bit(AF_MSIX_ENABLED
, &ha
->flags
);
2310 for (i
= 0; i
< QLA_MSIX_ENTRIES
; i
++) {
2311 qentry
= &ha
->msix_entries
[qla4_8xxx_msix_entries
[i
].index
];
2312 qentry
->msix_vector
= entries
[i
].vector
;
2313 qentry
->msix_entry
= entries
[i
].entry
;
2314 qentry
->have_irq
= 0;
2315 ret
= request_irq(qentry
->msix_vector
,
2316 qla4_8xxx_msix_entries
[i
].handler
, 0,
2317 qla4_8xxx_msix_entries
[i
].name
, ha
);
2319 ql4_printk(KERN_WARNING
, ha
,
2320 "MSI-X: Unable to register handler -- %x/%d.\n",
2321 qla4_8xxx_msix_entries
[i
].index
, ret
);
2322 qla4_8xxx_disable_msix(ha
);
2325 qentry
->have_irq
= 1;
2326 DEBUG2(ql4_printk(KERN_INFO
, ha
, "%s: %s\n",
2327 __func__
, qla4_8xxx_msix_entries
[i
].name
));