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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / parport / parport_pc.c
blob1ea0794b9f183d411d48ebf3ba95a84934c2e712
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/platform_device.h>
58 #include <linux/sysctl.h>
59 #include <linux/io.h>
60 #include <linux/uaccess.h>
61
62 #include <asm/dma.h>
63
64 #include <linux/parport.h>
65 #include <linux/parport_pc.h>
66 #include <linux/via.h>
67 #include <asm/parport.h>
68
69 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71 #ifdef CONFIG_ISA_DMA_API
72 #define HAS_DMA
73 #endif
74
75 /* ECR modes */
76 #define ECR_SPP 00
77 #define ECR_PS2 01
78 #define ECR_PPF 02
79 #define ECR_ECP 03
80 #define ECR_EPP 04
81 #define ECR_VND 05
82 #define ECR_TST 06
83 #define ECR_CNF 07
84 #define ECR_MODE_MASK 0xe0
85 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87 #undef DEBUG
88
89 #ifdef DEBUG
90 #define DPRINTK printk
91 #else
92 #define DPRINTK(stuff...)
93 #endif
94
95
96 #define NR_SUPERIOS 3
97 static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101 } superios[NR_SUPERIOS] = { {0,},};
102
103 static int user_specified;
104 #if defined(CONFIG_PARPORT_PC_SUPERIO) || (defined(CONFIG_PARPORT_1284) && \
105 defined(CONFIG_PARPORT_PC_FIFO))
106 static int verbose_probing;
107 #endif
108 static int pci_registered_parport;
109 static int pnp_registered_parport;
110
111 /* frob_control, but for ECR */
112 static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114 {
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124 }
125
126 static inline void frob_set_mode(struct parport *p, int mode)
127 {
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129 }
130
131 #ifdef CONFIG_PARPORT_PC_FIFO
132 /* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138 static int change_mode(struct parport *p, int m)
139 {
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199 }
200
201 #ifdef CONFIG_PARPORT_1284
202 /* Find FIFO lossage; FIFO is reset */
203 #endif /* IEEE 1284 support */
204 #endif /* FIFO support */
205
206 /*
207 * Clear TIMEOUT BIT in EPP MODE
208 *
209 * This is also used in SPP detection.
210 */
211 static int clear_epp_timeout(struct parport *pb)
212 {
213 unsigned char r;
214
215 if (!(parport_pc_read_status(pb) & 0x01))
216 return 1;
217
218 /* To clear timeout some chips require double read */
219 parport_pc_read_status(pb);
220 r = parport_pc_read_status(pb);
221 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
222 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
223 r = parport_pc_read_status(pb);
224
225 return !(r & 0x01);
226 }
227
228 /*
229 * Access functions.
230 *
231 * Most of these aren't static because they may be used by the
232 * parport_xxx_yyy macros. extern __inline__ versions of several
233 * of these are in parport_pc.h.
234 */
235
236 static void parport_pc_init_state(struct pardevice *dev,
237 struct parport_state *s)
238 {
239 s->u.pc.ctr = 0xc;
240 if (dev->irq_func &&
241 dev->port->irq != PARPORT_IRQ_NONE)
242 /* Set ackIntEn */
243 s->u.pc.ctr |= 0x10;
244
245 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
246 * D.Gruszka VScom */
247 }
248
249 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
250 {
251 const struct parport_pc_private *priv = p->physport->private_data;
252 s->u.pc.ctr = priv->ctr;
253 if (priv->ecr)
254 s->u.pc.ecr = inb(ECONTROL(p));
255 }
256
257 static void parport_pc_restore_state(struct parport *p,
258 struct parport_state *s)
259 {
260 struct parport_pc_private *priv = p->physport->private_data;
261 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
262 outb(c, CONTROL(p));
263 priv->ctr = c;
264 if (priv->ecr)
265 ECR_WRITE(p, s->u.pc.ecr);
266 }
267
268 #ifdef CONFIG_PARPORT_1284
269 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
270 size_t length, int flags)
271 {
272 size_t got = 0;
273
274 if (flags & PARPORT_W91284PIC) {
275 unsigned char status;
276 size_t left = length;
277
278 /* use knowledge about data lines..:
279 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
280 * pError is 1 if there are 16 bytes in the Warp's FIFO
281 */
282 status = inb(STATUS(port));
283
284 while (!(status & 0x08) && got < length) {
285 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
286 /* can grab 16 bytes from warp fifo */
287 if (!((long)buf & 0x03))
288 insl(EPPDATA(port), buf, 4);
289 else
290 insb(EPPDATA(port), buf, 16);
291 buf += 16;
292 got += 16;
293 left -= 16;
294 } else {
295 /* grab single byte from the warp fifo */
296 *((char *)buf) = inb(EPPDATA(port));
297 buf++;
298 got++;
299 left--;
300 }
301 status = inb(STATUS(port));
302 if (status & 0x01) {
303 /* EPP timeout should never occur... */
304 printk(KERN_DEBUG
305 "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
306 clear_epp_timeout(port);
307 }
308 }
309 return got;
310 }
311 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
312 if (!(((long)buf | length) & 0x03))
313 insl(EPPDATA(port), buf, (length >> 2));
314 else
315 insb(EPPDATA(port), buf, length);
316 if (inb(STATUS(port)) & 0x01) {
317 clear_epp_timeout(port);
318 return -EIO;
319 }
320 return length;
321 }
322 for (; got < length; got++) {
323 *((char *)buf) = inb(EPPDATA(port));
324 buf++;
325 if (inb(STATUS(port)) & 0x01) {
326 /* EPP timeout */
327 clear_epp_timeout(port);
328 break;
329 }
330 }
331
332 return got;
333 }
334
335 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
336 size_t length, int flags)
337 {
338 size_t written = 0;
339
340 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
341 if (!(((long)buf | length) & 0x03))
342 outsl(EPPDATA(port), buf, (length >> 2));
343 else
344 outsb(EPPDATA(port), buf, length);
345 if (inb(STATUS(port)) & 0x01) {
346 clear_epp_timeout(port);
347 return -EIO;
348 }
349 return length;
350 }
351 for (; written < length; written++) {
352 outb(*((char *)buf), EPPDATA(port));
353 buf++;
354 if (inb(STATUS(port)) & 0x01) {
355 clear_epp_timeout(port);
356 break;
357 }
358 }
359
360 return written;
361 }
362
363 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
364 size_t length, int flags)
365 {
366 size_t got = 0;
367
368 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
369 insb(EPPADDR(port), buf, length);
370 if (inb(STATUS(port)) & 0x01) {
371 clear_epp_timeout(port);
372 return -EIO;
373 }
374 return length;
375 }
376 for (; got < length; got++) {
377 *((char *)buf) = inb(EPPADDR(port));
378 buf++;
379 if (inb(STATUS(port)) & 0x01) {
380 clear_epp_timeout(port);
381 break;
382 }
383 }
384
385 return got;
386 }
387
388 static size_t parport_pc_epp_write_addr(struct parport *port,
389 const void *buf, size_t length,
390 int flags)
391 {
392 size_t written = 0;
393
394 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
395 outsb(EPPADDR(port), buf, length);
396 if (inb(STATUS(port)) & 0x01) {
397 clear_epp_timeout(port);
398 return -EIO;
399 }
400 return length;
401 }
402 for (; written < length; written++) {
403 outb(*((char *)buf), EPPADDR(port));
404 buf++;
405 if (inb(STATUS(port)) & 0x01) {
406 clear_epp_timeout(port);
407 break;
408 }
409 }
410
411 return written;
412 }
413
414 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
415 size_t length, int flags)
416 {
417 size_t got;
418
419 frob_set_mode(port, ECR_EPP);
420 parport_pc_data_reverse(port);
421 parport_pc_write_control(port, 0x4);
422 got = parport_pc_epp_read_data(port, buf, length, flags);
423 frob_set_mode(port, ECR_PS2);
424
425 return got;
426 }
427
428 static size_t parport_pc_ecpepp_write_data(struct parport *port,
429 const void *buf, size_t length,
430 int flags)
431 {
432 size_t written;
433
434 frob_set_mode(port, ECR_EPP);
435 parport_pc_write_control(port, 0x4);
436 parport_pc_data_forward(port);
437 written = parport_pc_epp_write_data(port, buf, length, flags);
438 frob_set_mode(port, ECR_PS2);
439
440 return written;
441 }
442
443 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
444 size_t length, int flags)
445 {
446 size_t got;
447
448 frob_set_mode(port, ECR_EPP);
449 parport_pc_data_reverse(port);
450 parport_pc_write_control(port, 0x4);
451 got = parport_pc_epp_read_addr(port, buf, length, flags);
452 frob_set_mode(port, ECR_PS2);
453
454 return got;
455 }
456
457 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
458 const void *buf, size_t length,
459 int flags)
460 {
461 size_t written;
462
463 frob_set_mode(port, ECR_EPP);
464 parport_pc_write_control(port, 0x4);
465 parport_pc_data_forward(port);
466 written = parport_pc_epp_write_addr(port, buf, length, flags);
467 frob_set_mode(port, ECR_PS2);
468
469 return written;
470 }
471 #endif /* IEEE 1284 support */
472
473 #ifdef CONFIG_PARPORT_PC_FIFO
474 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
475 const void *buf, size_t length)
476 {
477 int ret = 0;
478 const unsigned char *bufp = buf;
479 size_t left = length;
480 unsigned long expire = jiffies + port->physport->cad->timeout;
481 const int fifo = FIFO(port);
482 int poll_for = 8; /* 80 usecs */
483 const struct parport_pc_private *priv = port->physport->private_data;
484 const int fifo_depth = priv->fifo_depth;
485
486 port = port->physport;
487
488 /* We don't want to be interrupted every character. */
489 parport_pc_disable_irq(port);
490 /* set nErrIntrEn and serviceIntr */
491 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
492
493 /* Forward mode. */
494 parport_pc_data_forward(port); /* Must be in PS2 mode */
495
496 while (left) {
497 unsigned char byte;
498 unsigned char ecrval = inb(ECONTROL(port));
499 int i = 0;
500
501 if (need_resched() && time_before(jiffies, expire))
502 /* Can't yield the port. */
503 schedule();
504
505 /* Anyone else waiting for the port? */
506 if (port->waithead) {
507 printk(KERN_DEBUG "Somebody wants the port\n");
508 break;
509 }
510
511 if (ecrval & 0x02) {
512 /* FIFO is full. Wait for interrupt. */
513
514 /* Clear serviceIntr */
515 ECR_WRITE(port, ecrval & ~(1<<2));
516 false_alarm:
517 ret = parport_wait_event(port, HZ);
518 if (ret < 0)
519 break;
520 ret = 0;
521 if (!time_before(jiffies, expire)) {
522 /* Timed out. */
523 printk(KERN_DEBUG "FIFO write timed out\n");
524 break;
525 }
526 ecrval = inb(ECONTROL(port));
527 if (!(ecrval & (1<<2))) {
528 if (need_resched() &&
529 time_before(jiffies, expire))
530 schedule();
531
532 goto false_alarm;
533 }
534
535 continue;
536 }
537
538 /* Can't fail now. */
539 expire = jiffies + port->cad->timeout;
540
541 poll:
542 if (signal_pending(current))
543 break;
544
545 if (ecrval & 0x01) {
546 /* FIFO is empty. Blast it full. */
547 const int n = left < fifo_depth ? left : fifo_depth;
548 outsb(fifo, bufp, n);
549 bufp += n;
550 left -= n;
551
552 /* Adjust the poll time. */
553 if (i < (poll_for - 2))
554 poll_for--;
555 continue;
556 } else if (i++ < poll_for) {
557 udelay(10);
558 ecrval = inb(ECONTROL(port));
559 goto poll;
560 }
561
562 /* Half-full(call me an optimist) */
563 byte = *bufp++;
564 outb(byte, fifo);
565 left--;
566 }
567 dump_parport_state("leave fifo_write_block_pio", port);
568 return length - left;
569 }
570
571 #ifdef HAS_DMA
572 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
573 const void *buf, size_t length)
574 {
575 int ret = 0;
576 unsigned long dmaflag;
577 size_t left = length;
578 const struct parport_pc_private *priv = port->physport->private_data;
579 struct device *dev = port->physport->dev;
580 dma_addr_t dma_addr, dma_handle;
581 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
582 unsigned long start = (unsigned long) buf;
583 unsigned long end = (unsigned long) buf + length - 1;
584
585 dump_parport_state("enter fifo_write_block_dma", port);
586 if (end < MAX_DMA_ADDRESS) {
587 /* If it would cross a 64k boundary, cap it at the end. */
588 if ((start ^ end) & ~0xffffUL)
589 maxlen = 0x10000 - (start & 0xffff);
590
591 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
592 DMA_TO_DEVICE);
593 } else {
594 /* above 16 MB we use a bounce buffer as ISA-DMA
595 is not possible */
596 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
597 dma_addr = priv->dma_handle;
598 dma_handle = 0;
599 }
600
601 port = port->physport;
602
603 /* We don't want to be interrupted every character. */
604 parport_pc_disable_irq(port);
605 /* set nErrIntrEn and serviceIntr */
606 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
607
608 /* Forward mode. */
609 parport_pc_data_forward(port); /* Must be in PS2 mode */
610
611 while (left) {
612 unsigned long expire = jiffies + port->physport->cad->timeout;
613
614 size_t count = left;
615
616 if (count > maxlen)
617 count = maxlen;
618
619 if (!dma_handle) /* bounce buffer ! */
620 memcpy(priv->dma_buf, buf, count);
621
622 dmaflag = claim_dma_lock();
623 disable_dma(port->dma);
624 clear_dma_ff(port->dma);
625 set_dma_mode(port->dma, DMA_MODE_WRITE);
626 set_dma_addr(port->dma, dma_addr);
627 set_dma_count(port->dma, count);
628
629 /* Set DMA mode */
630 frob_econtrol(port, 1<<3, 1<<3);
631
632 /* Clear serviceIntr */
633 frob_econtrol(port, 1<<2, 0);
634
635 enable_dma(port->dma);
636 release_dma_lock(dmaflag);
637
638 /* assume DMA will be successful */
639 left -= count;
640 buf += count;
641 if (dma_handle)
642 dma_addr += count;
643
644 /* Wait for interrupt. */
645 false_alarm:
646 ret = parport_wait_event(port, HZ);
647 if (ret < 0)
648 break;
649 ret = 0;
650 if (!time_before(jiffies, expire)) {
651 /* Timed out. */
652 printk(KERN_DEBUG "DMA write timed out\n");
653 break;
654 }
655 /* Is serviceIntr set? */
656 if (!(inb(ECONTROL(port)) & (1<<2))) {
657 cond_resched();
658
659 goto false_alarm;
660 }
661
662 dmaflag = claim_dma_lock();
663 disable_dma(port->dma);
664 clear_dma_ff(port->dma);
665 count = get_dma_residue(port->dma);
666 release_dma_lock(dmaflag);
667
668 cond_resched(); /* Can't yield the port. */
669
670 /* Anyone else waiting for the port? */
671 if (port->waithead) {
672 printk(KERN_DEBUG "Somebody wants the port\n");
673 break;
674 }
675
676 /* update for possible DMA residue ! */
677 buf -= count;
678 left += count;
679 if (dma_handle)
680 dma_addr -= count;
681 }
682
683 /* Maybe got here through break, so adjust for DMA residue! */
684 dmaflag = claim_dma_lock();
685 disable_dma(port->dma);
686 clear_dma_ff(port->dma);
687 left += get_dma_residue(port->dma);
688 release_dma_lock(dmaflag);
689
690 /* Turn off DMA mode */
691 frob_econtrol(port, 1<<3, 0);
692
693 if (dma_handle)
694 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
695
696 dump_parport_state("leave fifo_write_block_dma", port);
697 return length - left;
698 }
699 #endif
700
701 static inline size_t parport_pc_fifo_write_block(struct parport *port,
702 const void *buf, size_t length)
703 {
704 #ifdef HAS_DMA
705 if (port->dma != PARPORT_DMA_NONE)
706 return parport_pc_fifo_write_block_dma(port, buf, length);
707 #endif
708 return parport_pc_fifo_write_block_pio(port, buf, length);
709 }
710
711 /* Parallel Port FIFO mode (ECP chipsets) */
712 static size_t parport_pc_compat_write_block_pio(struct parport *port,
713 const void *buf, size_t length,
714 int flags)
715 {
716 size_t written;
717 int r;
718 unsigned long expire;
719 const struct parport_pc_private *priv = port->physport->private_data;
720
721 /* Special case: a timeout of zero means we cannot call schedule().
722 * Also if O_NONBLOCK is set then use the default implementation. */
723 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
724 return parport_ieee1284_write_compat(port, buf,
725 length, flags);
726
727 /* Set up parallel port FIFO mode.*/
728 parport_pc_data_forward(port); /* Must be in PS2 mode */
729 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
730 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
731 if (r)
732 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
733 port->name);
734
735 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
736
737 /* Write the data to the FIFO. */
738 written = parport_pc_fifo_write_block(port, buf, length);
739
740 /* Finish up. */
741 /* For some hardware we don't want to touch the mode until
742 * the FIFO is empty, so allow 4 seconds for each position
743 * in the fifo.
744 */
745 expire = jiffies + (priv->fifo_depth * HZ * 4);
746 do {
747 /* Wait for the FIFO to empty */
748 r = change_mode(port, ECR_PS2);
749 if (r != -EBUSY)
750 break;
751 } while (time_before(jiffies, expire));
752 if (r == -EBUSY) {
753
754 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
755
756 /* Prevent further data transfer. */
757 frob_set_mode(port, ECR_TST);
758
759 /* Adjust for the contents of the FIFO. */
760 for (written -= priv->fifo_depth; ; written++) {
761 if (inb(ECONTROL(port)) & 0x2) {
762 /* Full up. */
763 break;
764 }
765 outb(0, FIFO(port));
766 }
767
768 /* Reset the FIFO and return to PS2 mode. */
769 frob_set_mode(port, ECR_PS2);
770 }
771
772 r = parport_wait_peripheral(port,
773 PARPORT_STATUS_BUSY,
774 PARPORT_STATUS_BUSY);
775 if (r)
776 printk(KERN_DEBUG
777 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
778 port->name, r);
779
780 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
781
782 return written;
783 }
784
785 /* ECP */
786 #ifdef CONFIG_PARPORT_1284
787 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
788 const void *buf, size_t length,
789 int flags)
790 {
791 size_t written;
792 int r;
793 unsigned long expire;
794 const struct parport_pc_private *priv = port->physport->private_data;
795
796 /* Special case: a timeout of zero means we cannot call schedule().
797 * Also if O_NONBLOCK is set then use the default implementation. */
798 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
799 return parport_ieee1284_ecp_write_data(port, buf,
800 length, flags);
801
802 /* Switch to forward mode if necessary. */
803 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
804 /* Event 47: Set nInit high. */
805 parport_frob_control(port,
806 PARPORT_CONTROL_INIT
807 | PARPORT_CONTROL_AUTOFD,
808 PARPORT_CONTROL_INIT
809 | PARPORT_CONTROL_AUTOFD);
810
811 /* Event 49: PError goes high. */
812 r = parport_wait_peripheral(port,
813 PARPORT_STATUS_PAPEROUT,
814 PARPORT_STATUS_PAPEROUT);
815 if (r) {
816 printk(KERN_DEBUG "%s: PError timeout (%d) "
817 "in ecp_write_block_pio\n", port->name, r);
818 }
819 }
820
821 /* Set up ECP parallel port mode.*/
822 parport_pc_data_forward(port); /* Must be in PS2 mode */
823 parport_pc_frob_control(port,
824 PARPORT_CONTROL_STROBE |
825 PARPORT_CONTROL_AUTOFD,
826 0);
827 r = change_mode(port, ECR_ECP); /* ECP FIFO */
828 if (r)
829 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
830 port->name);
831 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
832
833 /* Write the data to the FIFO. */
834 written = parport_pc_fifo_write_block(port, buf, length);
835
836 /* Finish up. */
837 /* For some hardware we don't want to touch the mode until
838 * the FIFO is empty, so allow 4 seconds for each position
839 * in the fifo.
840 */
841 expire = jiffies + (priv->fifo_depth * (HZ * 4));
842 do {
843 /* Wait for the FIFO to empty */
844 r = change_mode(port, ECR_PS2);
845 if (r != -EBUSY)
846 break;
847 } while (time_before(jiffies, expire));
848 if (r == -EBUSY) {
849
850 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
851
852 /* Prevent further data transfer. */
853 frob_set_mode(port, ECR_TST);
854
855 /* Adjust for the contents of the FIFO. */
856 for (written -= priv->fifo_depth; ; written++) {
857 if (inb(ECONTROL(port)) & 0x2) {
858 /* Full up. */
859 break;
860 }
861 outb(0, FIFO(port));
862 }
863
864 /* Reset the FIFO and return to PS2 mode. */
865 frob_set_mode(port, ECR_PS2);
866
867 /* Host transfer recovery. */
868 parport_pc_data_reverse(port); /* Must be in PS2 mode */
869 udelay(5);
870 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
871 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
872 if (r)
873 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
874 "in ecp_write_block_pio\n", port->name, r);
875
876 parport_frob_control(port,
877 PARPORT_CONTROL_INIT,
878 PARPORT_CONTROL_INIT);
879 r = parport_wait_peripheral(port,
880 PARPORT_STATUS_PAPEROUT,
881 PARPORT_STATUS_PAPEROUT);
882 if (r)
883 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
884 "in ecp_write_block_pio\n", port->name, r);
885 }
886
887 r = parport_wait_peripheral(port,
888 PARPORT_STATUS_BUSY,
889 PARPORT_STATUS_BUSY);
890 if (r)
891 printk(KERN_DEBUG
892 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
893 port->name, r);
894
895 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
896
897 return written;
898 }
899
900 #endif /* IEEE 1284 support */
901 #endif /* Allowed to use FIFO/DMA */
902
903
904 /*
905 * ******************************************
906 * INITIALISATION AND MODULE STUFF BELOW HERE
907 * ******************************************
908 */
909
910 /* GCC is not inlining extern inline function later overwriten to non-inline,
911 so we use outlined_ variants here. */
912 static const struct parport_operations parport_pc_ops = {
913 .write_data = parport_pc_write_data,
914 .read_data = parport_pc_read_data,
915
916 .write_control = parport_pc_write_control,
917 .read_control = parport_pc_read_control,
918 .frob_control = parport_pc_frob_control,
919
920 .read_status = parport_pc_read_status,
921
922 .enable_irq = parport_pc_enable_irq,
923 .disable_irq = parport_pc_disable_irq,
924
925 .data_forward = parport_pc_data_forward,
926 .data_reverse = parport_pc_data_reverse,
927
928 .init_state = parport_pc_init_state,
929 .save_state = parport_pc_save_state,
930 .restore_state = parport_pc_restore_state,
931
932 .epp_write_data = parport_ieee1284_epp_write_data,
933 .epp_read_data = parport_ieee1284_epp_read_data,
934 .epp_write_addr = parport_ieee1284_epp_write_addr,
935 .epp_read_addr = parport_ieee1284_epp_read_addr,
936
937 .ecp_write_data = parport_ieee1284_ecp_write_data,
938 .ecp_read_data = parport_ieee1284_ecp_read_data,
939 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
940
941 .compat_write_data = parport_ieee1284_write_compat,
942 .nibble_read_data = parport_ieee1284_read_nibble,
943 .byte_read_data = parport_ieee1284_read_byte,
944
945 .owner = THIS_MODULE,
946 };
947
948 #ifdef CONFIG_PARPORT_PC_SUPERIO
949
950 static struct superio_struct *find_free_superio(void)
951 {
952 int i;
953 for (i = 0; i < NR_SUPERIOS; i++)
954 if (superios[i].io == 0)
955 return &superios[i];
956 return NULL;
957 }
958
959
960 /* Super-IO chipset detection, Winbond, SMSC */
961 static void __devinit show_parconfig_smsc37c669(int io, int key)
962 {
963 int cr1, cr4, cra, cr23, cr26, cr27;
964 struct superio_struct *s;
965
966 static const char *const modes[] = {
967 "SPP and Bidirectional (PS/2)",
968 "EPP and SPP",
969 "ECP",
970 "ECP and EPP" };
971
972 outb(key, io);
973 outb(key, io);
974 outb(1, io);
975 cr1 = inb(io + 1);
976 outb(4, io);
977 cr4 = inb(io + 1);
978 outb(0x0a, io);
979 cra = inb(io + 1);
980 outb(0x23, io);
981 cr23 = inb(io + 1);
982 outb(0x26, io);
983 cr26 = inb(io + 1);
984 outb(0x27, io);
985 cr27 = inb(io + 1);
986 outb(0xaa, io);
987
988 if (verbose_probing) {
989 printk(KERN_INFO
990 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
991 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
992 cr1, cr4, cra, cr23, cr26, cr27);
993
994 /* The documentation calls DMA and IRQ-Lines by letters, so
995 the board maker can/will wire them
996 appropriately/randomly... G=reserved H=IDE-irq, */
997 printk(KERN_INFO
998 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
999 cr23 * 4,
1000 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
1001 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
1002 cra & 0x0f);
1003 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1004 (cr23 * 4 >= 0x100) ? "yes" : "no",
1005 (cr1 & 4) ? "yes" : "no");
1006 printk(KERN_INFO
1007 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1008 (cr1 & 0x08) ? "Standard mode only (SPP)"
1009 : modes[cr4 & 0x03],
1010 (cr4 & 0x40) ? "1.7" : "1.9");
1011 }
1012
1013 /* Heuristics ! BIOS setup for this mainboard device limits
1014 the choices to standard settings, i.e. io-address and IRQ
1015 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1016 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1017 if (cr23 * 4 >= 0x100) { /* if active */
1018 s = find_free_superio();
1019 if (s == NULL)
1020 printk(KERN_INFO "Super-IO: too many chips!\n");
1021 else {
1022 int d;
1023 switch (cr23 * 4) {
1024 case 0x3bc:
1025 s->io = 0x3bc;
1026 s->irq = 7;
1027 break;
1028 case 0x378:
1029 s->io = 0x378;
1030 s->irq = 7;
1031 break;
1032 case 0x278:
1033 s->io = 0x278;
1034 s->irq = 5;
1035 }
1036 d = (cr26 & 0x0f);
1037 if (d == 1 || d == 3)
1038 s->dma = d;
1039 else
1040 s->dma = PARPORT_DMA_NONE;
1041 }
1042 }
1043 }
1044
1045
1046 static void __devinit show_parconfig_winbond(int io, int key)
1047 {
1048 int cr30, cr60, cr61, cr70, cr74, crf0;
1049 struct superio_struct *s;
1050 static const char *const modes[] = {
1051 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1052 "EPP-1.9 and SPP",
1053 "ECP",
1054 "ECP and EPP-1.9",
1055 "Standard (SPP)",
1056 "EPP-1.7 and SPP", /* 5 */
1057 "undefined!",
1058 "ECP and EPP-1.7" };
1059 static char *const irqtypes[] = {
1060 "pulsed low, high-Z",
1061 "follows nACK" };
1062
1063 /* The registers are called compatible-PnP because the
1064 register layout is modelled after ISA-PnP, the access
1065 method is just another ... */
1066 outb(key, io);
1067 outb(key, io);
1068 outb(0x07, io); /* Register 7: Select Logical Device */
1069 outb(0x01, io + 1); /* LD1 is Parallel Port */
1070 outb(0x30, io);
1071 cr30 = inb(io + 1);
1072 outb(0x60, io);
1073 cr60 = inb(io + 1);
1074 outb(0x61, io);
1075 cr61 = inb(io + 1);
1076 outb(0x70, io);
1077 cr70 = inb(io + 1);
1078 outb(0x74, io);
1079 cr74 = inb(io + 1);
1080 outb(0xf0, io);
1081 crf0 = inb(io + 1);
1082 outb(0xaa, io);
1083
1084 if (verbose_probing) {
1085 printk(KERN_INFO
1086 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1087 cr30, cr60, cr61, cr70, cr74, crf0);
1088 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1089 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1090 if ((cr74 & 0x07) > 3)
1091 printk("dma=none\n");
1092 else
1093 printk("dma=%d\n", cr74 & 0x07);
1094 printk(KERN_INFO
1095 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1096 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1097 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1098 modes[crf0 & 0x07]);
1099 }
1100
1101 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1102 s = find_free_superio();
1103 if (s == NULL)
1104 printk(KERN_INFO "Super-IO: too many chips!\n");
1105 else {
1106 s->io = (cr60 << 8) | cr61;
1107 s->irq = cr70 & 0x0f;
1108 s->dma = (((cr74 & 0x07) > 3) ?
1109 PARPORT_DMA_NONE : (cr74 & 0x07));
1110 }
1111 }
1112 }
1113
1114 static void __devinit decode_winbond(int efer, int key, int devid,
1115 int devrev, int oldid)
1116 {
1117 const char *type = "unknown";
1118 int id, progif = 2;
1119
1120 if (devid == devrev)
1121 /* simple heuristics, we happened to read some
1122 non-winbond register */
1123 return;
1124
1125 id = (devid << 8) | devrev;
1126
1127 /* Values are from public data sheets pdf files, I can just
1128 confirm 83977TF is correct :-) */
1129 if (id == 0x9771)
1130 type = "83977F/AF";
1131 else if (id == 0x9773)
1132 type = "83977TF / SMSC 97w33x/97w34x";
1133 else if (id == 0x9774)
1134 type = "83977ATF";
1135 else if ((id & ~0x0f) == 0x5270)
1136 type = "83977CTF / SMSC 97w36x";
1137 else if ((id & ~0x0f) == 0x52f0)
1138 type = "83977EF / SMSC 97w35x";
1139 else if ((id & ~0x0f) == 0x5210)
1140 type = "83627";
1141 else if ((id & ~0x0f) == 0x6010)
1142 type = "83697HF";
1143 else if ((oldid & 0x0f) == 0x0a) {
1144 type = "83877F";
1145 progif = 1;
1146 } else if ((oldid & 0x0f) == 0x0b) {
1147 type = "83877AF";
1148 progif = 1;
1149 } else if ((oldid & 0x0f) == 0x0c) {
1150 type = "83877TF";
1151 progif = 1;
1152 } else if ((oldid & 0x0f) == 0x0d) {
1153 type = "83877ATF";
1154 progif = 1;
1155 } else
1156 progif = 0;
1157
1158 if (verbose_probing)
1159 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1160 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1161 efer, key, devid, devrev, oldid, type);
1162
1163 if (progif == 2)
1164 show_parconfig_winbond(efer, key);
1165 }
1166
1167 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1168 {
1169 const char *type = "unknown";
1170 void (*func)(int io, int key);
1171 int id;
1172
1173 if (devid == devrev)
1174 /* simple heuristics, we happened to read some
1175 non-smsc register */
1176 return;
1177
1178 func = NULL;
1179 id = (devid << 8) | devrev;
1180
1181 if (id == 0x0302) {
1182 type = "37c669";
1183 func = show_parconfig_smsc37c669;
1184 } else if (id == 0x6582)
1185 type = "37c665IR";
1186 else if (devid == 0x65)
1187 type = "37c665GT";
1188 else if (devid == 0x66)
1189 type = "37c666GT";
1190
1191 if (verbose_probing)
1192 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1193 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1194 efer, key, devid, devrev, type);
1195
1196 if (func)
1197 func(efer, key);
1198 }
1199
1200
1201 static void __devinit winbond_check(int io, int key)
1202 {
1203 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1204
1205 if (!request_region(io, 3, __func__))
1206 return;
1207
1208 origval = inb(io); /* Save original value */
1209
1210 /* First probe without key */
1211 outb(0x20, io);
1212 x_devid = inb(io + 1);
1213 outb(0x21, io);
1214 x_devrev = inb(io + 1);
1215 outb(0x09, io);
1216 x_oldid = inb(io + 1);
1217
1218 outb(key, io);
1219 outb(key, io); /* Write Magic Sequence to EFER, extended
1220 funtion enable register */
1221 outb(0x20, io); /* Write EFIR, extended function index register */
1222 devid = inb(io + 1); /* Read EFDR, extended function data register */
1223 outb(0x21, io);
1224 devrev = inb(io + 1);
1225 outb(0x09, io);
1226 oldid = inb(io + 1);
1227 outb(0xaa, io); /* Magic Seal */
1228
1229 outb(origval, io); /* in case we poked some entirely different hardware */
1230
1231 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1232 goto out; /* protection against false positives */
1233
1234 decode_winbond(io, key, devid, devrev, oldid);
1235 out:
1236 release_region(io, 3);
1237 }
1238
1239 static void __devinit winbond_check2(int io, int key)
1240 {
1241 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1242
1243 if (!request_region(io, 3, __func__))
1244 return;
1245
1246 origval[0] = inb(io); /* Save original values */
1247 origval[1] = inb(io + 1);
1248 origval[2] = inb(io + 2);
1249
1250 /* First probe without the key */
1251 outb(0x20, io + 2);
1252 x_devid = inb(io + 2);
1253 outb(0x21, io + 1);
1254 x_devrev = inb(io + 2);
1255 outb(0x09, io + 1);
1256 x_oldid = inb(io + 2);
1257
1258 outb(key, io); /* Write Magic Byte to EFER, extended
1259 funtion enable register */
1260 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1261 devid = inb(io + 2); /* Read EFDR, extended function data register */
1262 outb(0x21, io + 1);
1263 devrev = inb(io + 2);
1264 outb(0x09, io + 1);
1265 oldid = inb(io + 2);
1266 outb(0xaa, io); /* Magic Seal */
1267
1268 outb(origval[0], io); /* in case we poked some entirely different hardware */
1269 outb(origval[1], io + 1);
1270 outb(origval[2], io + 2);
1271
1272 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1273 goto out; /* protection against false positives */
1274
1275 decode_winbond(io, key, devid, devrev, oldid);
1276 out:
1277 release_region(io, 3);
1278 }
1279
1280 static void __devinit smsc_check(int io, int key)
1281 {
1282 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1283
1284 if (!request_region(io, 3, __func__))
1285 return;
1286
1287 origval = inb(io); /* Save original value */
1288
1289 /* First probe without the key */
1290 outb(0x0d, io);
1291 x_oldid = inb(io + 1);
1292 outb(0x0e, io);
1293 x_oldrev = inb(io + 1);
1294 outb(0x20, io);
1295 x_id = inb(io + 1);
1296 outb(0x21, io);
1297 x_rev = inb(io + 1);
1298
1299 outb(key, io);
1300 outb(key, io); /* Write Magic Sequence to EFER, extended
1301 funtion enable register */
1302 outb(0x0d, io); /* Write EFIR, extended function index register */
1303 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1304 outb(0x0e, io);
1305 oldrev = inb(io + 1);
1306 outb(0x20, io);
1307 id = inb(io + 1);
1308 outb(0x21, io);
1309 rev = inb(io + 1);
1310 outb(0xaa, io); /* Magic Seal */
1311
1312 outb(origval, io); /* in case we poked some entirely different hardware */
1313
1314 if (x_id == id && x_oldrev == oldrev &&
1315 x_oldid == oldid && x_rev == rev)
1316 goto out; /* protection against false positives */
1317
1318 decode_smsc(io, key, oldid, oldrev);
1319 out:
1320 release_region(io, 3);
1321 }
1322
1323
1324 static void __devinit detect_and_report_winbond(void)
1325 {
1326 if (verbose_probing)
1327 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1328 winbond_check(0x3f0, 0x87);
1329 winbond_check(0x370, 0x87);
1330 winbond_check(0x2e , 0x87);
1331 winbond_check(0x4e , 0x87);
1332 winbond_check(0x3f0, 0x86);
1333 winbond_check2(0x250, 0x88);
1334 winbond_check2(0x250, 0x89);
1335 }
1336
1337 static void __devinit detect_and_report_smsc(void)
1338 {
1339 if (verbose_probing)
1340 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1341 smsc_check(0x3f0, 0x55);
1342 smsc_check(0x370, 0x55);
1343 smsc_check(0x3f0, 0x44);
1344 smsc_check(0x370, 0x44);
1345 }
1346
1347 static void __devinit detect_and_report_it87(void)
1348 {
1349 u16 dev;
1350 u8 origval, r;
1351 if (verbose_probing)
1352 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1353 if (!request_region(0x2e, 2, __func__))
1354 return;
1355 origval = inb(0x2e); /* Save original value */
1356 outb(0x87, 0x2e);
1357 outb(0x01, 0x2e);
1358 outb(0x55, 0x2e);
1359 outb(0x55, 0x2e);
1360 outb(0x20, 0x2e);
1361 dev = inb(0x2f) << 8;
1362 outb(0x21, 0x2e);
1363 dev |= inb(0x2f);
1364 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1365 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1366 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1367 outb(0x07, 0x2E); /* Parallel Port */
1368 outb(0x03, 0x2F);
1369 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1370 r = inb(0x2f);
1371 outb(0xF0, 0x2E);
1372 outb(r | 8, 0x2F);
1373 outb(0x02, 0x2E); /* Lock */
1374 outb(0x02, 0x2F);
1375 } else {
1376 outb(origval, 0x2e); /* Oops, sorry to disturb */
1377 }
1378 release_region(0x2e, 2);
1379 }
1380 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1381
1382 static struct superio_struct *find_superio(struct parport *p)
1383 {
1384 int i;
1385 for (i = 0; i < NR_SUPERIOS; i++)
1386 if (superios[i].io != p->base)
1387 return &superios[i];
1388 return NULL;
1389 }
1390
1391 static int get_superio_dma(struct parport *p)
1392 {
1393 struct superio_struct *s = find_superio(p);
1394 if (s)
1395 return s->dma;
1396 return PARPORT_DMA_NONE;
1397 }
1398
1399 static int get_superio_irq(struct parport *p)
1400 {
1401 struct superio_struct *s = find_superio(p);
1402 if (s)
1403 return s->irq;
1404 return PARPORT_IRQ_NONE;
1405 }
1406
1407
1408 /* --- Mode detection ------------------------------------- */
1409
1410 /*
1411 * Checks for port existence, all ports support SPP MODE
1412 * Returns:
1413 * 0 : No parallel port at this address
1414 * PARPORT_MODE_PCSPP : SPP port detected
1415 * (if the user specified an ioport himself,
1416 * this shall always be the case!)
1417 *
1418 */
1419 static int parport_SPP_supported(struct parport *pb)
1420 {
1421 unsigned char r, w;
1422
1423 /*
1424 * first clear an eventually pending EPP timeout
1425 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1426 * that does not even respond to SPP cycles if an EPP
1427 * timeout is pending
1428 */
1429 clear_epp_timeout(pb);
1430
1431 /* Do a simple read-write test to make sure the port exists. */
1432 w = 0xc;
1433 outb(w, CONTROL(pb));
1434
1435 /* Is there a control register that we can read from? Some
1436 * ports don't allow reads, so read_control just returns a
1437 * software copy. Some ports _do_ allow reads, so bypass the
1438 * software copy here. In addition, some bits aren't
1439 * writable. */
1440 r = inb(CONTROL(pb));
1441 if ((r & 0xf) == w) {
1442 w = 0xe;
1443 outb(w, CONTROL(pb));
1444 r = inb(CONTROL(pb));
1445 outb(0xc, CONTROL(pb));
1446 if ((r & 0xf) == w)
1447 return PARPORT_MODE_PCSPP;
1448 }
1449
1450 if (user_specified)
1451 /* That didn't work, but the user thinks there's a
1452 * port here. */
1453 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1454 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1455
1456 /* Try the data register. The data lines aren't tri-stated at
1457 * this stage, so we expect back what we wrote. */
1458 w = 0xaa;
1459 parport_pc_write_data(pb, w);
1460 r = parport_pc_read_data(pb);
1461 if (r == w) {
1462 w = 0x55;
1463 parport_pc_write_data(pb, w);
1464 r = parport_pc_read_data(pb);
1465 if (r == w)
1466 return PARPORT_MODE_PCSPP;
1467 }
1468
1469 if (user_specified) {
1470 /* Didn't work, but the user is convinced this is the
1471 * place. */
1472 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1473 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1474 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1475 "but there is probably no parallel port there!\n",
1476 pb->base);
1477 }
1478
1479 /* It's possible that we can't read the control register or
1480 * the data register. In that case just believe the user. */
1481 if (user_specified)
1482 return PARPORT_MODE_PCSPP;
1483
1484 return 0;
1485 }
1486
1487 /* Check for ECR
1488 *
1489 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1490 * on these cards actually accesses the CTR.
1491 *
1492 * Modern cards don't do this but reading from ECR will return 0xff
1493 * regardless of what is written here if the card does NOT support
1494 * ECP.
1495 *
1496 * We first check to see if ECR is the same as CTR. If not, the low
1497 * two bits of ECR aren't writable, so we check by writing ECR and
1498 * reading it back to see if it's what we expect.
1499 */
1500 static int parport_ECR_present(struct parport *pb)
1501 {
1502 struct parport_pc_private *priv = pb->private_data;
1503 unsigned char r = 0xc;
1504
1505 outb(r, CONTROL(pb));
1506 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1507 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1508
1509 r = inb(CONTROL(pb));
1510 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1511 goto no_reg; /* Sure that no ECR register exists */
1512 }
1513
1514 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1515 goto no_reg;
1516
1517 ECR_WRITE(pb, 0x34);
1518 if (inb(ECONTROL(pb)) != 0x35)
1519 goto no_reg;
1520
1521 priv->ecr = 1;
1522 outb(0xc, CONTROL(pb));
1523
1524 /* Go to mode 000 */
1525 frob_set_mode(pb, ECR_SPP);
1526
1527 return 1;
1528
1529 no_reg:
1530 outb(0xc, CONTROL(pb));
1531 return 0;
1532 }
1533
1534 #ifdef CONFIG_PARPORT_1284
1535 /* Detect PS/2 support.
1536 *
1537 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1538 * allows us to read data from the data lines. In theory we would get back
1539 * 0xff but any peripheral attached to the port may drag some or all of the
1540 * lines down to zero. So if we get back anything that isn't the contents
1541 * of the data register we deem PS/2 support to be present.
1542 *
1543 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1544 * drivers, but an external peripheral with sufficiently beefy drivers of
1545 * its own can overpower them and assert its own levels onto the bus, from
1546 * where they can then be read back as normal. Ports with this property
1547 * and the right type of device attached are likely to fail the SPP test,
1548 * (as they will appear to have stuck bits) and so the fact that they might
1549 * be misdetected here is rather academic.
1550 */
1551
1552 static int parport_PS2_supported(struct parport *pb)
1553 {
1554 int ok = 0;
1555
1556 clear_epp_timeout(pb);
1557
1558 /* try to tri-state the buffer */
1559 parport_pc_data_reverse(pb);
1560
1561 parport_pc_write_data(pb, 0x55);
1562 if (parport_pc_read_data(pb) != 0x55)
1563 ok++;
1564
1565 parport_pc_write_data(pb, 0xaa);
1566 if (parport_pc_read_data(pb) != 0xaa)
1567 ok++;
1568
1569 /* cancel input mode */
1570 parport_pc_data_forward(pb);
1571
1572 if (ok) {
1573 pb->modes |= PARPORT_MODE_TRISTATE;
1574 } else {
1575 struct parport_pc_private *priv = pb->private_data;
1576 priv->ctr_writable &= ~0x20;
1577 }
1578
1579 return ok;
1580 }
1581
1582 #ifdef CONFIG_PARPORT_PC_FIFO
1583 static int parport_ECP_supported(struct parport *pb)
1584 {
1585 int i;
1586 int config, configb;
1587 int pword;
1588 struct parport_pc_private *priv = pb->private_data;
1589 /* Translate ECP intrLine to ISA irq value */
1590 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1591
1592 /* If there is no ECR, we have no hope of supporting ECP. */
1593 if (!priv->ecr)
1594 return 0;
1595
1596 /* Find out FIFO depth */
1597 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1598 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1599 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1600 outb(0xaa, FIFO(pb));
1601
1602 /*
1603 * Using LGS chipset it uses ECR register, but
1604 * it doesn't support ECP or FIFO MODE
1605 */
1606 if (i == 1024) {
1607 ECR_WRITE(pb, ECR_SPP << 5);
1608 return 0;
1609 }
1610
1611 priv->fifo_depth = i;
1612 if (verbose_probing)
1613 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1614
1615 /* Find out writeIntrThreshold */
1616 frob_econtrol(pb, 1<<2, 1<<2);
1617 frob_econtrol(pb, 1<<2, 0);
1618 for (i = 1; i <= priv->fifo_depth; i++) {
1619 inb(FIFO(pb));
1620 udelay(50);
1621 if (inb(ECONTROL(pb)) & (1<<2))
1622 break;
1623 }
1624
1625 if (i <= priv->fifo_depth) {
1626 if (verbose_probing)
1627 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1628 pb->base, i);
1629 } else
1630 /* Number of bytes we know we can write if we get an
1631 interrupt. */
1632 i = 0;
1633
1634 priv->writeIntrThreshold = i;
1635
1636 /* Find out readIntrThreshold */
1637 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1638 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1639 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1640 frob_econtrol(pb, 1<<2, 1<<2);
1641 frob_econtrol(pb, 1<<2, 0);
1642 for (i = 1; i <= priv->fifo_depth; i++) {
1643 outb(0xaa, FIFO(pb));
1644 if (inb(ECONTROL(pb)) & (1<<2))
1645 break;
1646 }
1647
1648 if (i <= priv->fifo_depth) {
1649 if (verbose_probing)
1650 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1651 pb->base, i);
1652 } else
1653 /* Number of bytes we can read if we get an interrupt. */
1654 i = 0;
1655
1656 priv->readIntrThreshold = i;
1657
1658 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1659 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1660 config = inb(CONFIGA(pb));
1661 pword = (config >> 4) & 0x7;
1662 switch (pword) {
1663 case 0:
1664 pword = 2;
1665 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1666 pb->base);
1667 break;
1668 case 2:
1669 pword = 4;
1670 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1671 pb->base);
1672 break;
1673 default:
1674 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1675 pb->base);
1676 /* Assume 1 */
1677 case 1:
1678 pword = 1;
1679 }
1680 priv->pword = pword;
1681
1682 if (verbose_probing) {
1683 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1684 pb->base, 8 * pword);
1685
1686 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1687 config & 0x80 ? "Level" : "Pulses");
1688
1689 configb = inb(CONFIGB(pb));
1690 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1691 pb->base, config, configb);
1692 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1693 if ((configb >> 3) & 0x07)
1694 printk("%d", intrline[(configb >> 3) & 0x07]);
1695 else
1696 printk("<none or set by other means>");
1697 printk(" dma=");
1698 if ((configb & 0x03) == 0x00)
1699 printk("<none or set by other means>\n");
1700 else
1701 printk("%d\n", configb & 0x07);
1702 }
1703
1704 /* Go back to mode 000 */
1705 frob_set_mode(pb, ECR_SPP);
1706
1707 return 1;
1708 }
1709 #endif
1710
1711 static int parport_ECPPS2_supported(struct parport *pb)
1712 {
1713 const struct parport_pc_private *priv = pb->private_data;
1714 int result;
1715 unsigned char oecr;
1716
1717 if (!priv->ecr)
1718 return 0;
1719
1720 oecr = inb(ECONTROL(pb));
1721 ECR_WRITE(pb, ECR_PS2 << 5);
1722 result = parport_PS2_supported(pb);
1723 ECR_WRITE(pb, oecr);
1724 return result;
1725 }
1726
1727 /* EPP mode detection */
1728
1729 static int parport_EPP_supported(struct parport *pb)
1730 {
1731 const struct parport_pc_private *priv = pb->private_data;
1732
1733 /*
1734 * Theory:
1735 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1736 * when EPP is possible and is set high when an EPP timeout
1737 * occurs (EPP uses the HALT line to stop the CPU while it does
1738 * the byte transfer, an EPP timeout occurs if the attached
1739 * device fails to respond after 10 micro seconds).
1740 *
1741 * This bit is cleared by either reading it (National Semi)
1742 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1743 * This bit is always high in non EPP modes.
1744 */
1745
1746 /* If EPP timeout bit clear then EPP available */
1747 if (!clear_epp_timeout(pb))
1748 return 0; /* No way to clear timeout */
1749
1750 /* Check for Intel bug. */
1751 if (priv->ecr) {
1752 unsigned char i;
1753 for (i = 0x00; i < 0x80; i += 0x20) {
1754 ECR_WRITE(pb, i);
1755 if (clear_epp_timeout(pb)) {
1756 /* Phony EPP in ECP. */
1757 return 0;
1758 }
1759 }
1760 }
1761
1762 pb->modes |= PARPORT_MODE_EPP;
1763
1764 /* Set up access functions to use EPP hardware. */
1765 pb->ops->epp_read_data = parport_pc_epp_read_data;
1766 pb->ops->epp_write_data = parport_pc_epp_write_data;
1767 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1768 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1769
1770 return 1;
1771 }
1772
1773 static int parport_ECPEPP_supported(struct parport *pb)
1774 {
1775 struct parport_pc_private *priv = pb->private_data;
1776 int result;
1777 unsigned char oecr;
1778
1779 if (!priv->ecr)
1780 return 0;
1781
1782 oecr = inb(ECONTROL(pb));
1783 /* Search for SMC style EPP+ECP mode */
1784 ECR_WRITE(pb, 0x80);
1785 outb(0x04, CONTROL(pb));
1786 result = parport_EPP_supported(pb);
1787
1788 ECR_WRITE(pb, oecr);
1789
1790 if (result) {
1791 /* Set up access functions to use ECP+EPP hardware. */
1792 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1793 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1794 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1795 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1796 }
1797
1798 return result;
1799 }
1800
1801 #else /* No IEEE 1284 support */
1802
1803 /* Don't bother probing for modes we know we won't use. */
1804 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1805 #ifdef CONFIG_PARPORT_PC_FIFO
1806 static int parport_ECP_supported(struct parport *pb)
1807 {
1808 return 0;
1809 }
1810 #endif
1811 static int __devinit parport_EPP_supported(struct parport *pb)
1812 {
1813 return 0;
1814 }
1815
1816 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1817 {
1818 return 0;
1819 }
1820
1821 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1822 {
1823 return 0;
1824 }
1825
1826 #endif /* No IEEE 1284 support */
1827
1828 /* --- IRQ detection -------------------------------------- */
1829
1830 /* Only if supports ECP mode */
1831 static int programmable_irq_support(struct parport *pb)
1832 {
1833 int irq, intrLine;
1834 unsigned char oecr = inb(ECONTROL(pb));
1835 static const int lookup[8] = {
1836 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1837 };
1838
1839 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1840
1841 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1842 irq = lookup[intrLine];
1843
1844 ECR_WRITE(pb, oecr);
1845 return irq;
1846 }
1847
1848 static int irq_probe_ECP(struct parport *pb)
1849 {
1850 int i;
1851 unsigned long irqs;
1852
1853 irqs = probe_irq_on();
1854
1855 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1856 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1857 ECR_WRITE(pb, ECR_TST << 5);
1858
1859 /* If Full FIFO sure that writeIntrThreshold is generated */
1860 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1861 outb(0xaa, FIFO(pb));
1862
1863 pb->irq = probe_irq_off(irqs);
1864 ECR_WRITE(pb, ECR_SPP << 5);
1865
1866 if (pb->irq <= 0)
1867 pb->irq = PARPORT_IRQ_NONE;
1868
1869 return pb->irq;
1870 }
1871
1872 /*
1873 * This detection seems that only works in National Semiconductors
1874 * This doesn't work in SMC, LGS, and Winbond
1875 */
1876 static int irq_probe_EPP(struct parport *pb)
1877 {
1878 #ifndef ADVANCED_DETECT
1879 return PARPORT_IRQ_NONE;
1880 #else
1881 int irqs;
1882 unsigned char oecr;
1883
1884 if (pb->modes & PARPORT_MODE_PCECR)
1885 oecr = inb(ECONTROL(pb));
1886
1887 irqs = probe_irq_on();
1888
1889 if (pb->modes & PARPORT_MODE_PCECR)
1890 frob_econtrol(pb, 0x10, 0x10);
1891
1892 clear_epp_timeout(pb);
1893 parport_pc_frob_control(pb, 0x20, 0x20);
1894 parport_pc_frob_control(pb, 0x10, 0x10);
1895 clear_epp_timeout(pb);
1896
1897 /* Device isn't expecting an EPP read
1898 * and generates an IRQ.
1899 */
1900 parport_pc_read_epp(pb);
1901 udelay(20);
1902
1903 pb->irq = probe_irq_off(irqs);
1904 if (pb->modes & PARPORT_MODE_PCECR)
1905 ECR_WRITE(pb, oecr);
1906 parport_pc_write_control(pb, 0xc);
1907
1908 if (pb->irq <= 0)
1909 pb->irq = PARPORT_IRQ_NONE;
1910
1911 return pb->irq;
1912 #endif /* Advanced detection */
1913 }
1914
1915 static int irq_probe_SPP(struct parport *pb)
1916 {
1917 /* Don't even try to do this. */
1918 return PARPORT_IRQ_NONE;
1919 }
1920
1921 /* We will attempt to share interrupt requests since other devices
1922 * such as sound cards and network cards seem to like using the
1923 * printer IRQs.
1924 *
1925 * When ECP is available we can autoprobe for IRQs.
1926 * NOTE: If we can autoprobe it, we can register the IRQ.
1927 */
1928 static int parport_irq_probe(struct parport *pb)
1929 {
1930 struct parport_pc_private *priv = pb->private_data;
1931
1932 if (priv->ecr) {
1933 pb->irq = programmable_irq_support(pb);
1934
1935 if (pb->irq == PARPORT_IRQ_NONE)
1936 pb->irq = irq_probe_ECP(pb);
1937 }
1938
1939 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1940 (pb->modes & PARPORT_MODE_EPP))
1941 pb->irq = irq_probe_EPP(pb);
1942
1943 clear_epp_timeout(pb);
1944
1945 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1946 pb->irq = irq_probe_EPP(pb);
1947
1948 clear_epp_timeout(pb);
1949
1950 if (pb->irq == PARPORT_IRQ_NONE)
1951 pb->irq = irq_probe_SPP(pb);
1952
1953 if (pb->irq == PARPORT_IRQ_NONE)
1954 pb->irq = get_superio_irq(pb);
1955
1956 return pb->irq;
1957 }
1958
1959 /* --- DMA detection -------------------------------------- */
1960
1961 /* Only if chipset conforms to ECP ISA Interface Standard */
1962 static int programmable_dma_support(struct parport *p)
1963 {
1964 unsigned char oecr = inb(ECONTROL(p));
1965 int dma;
1966
1967 frob_set_mode(p, ECR_CNF);
1968
1969 dma = inb(CONFIGB(p)) & 0x07;
1970 /* 000: Indicates jumpered 8-bit DMA if read-only.
1971 100: Indicates jumpered 16-bit DMA if read-only. */
1972 if ((dma & 0x03) == 0)
1973 dma = PARPORT_DMA_NONE;
1974
1975 ECR_WRITE(p, oecr);
1976 return dma;
1977 }
1978
1979 static int parport_dma_probe(struct parport *p)
1980 {
1981 const struct parport_pc_private *priv = p->private_data;
1982 if (priv->ecr) /* ask ECP chipset first */
1983 p->dma = programmable_dma_support(p);
1984 if (p->dma == PARPORT_DMA_NONE) {
1985 /* ask known Super-IO chips proper, although these
1986 claim ECP compatible, some don't report their DMA
1987 conforming to ECP standards */
1988 p->dma = get_superio_dma(p);
1989 }
1990
1991 return p->dma;
1992 }
1993
1994 /* --- Initialisation code -------------------------------- */
1995
1996 static LIST_HEAD(ports_list);
1997 static DEFINE_SPINLOCK(ports_lock);
1998
1999 struct parport *parport_pc_probe_port(unsigned long int base,
2000 unsigned long int base_hi,
2001 int irq, int dma,
2002 struct device *dev,
2003 int irqflags)
2004 {
2005 struct parport_pc_private *priv;
2006 struct parport_operations *ops;
2007 struct parport *p;
2008 int probedirq = PARPORT_IRQ_NONE;
2009 struct resource *base_res;
2010 struct resource *ECR_res = NULL;
2011 struct resource *EPP_res = NULL;
2012 struct platform_device *pdev = NULL;
2013
2014 if (!dev) {
2015 /* We need a physical device to attach to, but none was
2016 * provided. Create our own. */
2017 pdev = platform_device_register_simple("parport_pc",
2018 base, NULL, 0);
2019 if (IS_ERR(pdev))
2020 return NULL;
2021 dev = &pdev->dev;
2022
2023 dev->coherent_dma_mask = DMA_BIT_MASK(24);
2024 dev->dma_mask = &dev->coherent_dma_mask;
2025 }
2026
2027 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2028 if (!ops)
2029 goto out1;
2030
2031 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2032 if (!priv)
2033 goto out2;
2034
2035 /* a misnomer, actually - it's allocate and reserve parport number */
2036 p = parport_register_port(base, irq, dma, ops);
2037 if (!p)
2038 goto out3;
2039
2040 base_res = request_region(base, 3, p->name);
2041 if (!base_res)
2042 goto out4;
2043
2044 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2045 priv->ctr = 0xc;
2046 priv->ctr_writable = ~0x10;
2047 priv->ecr = 0;
2048 priv->fifo_depth = 0;
2049 priv->dma_buf = NULL;
2050 priv->dma_handle = 0;
2051 INIT_LIST_HEAD(&priv->list);
2052 priv->port = p;
2053
2054 p->dev = dev;
2055 p->base_hi = base_hi;
2056 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2057 p->private_data = priv;
2058
2059 if (base_hi) {
2060 ECR_res = request_region(base_hi, 3, p->name);
2061 if (ECR_res)
2062 parport_ECR_present(p);
2063 }
2064
2065 if (base != 0x3bc) {
2066 EPP_res = request_region(base+0x3, 5, p->name);
2067 if (EPP_res)
2068 if (!parport_EPP_supported(p))
2069 parport_ECPEPP_supported(p);
2070 }
2071 if (!parport_SPP_supported(p))
2072 /* No port. */
2073 goto out5;
2074 if (priv->ecr)
2075 parport_ECPPS2_supported(p);
2076 else
2077 parport_PS2_supported(p);
2078
2079 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2080
2081 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2082 if (p->base_hi && priv->ecr)
2083 printk(" (0x%lx)", p->base_hi);
2084 if (p->irq == PARPORT_IRQ_AUTO) {
2085 p->irq = PARPORT_IRQ_NONE;
2086 parport_irq_probe(p);
2087 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2088 p->irq = PARPORT_IRQ_NONE;
2089 parport_irq_probe(p);
2090 probedirq = p->irq;
2091 p->irq = PARPORT_IRQ_NONE;
2092 }
2093 if (p->irq != PARPORT_IRQ_NONE) {
2094 printk(", irq %d", p->irq);
2095 priv->ctr_writable |= 0x10;
2096
2097 if (p->dma == PARPORT_DMA_AUTO) {
2098 p->dma = PARPORT_DMA_NONE;
2099 parport_dma_probe(p);
2100 }
2101 }
2102 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2103 is mandatory (see above) */
2104 p->dma = PARPORT_DMA_NONE;
2105
2106 #ifdef CONFIG_PARPORT_PC_FIFO
2107 if (parport_ECP_supported(p) &&
2108 p->dma != PARPORT_DMA_NOFIFO &&
2109 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2110 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2111 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2112 #ifdef CONFIG_PARPORT_1284
2113 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2114 /* currently broken, but working on it.. (FB) */
2115 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2116 #endif /* IEEE 1284 support */
2117 if (p->dma != PARPORT_DMA_NONE) {
2118 printk(", dma %d", p->dma);
2119 p->modes |= PARPORT_MODE_DMA;
2120 } else
2121 printk(", using FIFO");
2122 } else
2123 /* We can't use the DMA channel after all. */
2124 p->dma = PARPORT_DMA_NONE;
2125 #endif /* Allowed to use FIFO/DMA */
2126
2127 printk(" [");
2128
2129 #define printmode(x) \
2130 {\
2131 if (p->modes & PARPORT_MODE_##x) {\
2132 printk("%s%s", f ? "," : "", #x);\
2133 f++;\
2134 } \
2135 }
2136
2137 {
2138 int f = 0;
2139 printmode(PCSPP);
2140 printmode(TRISTATE);
2141 printmode(COMPAT)
2142 printmode(EPP);
2143 printmode(ECP);
2144 printmode(DMA);
2145 }
2146 #undef printmode
2147 #ifndef CONFIG_PARPORT_1284
2148 printk("(,...)");
2149 #endif /* CONFIG_PARPORT_1284 */
2150 printk("]\n");
2151 if (probedirq != PARPORT_IRQ_NONE)
2152 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2153
2154 /* If No ECP release the ports grabbed above. */
2155 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2156 release_region(base_hi, 3);
2157 ECR_res = NULL;
2158 }
2159 /* Likewise for EEP ports */
2160 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2161 release_region(base+3, 5);
2162 EPP_res = NULL;
2163 }
2164 if (p->irq != PARPORT_IRQ_NONE) {
2165 if (request_irq(p->irq, parport_irq_handler,
2166 irqflags, p->name, p)) {
2167 printk(KERN_WARNING "%s: irq %d in use, "
2168 "resorting to polled operation\n",
2169 p->name, p->irq);
2170 p->irq = PARPORT_IRQ_NONE;
2171 p->dma = PARPORT_DMA_NONE;
2172 }
2173
2174 #ifdef CONFIG_PARPORT_PC_FIFO
2175 #ifdef HAS_DMA
2176 if (p->dma != PARPORT_DMA_NONE) {
2177 if (request_dma(p->dma, p->name)) {
2178 printk(KERN_WARNING "%s: dma %d in use, "
2179 "resorting to PIO operation\n",
2180 p->name, p->dma);
2181 p->dma = PARPORT_DMA_NONE;
2182 } else {
2183 priv->dma_buf =
2184 dma_alloc_coherent(dev,
2185 PAGE_SIZE,
2186 &priv->dma_handle,
2187 GFP_KERNEL);
2188 if (!priv->dma_buf) {
2189 printk(KERN_WARNING "%s: "
2190 "cannot get buffer for DMA, "
2191 "resorting to PIO operation\n",
2192 p->name);
2193 free_dma(p->dma);
2194 p->dma = PARPORT_DMA_NONE;
2195 }
2196 }
2197 }
2198 #endif
2199 #endif
2200 }
2201
2202 /* Done probing. Now put the port into a sensible start-up state. */
2203 if (priv->ecr)
2204 /*
2205 * Put the ECP detected port in PS2 mode.
2206 * Do this also for ports that have ECR but don't do ECP.
2207 */
2208 ECR_WRITE(p, 0x34);
2209
2210 parport_pc_write_data(p, 0);
2211 parport_pc_data_forward(p);
2212
2213 /* Now that we've told the sharing engine about the port, and
2214 found out its characteristics, let the high-level drivers
2215 know about it. */
2216 spin_lock(&ports_lock);
2217 list_add(&priv->list, &ports_list);
2218 spin_unlock(&ports_lock);
2219 parport_announce_port(p);
2220
2221 return p;
2222
2223 out5:
2224 if (ECR_res)
2225 release_region(base_hi, 3);
2226 if (EPP_res)
2227 release_region(base+0x3, 5);
2228 release_region(base, 3);
2229 out4:
2230 parport_put_port(p);
2231 out3:
2232 kfree(priv);
2233 out2:
2234 kfree(ops);
2235 out1:
2236 if (pdev)
2237 platform_device_unregister(pdev);
2238 return NULL;
2239 }
2240 EXPORT_SYMBOL(parport_pc_probe_port);
2241
2242 void parport_pc_unregister_port(struct parport *p)
2243 {
2244 struct parport_pc_private *priv = p->private_data;
2245 struct parport_operations *ops = p->ops;
2246
2247 parport_remove_port(p);
2248 spin_lock(&ports_lock);
2249 list_del_init(&priv->list);
2250 spin_unlock(&ports_lock);
2251 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2252 if (p->dma != PARPORT_DMA_NONE)
2253 free_dma(p->dma);
2254 #endif
2255 if (p->irq != PARPORT_IRQ_NONE)
2256 free_irq(p->irq, p);
2257 release_region(p->base, 3);
2258 if (p->size > 3)
2259 release_region(p->base + 3, p->size - 3);
2260 if (p->modes & PARPORT_MODE_ECP)
2261 release_region(p->base_hi, 3);
2262 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2263 if (priv->dma_buf)
2264 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2265 priv->dma_buf,
2266 priv->dma_handle);
2267 #endif
2268 kfree(p->private_data);
2269 parport_put_port(p);
2270 kfree(ops); /* hope no-one cached it */
2271 }
2272 EXPORT_SYMBOL(parport_pc_unregister_port);
2273
2274 #ifdef CONFIG_PCI
2275
2276 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2277 static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq,
2278 int autodma,
2279 const struct parport_pc_via_data *via)
2280 {
2281 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2282 struct resource *base_res;
2283 u32 ite8872set;
2284 u32 ite8872_lpt, ite8872_lpthi;
2285 u8 ite8872_irq, type;
2286 int irq;
2287 int i;
2288
2289 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2290
2291 /* make sure which one chip */
2292 for (i = 0; i < 5; i++) {
2293 base_res = request_region(inta_addr[i], 32, "it887x");
2294 if (base_res) {
2295 int test;
2296 pci_write_config_dword(pdev, 0x60,
2297 0xe5000000 | inta_addr[i]);
2298 pci_write_config_dword(pdev, 0x78,
2299 0x00000000 | inta_addr[i]);
2300 test = inb(inta_addr[i]);
2301 if (test != 0xff)
2302 break;
2303 release_region(inta_addr[i], 0x8);
2304 }
2305 }
2306 if (i >= 5) {
2307 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2308 return 0;
2309 }
2310
2311 type = inb(inta_addr[i] + 0x18);
2312 type &= 0x0f;
2313
2314 switch (type) {
2315 case 0x2:
2316 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2317 ite8872set = 0x64200000;
2318 break;
2319 case 0xa:
2320 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2321 ite8872set = 0x64200000;
2322 break;
2323 case 0xe:
2324 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2325 ite8872set = 0x64e00000;
2326 break;
2327 case 0x6:
2328 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2329 return 0;
2330 case 0x8:
2331 DPRINTK(KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2332 return 0;
2333 default:
2334 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2335 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2336 "output to Rich.Liu@ite.com.tw\n");
2337 return 0;
2338 }
2339
2340 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2341 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2342 ite8872_lpt &= 0x0000ff00;
2343 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2344 ite8872_lpthi &= 0x0000ff00;
2345 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2346 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2347 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2348 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2349 /* SET Parallel IRQ */
2350 pci_write_config_dword(pdev, 0x9c,
2351 ite8872set | (ite8872_irq * 0x11111));
2352
2353 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2354 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2355 ite8872_lpt);
2356 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2357 ite8872_lpthi);
2358
2359 /* Let the user (or defaults) steer us away from interrupts */
2360 irq = ite8872_irq;
2361 if (autoirq != PARPORT_IRQ_AUTO)
2362 irq = PARPORT_IRQ_NONE;
2363
2364 /*
2365 * Release the resource so that parport_pc_probe_port can get it.
2366 */
2367 release_resource(base_res);
2368 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2369 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2370 printk(KERN_INFO
2371 "parport_pc: ITE 8872 parallel port: io=0x%X",
2372 ite8872_lpt);
2373 if (irq != PARPORT_IRQ_NONE)
2374 printk(", irq=%d", irq);
2375 printk("\n");
2376 return 1;
2377 }
2378
2379 return 0;
2380 }
2381
2382 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2383 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2384 static int __devinitdata parport_init_mode;
2385
2386 /* Data for two known VIA chips */
2387 static struct parport_pc_via_data via_686a_data __devinitdata = {
2388 0x51,
2389 0x50,
2390 0x85,
2391 0x02,
2392 0xE2,
2393 0xF0,
2394 0xE6
2395 };
2396 static struct parport_pc_via_data via_8231_data __devinitdata = {
2397 0x45,
2398 0x44,
2399 0x50,
2400 0x04,
2401 0xF2,
2402 0xFA,
2403 0xF6
2404 };
2405
2406 static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq,
2407 int autodma,
2408 const struct parport_pc_via_data *via)
2409 {
2410 u8 tmp, tmp2, siofunc;
2411 u8 ppcontrol = 0;
2412 int dma, irq;
2413 unsigned port1, port2;
2414 unsigned have_epp = 0;
2415
2416 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2417
2418 switch (parport_init_mode) {
2419 case 1:
2420 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2421 siofunc = VIA_FUNCTION_PARPORT_SPP;
2422 break;
2423 case 2:
2424 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2425 siofunc = VIA_FUNCTION_PARPORT_SPP;
2426 ppcontrol = VIA_PARPORT_BIDIR;
2427 break;
2428 case 3:
2429 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2430 siofunc = VIA_FUNCTION_PARPORT_EPP;
2431 ppcontrol = VIA_PARPORT_BIDIR;
2432 have_epp = 1;
2433 break;
2434 case 4:
2435 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2436 siofunc = VIA_FUNCTION_PARPORT_ECP;
2437 ppcontrol = VIA_PARPORT_BIDIR;
2438 break;
2439 case 5:
2440 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2441 siofunc = VIA_FUNCTION_PARPORT_ECP;
2442 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2443 have_epp = 1;
2444 break;
2445 default:
2446 printk(KERN_DEBUG
2447 "parport_pc: probing current configuration\n");
2448 siofunc = VIA_FUNCTION_PROBE;
2449 break;
2450 }
2451 /*
2452 * unlock super i/o configuration
2453 */
2454 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2455 tmp |= via->via_pci_superio_config_data;
2456 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2457
2458 /* Bits 1-0: Parallel Port Mode / Enable */
2459 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2460 tmp = inb(VIA_CONFIG_DATA);
2461 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2462 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2463 tmp2 = inb(VIA_CONFIG_DATA);
2464 if (siofunc == VIA_FUNCTION_PROBE) {
2465 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2466 ppcontrol = tmp2;
2467 } else {
2468 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2469 tmp |= siofunc;
2470 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2471 outb(tmp, VIA_CONFIG_DATA);
2472 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2473 tmp2 |= ppcontrol;
2474 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2475 outb(tmp2, VIA_CONFIG_DATA);
2476 }
2477
2478 /* Parallel Port I/O Base Address, bits 9-2 */
2479 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2480 port1 = inb(VIA_CONFIG_DATA) << 2;
2481
2482 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2483 port1);
2484 if (port1 == 0x3BC && have_epp) {
2485 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2486 outb((0x378 >> 2), VIA_CONFIG_DATA);
2487 printk(KERN_DEBUG
2488 "parport_pc: Parallel port base changed to 0x378\n");
2489 port1 = 0x378;
2490 }
2491
2492 /*
2493 * lock super i/o configuration
2494 */
2495 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2496 tmp &= ~via->via_pci_superio_config_data;
2497 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2498
2499 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2500 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2501 return 0;
2502 }
2503
2504 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2505 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2506 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2507
2508 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2509 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2510 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2511 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2512 } else
2513 /* if ECP not enabled, DMA is not enabled, assumed
2514 bogus 'dma' value */
2515 dma = PARPORT_DMA_NONE;
2516
2517 /* Let the user (or defaults) steer us away from interrupts and DMA */
2518 if (autoirq == PARPORT_IRQ_NONE) {
2519 irq = PARPORT_IRQ_NONE;
2520 dma = PARPORT_DMA_NONE;
2521 }
2522 if (autodma == PARPORT_DMA_NONE)
2523 dma = PARPORT_DMA_NONE;
2524
2525 switch (port1) {
2526 case 0x3bc:
2527 port2 = 0x7bc; break;
2528 case 0x378:
2529 port2 = 0x778; break;
2530 case 0x278:
2531 port2 = 0x678; break;
2532 default:
2533 printk(KERN_INFO
2534 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2535 port1);
2536 return 0;
2537 }
2538
2539 /* filter bogus IRQs */
2540 switch (irq) {
2541 case 0:
2542 case 2:
2543 case 8:
2544 case 13:
2545 irq = PARPORT_IRQ_NONE;
2546 break;
2547
2548 default: /* do nothing */
2549 break;
2550 }
2551
2552 /* finally, do the probe with values obtained */
2553 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2554 printk(KERN_INFO
2555 "parport_pc: VIA parallel port: io=0x%X", port1);
2556 if (irq != PARPORT_IRQ_NONE)
2557 printk(", irq=%d", irq);
2558 if (dma != PARPORT_DMA_NONE)
2559 printk(", dma=%d", dma);
2560 printk("\n");
2561 return 1;
2562 }
2563
2564 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2565 port1, irq, dma);
2566 return 0;
2567 }
2568
2569
2570 enum parport_pc_sio_types {
2571 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2572 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2573 sio_ite_8872,
2574 last_sio
2575 };
2576
2577 /* each element directly indexed from enum list, above */
2578 static struct parport_pc_superio {
2579 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2580 const struct parport_pc_via_data *via);
2581 const struct parport_pc_via_data *via;
2582 } parport_pc_superio_info[] __devinitdata = {
2583 { sio_via_probe, &via_686a_data, },
2584 { sio_via_probe, &via_8231_data, },
2585 { sio_ite_8872_probe, NULL, },
2586 };
2587
2588 enum parport_pc_pci_cards {
2589 siig_1p_10x = last_sio,
2590 siig_2p_10x,
2591 siig_1p_20x,
2592 siig_2p_20x,
2593 lava_parallel,
2594 lava_parallel_dual_a,
2595 lava_parallel_dual_b,
2596 boca_ioppar,
2597 plx_9050,
2598 timedia_4078a,
2599 timedia_4079h,
2600 timedia_4085h,
2601 timedia_4088a,
2602 timedia_4089a,
2603 timedia_4095a,
2604 timedia_4096a,
2605 timedia_4078u,
2606 timedia_4079a,
2607 timedia_4085u,
2608 timedia_4079r,
2609 timedia_4079s,
2610 timedia_4079d,
2611 timedia_4079e,
2612 timedia_4079f,
2613 timedia_9079a,
2614 timedia_9079b,
2615 timedia_9079c,
2616 timedia_4006a,
2617 timedia_4014,
2618 timedia_4008a,
2619 timedia_4018,
2620 timedia_9018a,
2621 syba_2p_epp,
2622 syba_1p_ecp,
2623 titan_010l,
2624 titan_1284p1,
2625 titan_1284p2,
2626 avlab_1p,
2627 avlab_2p,
2628 oxsemi_952,
2629 oxsemi_954,
2630 oxsemi_840,
2631 oxsemi_pcie_pport,
2632 aks_0100,
2633 mobility_pp,
2634 netmos_9705,
2635 netmos_9715,
2636 netmos_9755,
2637 netmos_9805,
2638 netmos_9815,
2639 netmos_9901,
2640 netmos_9865,
2641 quatech_sppxp100,
2642 };
2643
2644
2645 /* each element directly indexed from enum list, above
2646 * (but offset by last_sio) */
2647 static struct parport_pc_pci {
2648 int numports;
2649 struct { /* BAR (base address registers) numbers in the config
2650 space header */
2651 int lo;
2652 int hi;
2653 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2654 } addr[4];
2655
2656 /* If set, this is called immediately after pci_enable_device.
2657 * If it returns non-zero, no probing will take place and the
2658 * ports will not be used. */
2659 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2660
2661 /* If set, this is called after probing for ports. If 'failed'
2662 * is non-zero we couldn't use any of the ports. */
2663 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2664 } cards[] = {
2665 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2666 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2667 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2668 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2669 /* lava_parallel */ { 1, { { 0, -1 }, } },
2670 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2671 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2672 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2673 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2674 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2675 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2676 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2677 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2678 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2679 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2680 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2681 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2682 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2683 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2684 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2685 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2686 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2687 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2688 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2689 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2690 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2691 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2692 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2693 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2694 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2695 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2696 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2697 /* SYBA uses fixed offsets in
2698 a 1K io window */
2699 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2700 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2701 /* titan_010l */ { 1, { { 3, -1 }, } },
2702 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2703 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2704 /* avlab_1p */ { 1, { { 0, 1}, } },
2705 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2706 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2707 * and 840 locks up if you write 1 to bit 2! */
2708 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2709 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2710 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2711 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2712 /* aks_0100 */ { 1, { { 0, -1 }, } },
2713 /* mobility_pp */ { 1, { { 0, 1 }, } },
2714
2715 /* The netmos entries below are untested */
2716 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2717 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2718 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2719 /* netmos_9805 */ { 1, { { 0, -1 }, } },
2720 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2721 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2722 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2723 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2724 };
2725
2726 static const struct pci_device_id parport_pc_pci_tbl[] = {
2727 /* Super-IO onboard chips */
2728 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2729 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2730 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2732
2733 /* PCI cards */
2734 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2736 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2738 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2740 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2742 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2744 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2746 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2748 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2750 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2751 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2752 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2753 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2754 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2755 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2756 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2757 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2758 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2759 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2760 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2761 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2762 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2763 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2764 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2765 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2766 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2767 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2768 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2769 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2770 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2771 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2772 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2773 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2774 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2775 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2776 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2778 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2780 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2782 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
2783 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2784 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2785 /* AFAVLAB_TK9902 */
2786 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2787 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2788 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2790 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2792 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2794 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2796 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2798 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2800 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2802 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2804 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2806 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2808 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2810 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2812 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2813 /* NetMos communication controllers */
2814 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2816 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2818 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2820 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2822 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2824 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2825 0xA000, 0x2000, 0, 0, netmos_9901 },
2826 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2827 0xA000, 0x1000, 0, 0, netmos_9865 },
2828 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2829 0xA000, 0x2000, 0, 0, netmos_9865 },
2830 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2831 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2833 { 0, } /* terminate list */
2834 };
2835 MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2836
2837 struct pci_parport_data {
2838 int num;
2839 struct parport *ports[2];
2840 };
2841
2842 static int parport_pc_pci_probe(struct pci_dev *dev,
2843 const struct pci_device_id *id)
2844 {
2845 int err, count, n, i = id->driver_data;
2846 struct pci_parport_data *data;
2847
2848 if (i < last_sio)
2849 /* This is an onboard Super-IO and has already been probed */
2850 return 0;
2851
2852 /* This is a PCI card */
2853 i -= last_sio;
2854 count = 0;
2855 err = pci_enable_device(dev);
2856 if (err)
2857 return err;
2858
2859 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2860 if (!data)
2861 return -ENOMEM;
2862
2863 if (cards[i].preinit_hook &&
2864 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2865 kfree(data);
2866 return -ENODEV;
2867 }
2868
2869 for (n = 0; n < cards[i].numports; n++) {
2870 int lo = cards[i].addr[n].lo;
2871 int hi = cards[i].addr[n].hi;
2872 int irq;
2873 unsigned long io_lo, io_hi;
2874 io_lo = pci_resource_start(dev, lo);
2875 io_hi = 0;
2876 if ((hi >= 0) && (hi <= 6))
2877 io_hi = pci_resource_start(dev, hi);
2878 else if (hi > 6)
2879 io_lo += hi; /* Reinterpret the meaning of
2880 "hi" as an offset (see SYBA
2881 def.) */
2882 /* TODO: test if sharing interrupts works */
2883 irq = dev->irq;
2884 if (irq == IRQ_NONE) {
2885 printk(KERN_DEBUG
2886 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2887 parport_pc_pci_tbl[i + last_sio].vendor,
2888 parport_pc_pci_tbl[i + last_sio].device,
2889 io_lo, io_hi);
2890 irq = PARPORT_IRQ_NONE;
2891 } else {
2892 printk(KERN_DEBUG
2893 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2894 parport_pc_pci_tbl[i + last_sio].vendor,
2895 parport_pc_pci_tbl[i + last_sio].device,
2896 io_lo, io_hi, irq);
2897 }
2898 data->ports[count] =
2899 parport_pc_probe_port(io_lo, io_hi, irq,
2900 PARPORT_DMA_NONE, &dev->dev,
2901 IRQF_SHARED);
2902 if (data->ports[count])
2903 count++;
2904 }
2905
2906 data->num = count;
2907
2908 if (cards[i].postinit_hook)
2909 cards[i].postinit_hook(dev, count == 0);
2910
2911 if (count) {
2912 pci_set_drvdata(dev, data);
2913 return 0;
2914 }
2915
2916 kfree(data);
2917
2918 return -ENODEV;
2919 }
2920
2921 static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
2922 {
2923 struct pci_parport_data *data = pci_get_drvdata(dev);
2924 int i;
2925
2926 pci_set_drvdata(dev, NULL);
2927
2928 if (data) {
2929 for (i = data->num - 1; i >= 0; i--)
2930 parport_pc_unregister_port(data->ports[i]);
2931
2932 kfree(data);
2933 }
2934 }
2935
2936 static struct pci_driver parport_pc_pci_driver = {
2937 .name = "parport_pc",
2938 .id_table = parport_pc_pci_tbl,
2939 .probe = parport_pc_pci_probe,
2940 .remove = __devexit_p(parport_pc_pci_remove),
2941 };
2942
2943 static int __init parport_pc_init_superio(int autoirq, int autodma)
2944 {
2945 const struct pci_device_id *id;
2946 struct pci_dev *pdev = NULL;
2947 int ret = 0;
2948
2949 for_each_pci_dev(pdev) {
2950 id = pci_match_id(parport_pc_pci_tbl, pdev);
2951 if (id == NULL || id->driver_data >= last_sio)
2952 continue;
2953
2954 if (parport_pc_superio_info[id->driver_data].probe(
2955 pdev, autoirq, autodma,
2956 parport_pc_superio_info[id->driver_data].via)) {
2957 ret++;
2958 }
2959 }
2960
2961 return ret; /* number of devices found */
2962 }
2963 #else
2964 static struct pci_driver parport_pc_pci_driver;
2965 static int __init parport_pc_init_superio(int autoirq, int autodma)
2966 {
2967 return 0;
2968 }
2969 #endif /* CONFIG_PCI */
2970
2971 #ifdef CONFIG_PNP
2972
2973 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2974 /* Standard LPT Printer Port */
2975 {.id = "PNP0400", .driver_data = 0},
2976 /* ECP Printer Port */
2977 {.id = "PNP0401", .driver_data = 0},
2978 { }
2979 };
2980
2981 MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2982
2983 static int parport_pc_pnp_probe(struct pnp_dev *dev,
2984 const struct pnp_device_id *id)
2985 {
2986 struct parport *pdata;
2987 unsigned long io_lo, io_hi;
2988 int dma, irq;
2989
2990 if (pnp_port_valid(dev, 0) &&
2991 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2992 io_lo = pnp_port_start(dev, 0);
2993 } else
2994 return -EINVAL;
2995
2996 if (pnp_port_valid(dev, 1) &&
2997 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2998 io_hi = pnp_port_start(dev, 1);
2999 } else
3000 io_hi = 0;
3001
3002 if (pnp_irq_valid(dev, 0) &&
3003 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
3004 irq = pnp_irq(dev, 0);
3005 } else
3006 irq = PARPORT_IRQ_NONE;
3007
3008 if (pnp_dma_valid(dev, 0) &&
3009 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
3010 dma = pnp_dma(dev, 0);
3011 } else
3012 dma = PARPORT_DMA_NONE;
3013
3014 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3015 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
3016 if (pdata == NULL)
3017 return -ENODEV;
3018
3019 pnp_set_drvdata(dev, pdata);
3020 return 0;
3021 }
3022
3023 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3024 {
3025 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3026 if (!pdata)
3027 return;
3028
3029 parport_pc_unregister_port(pdata);
3030 }
3031
3032 /* we only need the pnp layer to activate the device, at least for now */
3033 static struct pnp_driver parport_pc_pnp_driver = {
3034 .name = "parport_pc",
3035 .id_table = parport_pc_pnp_tbl,
3036 .probe = parport_pc_pnp_probe,
3037 .remove = parport_pc_pnp_remove,
3038 };
3039
3040 #else
3041 static struct pnp_driver parport_pc_pnp_driver;
3042 #endif /* CONFIG_PNP */
3043
3044 static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
3045 {
3046 /* Always succeed, the actual probing is done in
3047 * parport_pc_probe_port(). */
3048 return 0;
3049 }
3050
3051 static struct platform_driver parport_pc_platform_driver = {
3052 .driver = {
3053 .owner = THIS_MODULE,
3054 .name = "parport_pc",
3055 },
3056 .probe = parport_pc_platform_probe,
3057 };
3058
3059 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3060 static int __devinit __attribute__((unused))
3061 parport_pc_find_isa_ports(int autoirq, int autodma)
3062 {
3063 int count = 0;
3064
3065 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3066 count++;
3067 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3068 count++;
3069 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3070 count++;
3071
3072 return count;
3073 }
3074
3075 /* This function is called by parport_pc_init if the user didn't
3076 * specify any ports to probe. Its job is to find some ports. Order
3077 * is important here -- we want ISA ports to be registered first,
3078 * followed by PCI cards (for least surprise), but before that we want
3079 * to do chipset-specific tests for some onboard ports that we know
3080 * about.
3081 *
3082 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3083 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3084 */
3085 static void __init parport_pc_find_ports(int autoirq, int autodma)
3086 {
3087 int count = 0, err;
3088
3089 #ifdef CONFIG_PARPORT_PC_SUPERIO
3090 detect_and_report_it87();
3091 detect_and_report_winbond();
3092 detect_and_report_smsc();
3093 #endif
3094
3095 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3096 count += parport_pc_init_superio(autoirq, autodma);
3097
3098 /* PnP ports, skip detection if SuperIO already found them */
3099 if (!count) {
3100 err = pnp_register_driver(&parport_pc_pnp_driver);
3101 if (!err)
3102 pnp_registered_parport = 1;
3103 }
3104
3105 /* ISA ports and whatever (see asm/parport.h). */
3106 parport_pc_find_nonpci_ports(autoirq, autodma);
3107
3108 err = pci_register_driver(&parport_pc_pci_driver);
3109 if (!err)
3110 pci_registered_parport = 1;
3111 }
3112
3113 /*
3114 * Piles of crap below pretend to be a parser for module and kernel
3115 * parameters. Say "thank you" to whoever had come up with that
3116 * syntax and keep in mind that code below is a cleaned up version.
3117 */
3118
3119 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3120 [0 ... PARPORT_PC_MAX_PORTS] = 0
3121 };
3122 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3123 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3124 };
3125 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3126 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3127 };
3128 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3129 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3130 };
3131
3132 static int __init parport_parse_param(const char *s, int *val,
3133 int automatic, int none, int nofifo)
3134 {
3135 if (!s)
3136 return 0;
3137 if (!strncmp(s, "auto", 4))
3138 *val = automatic;
3139 else if (!strncmp(s, "none", 4))
3140 *val = none;
3141 else if (nofifo && !strncmp(s, "nofifo", 6))
3142 *val = nofifo;
3143 else {
3144 char *ep;
3145 unsigned long r = simple_strtoul(s, &ep, 0);
3146 if (ep != s)
3147 *val = r;
3148 else {
3149 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3150 return -1;
3151 }
3152 }
3153 return 0;
3154 }
3155
3156 static int __init parport_parse_irq(const char *irqstr, int *val)
3157 {
3158 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3159 PARPORT_IRQ_NONE, 0);
3160 }
3161
3162 static int __init parport_parse_dma(const char *dmastr, int *val)
3163 {
3164 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3165 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3166 }
3167
3168 #ifdef CONFIG_PCI
3169 static int __init parport_init_mode_setup(char *str)
3170 {
3171 printk(KERN_DEBUG
3172 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3173
3174 if (!strcmp(str, "spp"))
3175 parport_init_mode = 1;
3176 if (!strcmp(str, "ps2"))
3177 parport_init_mode = 2;
3178 if (!strcmp(str, "epp"))
3179 parport_init_mode = 3;
3180 if (!strcmp(str, "ecp"))
3181 parport_init_mode = 4;
3182 if (!strcmp(str, "ecpepp"))
3183 parport_init_mode = 5;
3184 return 1;
3185 }
3186 #endif
3187
3188 #ifdef MODULE
3189 static const char *irq[PARPORT_PC_MAX_PORTS];
3190 static const char *dma[PARPORT_PC_MAX_PORTS];
3191
3192 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3193 module_param_array(io, int, NULL, 0);
3194 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3195 module_param_array(io_hi, int, NULL, 0);
3196 MODULE_PARM_DESC(irq, "IRQ line");
3197 module_param_array(irq, charp, NULL, 0);
3198 MODULE_PARM_DESC(dma, "DMA channel");
3199 module_param_array(dma, charp, NULL, 0);
3200 #if defined(CONFIG_PARPORT_PC_SUPERIO) || (defined(CONFIG_PARPORT_1284) && \
3201 defined(CONFIG_PARPORT_PC_FIFO))
3202 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3203 module_param(verbose_probing, int, 0644);
3204 #endif
3205 #ifdef CONFIG_PCI
3206 static char *init_mode;
3207 MODULE_PARM_DESC(init_mode,
3208 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3209 module_param(init_mode, charp, 0);
3210 #endif
3211
3212 static int __init parse_parport_params(void)
3213 {
3214 unsigned int i;
3215 int val;
3216
3217 #ifdef CONFIG_PCI
3218 if (init_mode)
3219 parport_init_mode_setup(init_mode);
3220 #endif
3221
3222 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3223 if (parport_parse_irq(irq[i], &val))
3224 return 1;
3225 irqval[i] = val;
3226 if (parport_parse_dma(dma[i], &val))
3227 return 1;
3228 dmaval[i] = val;
3229 }
3230 if (!io[0]) {
3231 /* The user can make us use any IRQs or DMAs we find. */
3232 if (irq[0] && !parport_parse_irq(irq[0], &val))
3233 switch (val) {
3234 case PARPORT_IRQ_NONE:
3235 case PARPORT_IRQ_AUTO:
3236 irqval[0] = val;
3237 break;
3238 default:
3239 printk(KERN_WARNING
3240 "parport_pc: irq specified "
3241 "without base address. Use 'io=' "
3242 "to specify one\n");
3243 }
3244
3245 if (dma[0] && !parport_parse_dma(dma[0], &val))
3246 switch (val) {
3247 case PARPORT_DMA_NONE:
3248 case PARPORT_DMA_AUTO:
3249 dmaval[0] = val;
3250 break;
3251 default:
3252 printk(KERN_WARNING
3253 "parport_pc: dma specified "
3254 "without base address. Use 'io=' "
3255 "to specify one\n");
3256 }
3257 }
3258 return 0;
3259 }
3260
3261 #else
3262
3263 static int parport_setup_ptr __initdata;
3264
3265 /*
3266 * Acceptable parameters:
3267 *
3268 * parport=0
3269 * parport=auto
3270 * parport=0xBASE[,IRQ[,DMA]]
3271 *
3272 * IRQ/DMA may be numeric or 'auto' or 'none'
3273 */
3274 static int __init parport_setup(char *str)
3275 {
3276 char *endptr;
3277 char *sep;
3278 int val;
3279
3280 if (!str || !*str || (*str == '0' && !*(str+1))) {
3281 /* Disable parport if "parport=0" in cmdline */
3282 io[0] = PARPORT_DISABLE;
3283 return 1;
3284 }
3285
3286 if (!strncmp(str, "auto", 4)) {
3287 irqval[0] = PARPORT_IRQ_AUTO;
3288 dmaval[0] = PARPORT_DMA_AUTO;
3289 return 1;
3290 }
3291
3292 val = simple_strtoul(str, &endptr, 0);
3293 if (endptr == str) {
3294 printk(KERN_WARNING "parport=%s not understood\n", str);
3295 return 1;
3296 }
3297
3298 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3299 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3300 return 1;
3301 }
3302
3303 io[parport_setup_ptr] = val;
3304 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3305 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3306
3307 sep = strchr(str, ',');
3308 if (sep++) {
3309 if (parport_parse_irq(sep, &val))
3310 return 1;
3311 irqval[parport_setup_ptr] = val;
3312 sep = strchr(sep, ',');
3313 if (sep++) {
3314 if (parport_parse_dma(sep, &val))
3315 return 1;
3316 dmaval[parport_setup_ptr] = val;
3317 }
3318 }
3319 parport_setup_ptr++;
3320 return 1;
3321 }
3322
3323 static int __init parse_parport_params(void)
3324 {
3325 return io[0] == PARPORT_DISABLE;
3326 }
3327
3328 __setup("parport=", parport_setup);
3329
3330 /*
3331 * Acceptable parameters:
3332 *
3333 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3334 */
3335 #ifdef CONFIG_PCI
3336 __setup("parport_init_mode=", parport_init_mode_setup);
3337 #endif
3338 #endif
3339
3340 /* "Parser" ends here */
3341
3342 static int __init parport_pc_init(void)
3343 {
3344 int err;
3345
3346 if (parse_parport_params())
3347 return -EINVAL;
3348
3349 err = platform_driver_register(&parport_pc_platform_driver);
3350 if (err)
3351 return err;
3352
3353 if (io[0]) {
3354 int i;
3355 /* Only probe the ports we were given. */
3356 user_specified = 1;
3357 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3358 if (!io[i])
3359 break;
3360 if (io_hi[i] == PARPORT_IOHI_AUTO)
3361 io_hi[i] = 0x400 + io[i];
3362 parport_pc_probe_port(io[i], io_hi[i],
3363 irqval[i], dmaval[i], NULL, 0);
3364 }
3365 } else
3366 parport_pc_find_ports(irqval[0], dmaval[0]);
3367
3368 return 0;
3369 }
3370
3371 static void __exit parport_pc_exit(void)
3372 {
3373 if (pci_registered_parport)
3374 pci_unregister_driver(&parport_pc_pci_driver);
3375 if (pnp_registered_parport)
3376 pnp_unregister_driver(&parport_pc_pnp_driver);
3377 platform_driver_unregister(&parport_pc_platform_driver);
3378
3379 while (!list_empty(&ports_list)) {
3380 struct parport_pc_private *priv;
3381 struct parport *port;
3382 priv = list_entry(ports_list.next,
3383 struct parport_pc_private, list);
3384 port = priv->port;
3385 if (port->dev && port->dev->bus == &platform_bus_type)
3386 platform_device_unregister(
3387 to_platform_device(port->dev));
3388 parport_pc_unregister_port(port);
3389 }
3390 }
3391
3392 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3393 MODULE_DESCRIPTION("PC-style parallel port driver");
3394 MODULE_LICENSE("GPL");
3395 module_init(parport_pc_init)
3396 module_exit(parport_pc_exit)
Tomato firmware and modifications.