release/src-rt-6.x.4708/linux/linux-2.6.36/arch/x86/kernel/cpu/mtrr/generic.c

   1 /*
   2  * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
   3  * because MTRRs can span upto 40 bits (36bits on most modern x86)
   4  */
   5 #define DEBUG
   6
   7 #include <linux/module.h>
   8 #include <linux/init.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11
  12 #include <asm/processor-flags.h>
  13 #include <asm/cpufeature.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/system.h>
  16 #include <asm/mtrr.h>
  17 #include <asm/msr.h>
  18 #include <asm/pat.h>
  19
  20 #include "mtrr.h"
  21
  22 struct fixed_range_block {
  23         int base_msr;           /* start address of an MTRR block */
  24         int ranges;             /* number of MTRRs in this block  */
  25 };
  26
  27 static struct fixed_range_block fixed_range_blocks[] = {
  28         { MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
  29         { MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
  30         { MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
  31         {}
  32 };
  33
  34 static unsigned long smp_changes_mask;
  35 static int mtrr_state_set;
  36 u64 mtrr_tom2;
  37
  38 struct mtrr_state_type mtrr_state;
  39 EXPORT_SYMBOL_GPL(mtrr_state);
  40
  41 /*
  42  * BIOS is expected to clear MtrrFixDramModEn bit, see for example
  43  * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  44  * Opteron Processors" (26094 Rev. 3.30 February 2006), section
  45  * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
  46  * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
  47  * 0 for operation."
  48  */
  49 static inline void k8_check_syscfg_dram_mod_en(void)
  50 {
  51         u32 lo, hi;
  52
  53         if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
  54               (boot_cpu_data.x86 >= 0x0f)))
  55                 return;
  56
  57         rdmsr(MSR_K8_SYSCFG, lo, hi);
  58         if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
  59                 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
  60                        " not cleared by BIOS, clearing this bit\n",
  61                        smp_processor_id());
  62                 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
  63                 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
  64         }
  65 }
  66
  67 /*
  68  * Returns the effective MTRR type for the region
  69  * Error returns:
  70  * - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
  71  * - 0xFF - when MTRR is not enabled
  72  */
  73 u8 mtrr_type_lookup(u64 start, u64 end)
  74 {
  75         int i;
  76         u64 base, mask;
  77         u8 prev_match, curr_match;
  78
  79         if (!mtrr_state_set)
  80                 return 0xFF;
  81
  82         if (!mtrr_state.enabled)
  83                 return 0xFF;
  84
  85         /* Make end inclusive end, instead of exclusive */
  86         end--;
  87
  88         /* Look in fixed ranges. Just return the type as per start */
  89         if (mtrr_state.have_fixed && (start < 0x100000)) {
  90                 int idx;
  91
  92                 if (start < 0x80000) {
  93                         idx = 0;
  94                         idx += (start >> 16);
  95                         return mtrr_state.fixed_ranges[idx];
  96                 } else if (start < 0xC0000) {
  97                         idx = 1 * 8;
  98                         idx += ((start - 0x80000) >> 14);
  99                         return mtrr_state.fixed_ranges[idx];
 100                 } else if (start < 0x1000000) {
 101                         idx = 3 * 8;
 102                         idx += ((start - 0xC0000) >> 12);
 103                         return mtrr_state.fixed_ranges[idx];
 104                 }
 105         }
 106
 107         /*
 108          * Look in variable ranges
 109          * Look of multiple ranges matching this address and pick type
 110          * as per MTRR precedence
 111          */
 112         if (!(mtrr_state.enabled & 2))
 113                 return mtrr_state.def_type;
 114
 115         prev_match = 0xFF;
 116         for (i = 0; i < num_var_ranges; ++i) {
 117                 unsigned short start_state, end_state;
 118
 119                 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
 120                         continue;
 121
 122                 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
 123                        (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
 124                 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
 125                        (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
 126
 127                 start_state = ((start & mask) == (base & mask));
 128                 end_state = ((end & mask) == (base & mask));
 129                 if (start_state != end_state)
 130                         return 0xFE;
 131
 132                 if ((start & mask) != (base & mask))
 133                         continue;
 134
 135                 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
 136                 if (prev_match == 0xFF) {
 137                         prev_match = curr_match;
 138                         continue;
 139                 }
 140
 141                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
 142                     curr_match == MTRR_TYPE_UNCACHABLE) {
 143                         return MTRR_TYPE_UNCACHABLE;
 144                 }
 145
 146                 if ((prev_match == MTRR_TYPE_WRBACK &&
 147                      curr_match == MTRR_TYPE_WRTHROUGH) ||
 148                     (prev_match == MTRR_TYPE_WRTHROUGH &&
 149                      curr_match == MTRR_TYPE_WRBACK)) {
 150                         prev_match = MTRR_TYPE_WRTHROUGH;
 151                         curr_match = MTRR_TYPE_WRTHROUGH;
 152                 }
 153
 154                 if (prev_match != curr_match)
 155                         return MTRR_TYPE_UNCACHABLE;
 156         }
 157
 158         if (mtrr_tom2) {
 159                 if (start >= (1ULL<<32) && (end < mtrr_tom2))
 160                         return MTRR_TYPE_WRBACK;
 161         }
 162
 163         if (prev_match != 0xFF)
 164                 return prev_match;
 165
 166         return mtrr_state.def_type;
 167 }
 168
 169 /* Get the MSR pair relating to a var range */
 170 static void
 171 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
 172 {
 173         rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 174         rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 175 }
 176
 177 /* Fill the MSR pair relating to a var range */
 178 void fill_mtrr_var_range(unsigned int index,
 179                 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
 180 {
 181         struct mtrr_var_range *vr;
 182
 183         vr = mtrr_state.var_ranges;
 184
 185         vr[index].base_lo = base_lo;
 186         vr[index].base_hi = base_hi;
 187         vr[index].mask_lo = mask_lo;
 188         vr[index].mask_hi = mask_hi;
 189 }
 190
 191 static void get_fixed_ranges(mtrr_type *frs)
 192 {
 193         unsigned int *p = (unsigned int *)frs;
 194         int i;
 195
 196         k8_check_syscfg_dram_mod_en();
 197
 198         rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
 199
 200         for (i = 0; i < 2; i++)
 201                 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
 202         for (i = 0; i < 8; i++)
 203                 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
 204 }
 205
 206 void mtrr_save_fixed_ranges(void *info)
 207 {
 208         if (cpu_has_mtrr)
 209                 get_fixed_ranges(mtrr_state.fixed_ranges);
 210 }
 211
 212 static unsigned __initdata last_fixed_start;
 213 static unsigned __initdata last_fixed_end;
 214 static mtrr_type __initdata last_fixed_type;
 215
 216 static void __init print_fixed_last(void)
 217 {
 218         if (!last_fixed_end)
 219                 return;
 220
 221         pr_debug("  %05X-%05X %s\n", last_fixed_start,
 222                  last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
 223
 224         last_fixed_end = 0;
 225 }
 226
 227 static void __init update_fixed_last(unsigned base, unsigned end,
 228                                      mtrr_type type)
 229 {
 230         last_fixed_start = base;
 231         last_fixed_end = end;
 232         last_fixed_type = type;
 233 }
 234
 235 static void __init
 236 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
 237 {
 238         unsigned i;
 239
 240         for (i = 0; i < 8; ++i, ++types, base += step) {
 241                 if (last_fixed_end == 0) {
 242                         update_fixed_last(base, base + step, *types);
 243                         continue;
 244                 }
 245                 if (last_fixed_end == base && last_fixed_type == *types) {
 246                         last_fixed_end = base + step;
 247                         continue;
 248                 }
 249                 /* new segments: gap or different type */
 250                 print_fixed_last();
 251                 update_fixed_last(base, base + step, *types);
 252         }
 253 }
 254
 255 static void prepare_set(void);
 256 static void post_set(void);
 257
 258 static void __init print_mtrr_state(void)
 259 {
 260         unsigned int i;
 261         int high_width;
 262
 263         pr_debug("MTRR default type: %s\n",
 264                  mtrr_attrib_to_str(mtrr_state.def_type));
 265         if (mtrr_state.have_fixed) {
 266                 pr_debug("MTRR fixed ranges %sabled:\n",
 267                          mtrr_state.enabled & 1 ? "en" : "dis");
 268                 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
 269                 for (i = 0; i < 2; ++i)
 270                         print_fixed(0x80000 + i * 0x20000, 0x04000,
 271                                     mtrr_state.fixed_ranges + (i + 1) * 8);
 272                 for (i = 0; i < 8; ++i)
 273                         print_fixed(0xC0000 + i * 0x08000, 0x01000,
 274                                     mtrr_state.fixed_ranges + (i + 3) * 8);
 275
 276                 /* tail */
 277                 print_fixed_last();
 278         }
 279         pr_debug("MTRR variable ranges %sabled:\n",
 280                  mtrr_state.enabled & 2 ? "en" : "dis");
 281         if (size_or_mask & 0xffffffffUL)
 282                 high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
 283         else
 284                 high_width = ffs(size_or_mask>>32) + 32 - 1;
 285         high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
 286
 287         for (i = 0; i < num_var_ranges; ++i) {
 288                 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
 289                         pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
 290                                  i,
 291                                  high_width,
 292                                  mtrr_state.var_ranges[i].base_hi,
 293                                  mtrr_state.var_ranges[i].base_lo >> 12,
 294                                  high_width,
 295                                  mtrr_state.var_ranges[i].mask_hi,
 296                                  mtrr_state.var_ranges[i].mask_lo >> 12,
 297                                  mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
 298                 else
 299                         pr_debug("  %u disabled\n", i);
 300         }
 301         if (mtrr_tom2)
 302                 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 303 }
 304
 305 /* Grab all of the MTRR state for this CPU into *state */
 306 void __init get_mtrr_state(void)
 307 {
 308         struct mtrr_var_range *vrs;
 309         unsigned long flags;
 310         unsigned lo, dummy;
 311         unsigned int i;
 312
 313         vrs = mtrr_state.var_ranges;
 314
 315         rdmsr(MSR_MTRRcap, lo, dummy);
 316         mtrr_state.have_fixed = (lo >> 8) & 1;
 317
 318         for (i = 0; i < num_var_ranges; i++)
 319                 get_mtrr_var_range(i, &vrs[i]);
 320         if (mtrr_state.have_fixed)
 321                 get_fixed_ranges(mtrr_state.fixed_ranges);
 322
 323         rdmsr(MSR_MTRRdefType, lo, dummy);
 324         mtrr_state.def_type = (lo & 0xff);
 325         mtrr_state.enabled = (lo & 0xc00) >> 10;
 326
 327         if (amd_special_default_mtrr()) {
 328                 unsigned low, high;
 329
 330                 /* TOP_MEM2 */
 331                 rdmsr(MSR_K8_TOP_MEM2, low, high);
 332                 mtrr_tom2 = high;
 333                 mtrr_tom2 <<= 32;
 334                 mtrr_tom2 |= low;
 335                 mtrr_tom2 &= 0xffffff800000ULL;
 336         }
 337
 338         print_mtrr_state();
 339
 340         mtrr_state_set = 1;
 341
 342         /* PAT setup for BP. We need to go through sync steps here */
 343         local_irq_save(flags);
 344         prepare_set();
 345
 346         pat_init();
 347
 348         post_set();
 349         local_irq_restore(flags);
 350 }
 351
 352 /* Some BIOS's are messed up and don't set all MTRRs the same! */
 353 void __init mtrr_state_warn(void)
 354 {
 355         unsigned long mask = smp_changes_mask;
 356
 357         if (!mask)
 358                 return;
 359         if (mask & MTRR_CHANGE_MASK_FIXED)
 360                 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
 361         if (mask & MTRR_CHANGE_MASK_VARIABLE)
 362                 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
 363         if (mask & MTRR_CHANGE_MASK_DEFTYPE)
 364                 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
 365
 366         printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
 367         printk(KERN_INFO "mtrr: corrected configuration.\n");
 368 }
 369
 370 /*
 371  * Doesn't attempt to pass an error out to MTRR users
 372  * because it's quite complicated in some cases and probably not
 373  * worth it because the best error handling is to ignore it.
 374  */
 375 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
 376 {
 377         if (wrmsr_safe(msr, a, b) < 0) {
 378                 printk(KERN_ERR
 379                         "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
 380                         smp_processor_id(), msr, a, b);
 381         }
 382 }
 383
 384 /**
 385  * set_fixed_range - checks & updates a fixed-range MTRR if it
 386  *                   differs from the value it should have
 387  * @msr: MSR address of the MTTR which should be checked and updated
 388  * @changed: pointer which indicates whether the MTRR needed to be changed
 389  * @msrwords: pointer to the MSR values which the MSR should have
 390  */
 391 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 392 {
 393         unsigned lo, hi;
 394
 395         rdmsr(msr, lo, hi);
 396
 397         if (lo != msrwords[0] || hi != msrwords[1]) {
 398                 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
 399                 *changed = true;
 400         }
 401 }
 402
 403 /**
 404  * generic_get_free_region - Get a free MTRR.
 405  * @base: The starting (base) address of the region.
 406  * @size: The size (in bytes) of the region.
 407  * @replace_reg: mtrr index to be replaced; set to invalid value if none.
 408  *
 409  * Returns: The index of the region on success, else negative on error.
 410  */
 411 int
 412 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 413 {
 414         unsigned long lbase, lsize;
 415         mtrr_type ltype;
 416         int i, max;
 417
 418         max = num_var_ranges;
 419         if (replace_reg >= 0 && replace_reg < max)
 420                 return replace_reg;
 421
 422         for (i = 0; i < max; ++i) {
 423                 mtrr_if->get(i, &lbase, &lsize, &ltype);
 424                 if (lsize == 0)
 425                         return i;
 426         }
 427
 428         return -ENOSPC;
 429 }
 430
 431 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 432                              unsigned long *size, mtrr_type *type)
 433 {
 434         unsigned int mask_lo, mask_hi, base_lo, base_hi;
 435         unsigned int tmp, hi;
 436
 437         /*
 438          * get_mtrr doesn't need to update mtrr_state, also it could be called
 439          * from any cpu, so try to print it out directly.
 440          */
 441         get_cpu();
 442
 443         rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
 444
 445         if ((mask_lo & 0x800) == 0) {
 446                 /*  Invalid (i.e. free) range */
 447                 *base = 0;
 448                 *size = 0;
 449                 *type = 0;
 450                 goto out_put_cpu;
 451         }
 452
 453         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 454
 455         /* Work out the shifted address mask: */
 456         tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
 457         mask_lo = size_or_mask | tmp;
 458
 459         /* Expand tmp with high bits to all 1s: */
 460         hi = fls(tmp);
 461         if (hi > 0) {
 462                 tmp |= ~((1<<(hi - 1)) - 1);
 463
 464                 if (tmp != mask_lo) {
 465                         printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
 466                         mask_lo = tmp;
 467                 }
 468         }
 469
 470         /*
 471          * This works correctly if size is a power of two, i.e. a
 472          * contiguous range:
 473          */
 474         *size = -mask_lo;
 475         *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
 476         *type = base_lo & 0xff;
 477
 478 out_put_cpu:
 479         put_cpu();
 480 }
 481
 482 /**
 483  * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
 484  *                    differ from the saved set
 485  * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
 486  */
 487 static int set_fixed_ranges(mtrr_type *frs)
 488 {
 489         unsigned long long *saved = (unsigned long long *)frs;
 490         bool changed = false;
 491         int block = -1, range;
 492
 493         k8_check_syscfg_dram_mod_en();
 494
 495         while (fixed_range_blocks[++block].ranges) {
 496                 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
 497                         set_fixed_range(fixed_range_blocks[block].base_msr + range,
 498                                         &changed, (unsigned int *)saved++);
 499         }
 500
 501         return changed;
 502 }
 503
 504 /*
 505  * Set the MSR pair relating to a var range.
 506  * Returns true if changes are made.
 507  */
 508 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 509 {
 510         unsigned int lo, hi;
 511         bool changed = false;
 512
 513         rdmsr(MTRRphysBase_MSR(index), lo, hi);
 514         if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
 515             || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 516                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 517
 518                 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 519                 changed = true;
 520         }
 521
 522         rdmsr(MTRRphysMask_MSR(index), lo, hi);
 523
 524         if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
 525             || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 526                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 527                 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 528                 changed = true;
 529         }
 530         return changed;
 531 }
 532
 533 static u32 deftype_lo, deftype_hi;
 534
 535 /**
 536  * set_mtrr_state - Set the MTRR state for this CPU.
 537  *
 538  * NOTE: The CPU must already be in a safe state for MTRR changes.
 539  * RETURNS: 0 if no changes made, else a mask indicating what was changed.
 540  */
 541 static unsigned long set_mtrr_state(void)
 542 {
 543         unsigned long change_mask = 0;
 544         unsigned int i;
 545
 546         for (i = 0; i < num_var_ranges; i++) {
 547                 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
 548                         change_mask |= MTRR_CHANGE_MASK_VARIABLE;
 549         }
 550
 551         if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
 552                 change_mask |= MTRR_CHANGE_MASK_FIXED;
 553
 554         /*
 555          * Set_mtrr_restore restores the old value of MTRRdefType,
 556          * so to set it we fiddle with the saved value:
 557          */
 558         if ((deftype_lo & 0xff) != mtrr_state.def_type
 559             || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
 560
 561                 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
 562                              (mtrr_state.enabled << 10);
 563                 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
 564         }
 565
 566         return change_mask;
 567 }
 568
 569
 570 static unsigned long cr4;
 571 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
 572
 573 /*
 574  * Since we are disabling the cache don't allow any interrupts,
 575  * they would run extremely slow and would only increase the pain.
 576  *
 577  * The caller must ensure that local interrupts are disabled and
 578  * are reenabled after post_set() has been called.
 579  */
 580 static void prepare_set(void) __acquires(set_atomicity_lock)
 581 {
 582         unsigned long cr0;
 583
 584         /*
 585          * Note that this is not ideal
 586          * since the cache is only flushed/disabled for this CPU while the
 587          * MTRRs are changed, but changing this requires more invasive
 588          * changes to the way the kernel boots
 589          */
 590
 591         raw_spin_lock(&set_atomicity_lock);
 592
 593         /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
 594         cr0 = read_cr0() | X86_CR0_CD;
 595         write_cr0(cr0);
 596         wbinvd();
 597
 598         /* Save value of CR4 and clear Page Global Enable (bit 7) */
 599         if (cpu_has_pge) {
 600                 cr4 = read_cr4();
 601                 write_cr4(cr4 & ~X86_CR4_PGE);
 602         }
 603
 604         /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
 605         __flush_tlb();
 606
 607         /* Save MTRR state */
 608         rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 609
 610         /* Disable MTRRs, and set the default type to uncached */
 611         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
 612 }
 613
 614 static void post_set(void) __releases(set_atomicity_lock)
 615 {
 616         /* Flush TLBs (no need to flush caches - they are disabled) */
 617         __flush_tlb();
 618
 619         /* Intel (P6) standard MTRRs */
 620         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 621
 622         /* Enable caches */
 623         write_cr0(read_cr0() & 0xbfffffff);
 624
 625         /* Restore value of CR4 */
 626         if (cpu_has_pge)
 627                 write_cr4(cr4);
 628         raw_spin_unlock(&set_atomicity_lock);
 629 }
 630
 631 static void generic_set_all(void)
 632 {
 633         unsigned long mask, count;
 634         unsigned long flags;
 635
 636         local_irq_save(flags);
 637         prepare_set();
 638
 639         /* Actually set the state */
 640         mask = set_mtrr_state();
 641
 642         /* also set PAT */
 643         pat_init();
 644
 645         post_set();
 646         local_irq_restore(flags);
 647
 648         /* Use the atomic bitops to update the global mask */
 649         for (count = 0; count < sizeof mask * 8; ++count) {
 650                 if (mask & 0x01)
 651                         set_bit(count, &smp_changes_mask);
 652                 mask >>= 1;
 653         }
 654
 655 }
 656
 657 /**
 658  * generic_set_mtrr - set variable MTRR register on the local CPU.
 659  *
 660  * @reg: The register to set.
 661  * @base: The base address of the region.
 662  * @size: The size of the region. If this is 0 the region is disabled.
 663  * @type: The type of the region.
 664  *
 665  * Returns nothing.
 666  */
 667 static void generic_set_mtrr(unsigned int reg, unsigned long base,
 668                              unsigned long size, mtrr_type type)
 669 {
 670         unsigned long flags;
 671         struct mtrr_var_range *vr;
 672
 673         vr = &mtrr_state.var_ranges[reg];
 674
 675         local_irq_save(flags);
 676         prepare_set();
 677
 678         if (size == 0) {
 679                 /*
 680                  * The invalid bit is kept in the mask, so we simply
 681                  * clear the relevant mask register to disable a range.
 682                  */
 683                 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
 684                 memset(vr, 0, sizeof(struct mtrr_var_range));
 685         } else {
 686                 vr->base_lo = base << PAGE_SHIFT | type;
 687                 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
 688                 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
 689                 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
 690
 691                 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
 692                 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
 693         }
 694
 695         post_set();
 696         local_irq_restore(flags);
 697 }
 698
 699 int generic_validate_add_page(unsigned long base, unsigned long size,
 700                               unsigned int type)
 701 {
 702         unsigned long lbase, last;
 703
 704         /*
 705          * For Intel PPro stepping <= 7
 706          * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
 707          */
 708         if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
 709             boot_cpu_data.x86_model == 1 &&
 710             boot_cpu_data.x86_mask <= 7) {
 711                 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
 712                         pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
 713                         return -EINVAL;
 714                 }
 715                 if (!(base + size < 0x70000 || base > 0x7003F) &&
 716                     (type == MTRR_TYPE_WRCOMB
 717                      || type == MTRR_TYPE_WRBACK)) {
 718                         pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
 719                         return -EINVAL;
 720                 }
 721         }
 722
 723         /*
 724          * Check upper bits of base and last are equal and lower bits are 0
 725          * for base and 1 for last
 726          */
 727         last = base + size - 1;
 728         for (lbase = base; !(lbase & 1) && (last & 1);
 729              lbase = lbase >> 1, last = last >> 1)
 730                 ;
 731         if (lbase != last) {
 732                 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
 733                 return -EINVAL;
 734         }
 735         return 0;
 736 }
 737
 738 static int generic_have_wrcomb(void)
 739 {
 740         unsigned long config, dummy;
 741         rdmsr(MSR_MTRRcap, config, dummy);
 742         return config & (1 << 10);
 743 }
 744
 745 int positive_have_wrcomb(void)
 746 {
 747         return 1;
 748 }
 749
 750 /*
 751  * Generic structure...
 752  */
 753 const struct mtrr_ops generic_mtrr_ops = {
 754         .use_intel_if           = 1,
 755         .set_all                = generic_set_all,
 756         .get                    = generic_get_mtrr,
 757         .get_free_region        = generic_get_free_region,
 758         .set                    = generic_set_mtrr,
 759         .validate_add_page      = generic_validate_add_page,
 760         .have_wrcomb            = generic_have_wrcomb,
 761 };