release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-mxc/include/mach/mx2x.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This contains hardware definitions that are common between i.MX21 and
   6  * i.MX27.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #ifndef __MACH_MX2x_H__
  24 #define __MACH_MX2x_H__
  25
  26 /* The following addresses are common between i.MX21 and i.MX27 */
  27
  28 /* Register offsets */
  29 #define MX2x_AIPI_BASE_ADDR             0x10000000
  30 #define MX2x_AIPI_BASE_ADDR_VIRT        0xf4000000
  31 #define MX2x_AIPI_SIZE                  SZ_1M
  32 #define MX2x_DMA_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x01000)
  33 #define MX2x_WDOG_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x02000)
  34 #define MX2x_GPT1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x03000)
  35 #define MX2x_GPT2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x04000)
  36 #define MX2x_GPT3_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x05000)
  37 #define MX2x_PWM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x06000)
  38 #define MX2x_RTC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x07000)
  39 #define MX2x_KPP_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x08000)
  40 #define MX2x_OWIRE_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x09000)
  41 #define MX2x_UART1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0a000)
  42 #define MX2x_UART2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0b000)
  43 #define MX2x_UART3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0c000)
  44 #define MX2x_UART4_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0d000)
  45 #define MX2x_CSPI1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0e000)
  46 #define MX2x_CSPI2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0f000)
  47 #define MX2x_SSI1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x10000)
  48 #define MX2x_SSI2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x11000)
  49 #define MX2x_I2C_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x12000)
  50 #define MX2x_SDHC1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x13000)
  51 #define MX2x_SDHC2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x14000)
  52 #define MX2x_GPIO_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x15000)
  53 #define MX2x_AUDMUX_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x16000)
  54 #define MX2x_CSPI3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x17000)
  55 #define MX2x_LCDC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x21000)
  56 #define MX2x_SLCDC_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x22000)
  57 #define MX2x_USBOTG_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x24000)
  58 #define MX2x_EMMA_PP_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x26000)
  59 #define MX2x_EMMA_PRP_BASE_ADDR                 (MX2x_AIPI_BASE_ADDR + 0x26400)
  60 #define MX2x_CCM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x27000)
  61 #define MX2x_SYSCTRL_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x27800)
  62 #define MX2x_JAM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3e000)
  63 #define MX2x_MAX_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3f000)
  64
  65 #define MX2x_AVIC_BASE_ADDR             0x10040000
  66
  67 #define MX2x_SAHB1_BASE_ADDR            0x80000000
  68 #define MX2x_SAHB1_BASE_ADDR_VIRT       0xf4100000
  69 #define MX2x_SAHB1_SIZE                 SZ_1M
  70 #define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
  71
  72 /*
  73  * This macro defines the physical to virtual address mapping for all the
  74  * peripheral modules. It is used by passing in the physical address as x
  75  * and returning the virtual address. If the physical address is not mapped,
  76  * it returns 0xDEADBEEF
  77  */
  78 #define IO_ADDRESS(x)   \
  79         (void __force __iomem *) \
  80         (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
  81                 AIPI_IO_ADDRESS(x) : \
  82         ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
  83                 SAHB1_IO_ADDRESS(x) : \
  84         ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
  85                 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
  86
  87 /* define the address mapping macros: in physical address order */
  88 #define AIPI_IO_ADDRESS(x)  \
  89         (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
  90
  91 #define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
  92
  93 #define SAHB1_IO_ADDRESS(x)  \
  94         (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
  95
  96 #define CS4_IO_ADDRESS(x)  \
  97         (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
  98
  99 #define X_MEMC_IO_ADDRESS(x)  \
 100         (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 101
 102 #define PCMCIA_IO_ADDRESS(x) \
 103         (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 104
 105 /* fixed interrupt numbers */
 106 #define MX2x_INT_CSPI3          6
 107 #define MX2x_INT_GPIO           8
 108 #define MX2x_INT_SDHC2          10
 109 #define MX2x_INT_SDHC1          11
 110 #define MX2x_INT_I2C            12
 111 #define MX2x_INT_SSI2           13
 112 #define MX2x_INT_SSI1           14
 113 #define MX2x_INT_CSPI2          15
 114 #define MX2x_INT_CSPI1          16
 115 #define MX2x_INT_UART4          17
 116 #define MX2x_INT_UART3          18
 117 #define MX2x_INT_UART2          19
 118 #define MX2x_INT_UART1          20
 119 #define MX2x_INT_KPP            21
 120 #define MX2x_INT_RTC            22
 121 #define MX2x_INT_PWM            23
 122 #define MX2x_INT_GPT3           24
 123 #define MX2x_INT_GPT2           25
 124 #define MX2x_INT_GPT1           26
 125 #define MX2x_INT_WDOG           27
 126 #define MX2x_INT_PCMCIA         28
 127 #define MX2x_INT_NANDFC         29
 128 #define MX2x_INT_CSI            31
 129 #define MX2x_INT_DMACH0         32
 130 #define MX2x_INT_DMACH1         33
 131 #define MX2x_INT_DMACH2         34
 132 #define MX2x_INT_DMACH3         35
 133 #define MX2x_INT_DMACH4         36
 134 #define MX2x_INT_DMACH5         37
 135 #define MX2x_INT_DMACH6         38
 136 #define MX2x_INT_DMACH7         39
 137 #define MX2x_INT_DMACH8         40
 138 #define MX2x_INT_DMACH9         41
 139 #define MX2x_INT_DMACH10        42
 140 #define MX2x_INT_DMACH11        43
 141 #define MX2x_INT_DMACH12        44
 142 #define MX2x_INT_DMACH13        45
 143 #define MX2x_INT_DMACH14        46
 144 #define MX2x_INT_DMACH15        47
 145 #define MX2x_INT_EMMAPRP        51
 146 #define MX2x_INT_EMMAPP         52
 147 #define MX2x_INT_SLCDC          60
 148 #define MX2x_INT_LCDC           61
 149
 150 /* fixed DMA request numbers */
 151 #define MX2x_DMA_REQ_CSPI3_RX   1
 152 #define MX2x_DMA_REQ_CSPI3_TX   2
 153 #define MX2x_DMA_REQ_EXT        3
 154 #define MX2x_DMA_REQ_SDHC2      6
 155 #define MX2x_DMA_REQ_SDHC1      7
 156 #define MX2x_DMA_REQ_SSI2_RX0   8
 157 #define MX2x_DMA_REQ_SSI2_TX0   9
 158 #define MX2x_DMA_REQ_SSI2_RX1   10
 159 #define MX2x_DMA_REQ_SSI2_TX1   11
 160 #define MX2x_DMA_REQ_SSI1_RX0   12
 161 #define MX2x_DMA_REQ_SSI1_TX0   13
 162 #define MX2x_DMA_REQ_SSI1_RX1   14
 163 #define MX2x_DMA_REQ_SSI1_TX1   15
 164 #define MX2x_DMA_REQ_CSPI2_RX   16
 165 #define MX2x_DMA_REQ_CSPI2_TX   17
 166 #define MX2x_DMA_REQ_CSPI1_RX   18
 167 #define MX2x_DMA_REQ_CSPI1_TX   19
 168 #define MX2x_DMA_REQ_UART4_RX   20
 169 #define MX2x_DMA_REQ_UART4_TX   21
 170 #define MX2x_DMA_REQ_UART3_RX   22
 171 #define MX2x_DMA_REQ_UART3_TX   23
 172 #define MX2x_DMA_REQ_UART2_RX   24
 173 #define MX2x_DMA_REQ_UART2_TX   25
 174 #define MX2x_DMA_REQ_UART1_RX   26
 175 #define MX2x_DMA_REQ_UART1_TX   27
 176 #define MX2x_DMA_REQ_CSI_STAT   30
 177 #define MX2x_DMA_REQ_CSI_RX     31
 178
 179 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
 180 /* these should go away */
 181 #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
 182 #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
 183 #define AIPI_SIZE MX2x_AIPI_SIZE
 184 #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
 185 #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
 186 #define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
 187 #define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
 188 #define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
 189 #define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
 190 #define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
 191 #define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
 192 #define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
 193 #define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
 194 #define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
 195 #define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
 196 #define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
 197 #define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
 198 #define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
 199 #define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
 200 #define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
 201 #define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
 202 #define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
 203 #define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
 204 #define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
 205 #define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
 206 #define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
 207 #define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
 208 #define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
 209 #define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
 210 #define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
 211 #define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
 212 #define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
 213 #define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
 214 #define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
 215 #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
 216 #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
 217 #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
 218 #define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
 219 #define SAHB1_SIZE MX2x_SAHB1_SIZE
 220 #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
 221 #define MXC_INT_CSPI3 MX2x_INT_CSPI3
 222 #define MXC_INT_GPIO MX2x_INT_GPIO
 223 #define MXC_INT_SDHC2 MX2x_INT_SDHC2
 224 #define MXC_INT_SDHC1 MX2x_INT_SDHC1
 225 #define MXC_INT_I2C MX2x_INT_I2C
 226 #define MXC_INT_SSI2 MX2x_INT_SSI2
 227 #define MXC_INT_SSI1 MX2x_INT_SSI1
 228 #define MXC_INT_CSPI2 MX2x_INT_CSPI2
 229 #define MXC_INT_CSPI1 MX2x_INT_CSPI1
 230 #define MXC_INT_UART4 MX2x_INT_UART4
 231 #define MXC_INT_UART3 MX2x_INT_UART3
 232 #define MXC_INT_UART2 MX2x_INT_UART2
 233 #define MXC_INT_UART1 MX2x_INT_UART1
 234 #define MXC_INT_KPP MX2x_INT_KPP
 235 #define MXC_INT_RTC MX2x_INT_RTC
 236 #define MXC_INT_PWM MX2x_INT_PWM
 237 #define MXC_INT_GPT3 MX2x_INT_GPT3
 238 #define MXC_INT_GPT2 MX2x_INT_GPT2
 239 #define MXC_INT_GPT1 MX2x_INT_GPT1
 240 #define MXC_INT_WDOG MX2x_INT_WDOG
 241 #define MXC_INT_PCMCIA MX2x_INT_PCMCIA
 242 #define MXC_INT_NANDFC MX2x_INT_NANDFC
 243 #define MXC_INT_CSI MX2x_INT_CSI
 244 #define MXC_INT_DMACH0 MX2x_INT_DMACH0
 245 #define MXC_INT_DMACH1 MX2x_INT_DMACH1
 246 #define MXC_INT_DMACH2 MX2x_INT_DMACH2
 247 #define MXC_INT_DMACH3 MX2x_INT_DMACH3
 248 #define MXC_INT_DMACH4 MX2x_INT_DMACH4
 249 #define MXC_INT_DMACH5 MX2x_INT_DMACH5
 250 #define MXC_INT_DMACH6 MX2x_INT_DMACH6
 251 #define MXC_INT_DMACH7 MX2x_INT_DMACH7
 252 #define MXC_INT_DMACH8 MX2x_INT_DMACH8
 253 #define MXC_INT_DMACH9 MX2x_INT_DMACH9
 254 #define MXC_INT_DMACH10 MX2x_INT_DMACH10
 255 #define MXC_INT_DMACH11 MX2x_INT_DMACH11
 256 #define MXC_INT_DMACH12 MX2x_INT_DMACH12
 257 #define MXC_INT_DMACH13 MX2x_INT_DMACH13
 258 #define MXC_INT_DMACH14 MX2x_INT_DMACH14
 259 #define MXC_INT_DMACH15 MX2x_INT_DMACH15
 260 #define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
 261 #define MXC_INT_EMMAPP MX2x_INT_EMMAPP
 262 #define MXC_INT_SLCDC MX2x_INT_SLCDC
 263 #define MXC_INT_LCDC MX2x_INT_LCDC
 264 #define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
 265 #define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
 266 #define DMA_REQ_EXT MX2x_DMA_REQ_EXT
 267 #define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
 268 #define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
 269 #define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
 270 #define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
 271 #define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
 272 #define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
 273 #define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
 274 #define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
 275 #define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
 276 #define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
 277 #define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
 278 #define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
 279 #define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
 280 #define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
 281 #define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
 282 #define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
 283 #define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
 284 #define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
 285 #define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
 286 #define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
 287 #define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
 288 #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
 289 #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
 290 #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
 291 #endif
 292
 293 #endif /* ifndef __MACH_MX2x_H__ */