release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-at91/pm.h

   1 #ifdef CONFIG_ARCH_AT91RM9200
   2 #include <mach/at91rm9200_mc.h>
   3
   4 /*
   5  * The AT91RM9200 goes into self-refresh mode with this command, and will
   6  * terminate self-refresh automatically on the next SDRAM access.
   7  *
   8  * Self-refresh mode is exited as soon as a memory access is made, but we don't
   9  * know for sure when that happens. However, we need to restore the low-power
  10  * mode if it was enabled before going idle. Restoring low-power mode while
  11  * still in self-refresh is "not recommended", but seems to work.
  12  */
  13
  14 static inline u32 sdram_selfrefresh_enable(void)
  15 {
  16         u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
  17
  18         at91_sys_write(AT91_SDRAMC_LPR, 0);
  19         at91_sys_write(AT91_SDRAMC_SRR, 1);
  20         return saved_lpr;
  21 }
  22
  23 #define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
  24
  25 #elif defined(CONFIG_ARCH_AT91CAP9)
  26 #include <mach/at91cap9_ddrsdr.h>
  27
  28
  29 static inline u32 sdram_selfrefresh_enable(void)
  30 {
  31         u32 saved_lpr, lpr;
  32
  33         saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  34
  35         lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
  36         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
  37         return saved_lpr;
  38 }
  39
  40 #define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
  41
  42 #elif defined(CONFIG_ARCH_AT91SAM9G45)
  43 #include <mach/at91sam9_ddrsdr.h>
  44
  45 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  46  * remember.
  47  */
  48 static u32 saved_lpr1;
  49
  50 static inline u32 sdram_selfrefresh_enable(void)
  51 {
  52         /* Those tow values allow us to delay self-refresh activation
  53          * to the maximum. */
  54         u32 lpr0, lpr1;
  55         u32 saved_lpr0;
  56
  57         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  58         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  59         lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  60
  61         saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  62         lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  63         lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  64
  65         /* self-refresh mode now */
  66         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  67         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  68
  69         return saved_lpr0;
  70 }
  71
  72 #define sdram_selfrefresh_disable(saved_lpr0)   \
  73         do { \
  74                 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
  75                 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
  76         } while (0)
  77
  78 #else
  79 #include <mach/at91sam9_sdramc.h>
  80
  81 #ifdef CONFIG_ARCH_AT91SAM9263
  82 #warning Assuming EB1 SDRAM controller is *NOT* used
  83 #endif
  84
  85 static inline u32 sdram_selfrefresh_enable(void)
  86 {
  87         u32 saved_lpr, lpr;
  88
  89         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
  90
  91         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
  92         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
  93         return saved_lpr;
  94 }
  95
  96 #define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
  97
  98 #endif