release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-at91/at91sam926x_time.c

   1 /*
   2  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
   3  *
   4  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
   5  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
   6  * Converted to ClockSource/ClockEvents by David Brownell.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/clockchips.h>
  17
  18 #include <asm/mach/time.h>
  19
  20 #include <mach/at91_pit.h>
  21
  22
  23 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
  24 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
  25
  26 static u32 pit_cycle;           /* write-once */
  27 static u32 pit_cnt;             /* access only w/system irq blocked */
  28
  29
  30 /*
  31  * Clocksource:  just a monotonic counter of MCK/16 cycles.
  32  * We don't care whether or not PIT irqs are enabled.
  33  */
  34 static cycle_t read_pit_clk(struct clocksource *cs)
  35 {
  36         unsigned long flags;
  37         u32 elapsed;
  38         u32 t;
  39
  40         raw_local_irq_save(flags);
  41         elapsed = pit_cnt;
  42         t = at91_sys_read(AT91_PIT_PIIR);
  43         raw_local_irq_restore(flags);
  44
  45         elapsed += PIT_PICNT(t) * pit_cycle;
  46         elapsed += PIT_CPIV(t);
  47         return elapsed;
  48 }
  49
  50 static struct clocksource pit_clk = {
  51         .name           = "pit",
  52         .rating         = 175,
  53         .read           = read_pit_clk,
  54         .shift          = 20,
  55         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  56 };
  57
  58
  59 /*
  60  * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
  61  */
  62 static void
  63 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  64 {
  65         switch (mode) {
  66         case CLOCK_EVT_MODE_PERIODIC:
  67                 /* update clocksource counter */
  68                 pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
  69                 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
  70                                 | AT91_PIT_PITIEN);
  71                 break;
  72         case CLOCK_EVT_MODE_ONESHOT:
  73                 BUG();
  74                 /* FALLTHROUGH */
  75         case CLOCK_EVT_MODE_SHUTDOWN:
  76         case CLOCK_EVT_MODE_UNUSED:
  77                 /* disable irq, leaving the clocksource active */
  78                 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
  79                 break;
  80         case CLOCK_EVT_MODE_RESUME:
  81                 break;
  82         }
  83 }
  84
  85 static struct clock_event_device pit_clkevt = {
  86         .name           = "pit",
  87         .features       = CLOCK_EVT_FEAT_PERIODIC,
  88         .shift          = 32,
  89         .rating         = 100,
  90         .set_mode       = pit_clkevt_mode,
  91 };
  92
  93
  94 /*
  95  * IRQ handler for the timer.
  96  */
  97 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
  98 {
  99         /*
 100          * irqs should be disabled here, but as the irq is shared they are only
 101          * guaranteed to be off if the timer irq is registered first.
 102          */
 103         WARN_ON_ONCE(!irqs_disabled());
 104
 105         /* The PIT interrupt may be disabled, and is shared */
 106         if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
 107                         && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
 108                 unsigned nr_ticks;
 109
 110                 /* Get number of ticks performed before irq, and ack it */
 111                 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
 112                 do {
 113                         pit_cnt += pit_cycle;
 114                         pit_clkevt.event_handler(&pit_clkevt);
 115                         nr_ticks--;
 116                 } while (nr_ticks);
 117
 118                 return IRQ_HANDLED;
 119         }
 120
 121         return IRQ_NONE;
 122 }
 123
 124 static struct irqaction at91sam926x_pit_irq = {
 125         .name           = "at91_tick",
 126         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 127         .handler        = at91sam926x_pit_interrupt
 128 };
 129
 130 static void at91sam926x_pit_reset(void)
 131 {
 132         /* Disable timer and irqs */
 133         at91_sys_write(AT91_PIT_MR, 0);
 134
 135         /* Clear any pending interrupts, wait for PIT to stop counting */
 136         while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
 137                 cpu_relax();
 138
 139         /* Start PIT but don't enable IRQ */
 140         at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 141 }
 142
 143 /*
 144  * Set up both clocksource and clockevent support.
 145  */
 146 static void __init at91sam926x_pit_init(void)
 147 {
 148         unsigned long   pit_rate;
 149         unsigned        bits;
 150
 151         /*
 152          * Use our actual MCK to figure out how many MCK/16 ticks per
 153          * 1/HZ period (instead of a compile-time constant LATCH).
 154          */
 155         pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
 156         pit_cycle = (pit_rate + HZ/2) / HZ;
 157         WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 158
 159         /* Initialize and enable the timer */
 160         at91sam926x_pit_reset();
 161
 162         /*
 163          * Register clocksource.  The high order bits of PIV are unused,
 164          * so this isn't a 32-bit counter unless we get clockevent irqs.
 165          */
 166         pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
 167         bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
 168         pit_clk.mask = CLOCKSOURCE_MASK(bits);
 169         clocksource_register(&pit_clk);
 170
 171         /* Set up irq handler */
 172         setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
 173
 174         /* Set up and register clockevents */
 175         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
 176         pit_clkevt.cpumask = cpumask_of(0);
 177         clockevents_register_device(&pit_clkevt);
 178 }
 179
 180 static void at91sam926x_pit_suspend(void)
 181 {
 182         /* Disable timer */
 183         at91_sys_write(AT91_PIT_MR, 0);
 184 }
 185
 186 struct sys_timer at91sam926x_timer = {
 187         .init           = at91sam926x_pit_init,
 188         .suspend        = at91sam926x_pit_suspend,
 189         .resume         = at91sam926x_pit_reset,
 190 };