release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/carmel/include/carmel.h

   1 /*  *********************************************************************
   2     *  SB1125 Board Support Package
   3     *
   4     *  Carmel Board definitions                 File: carmel.h
   5     *
   6     *  This file contains I/O, chip select, and GPIO assignments
   7     *  for the CARMEL (BCM1120) board.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *           Binh Vo (binh@broadcom.com)
  11     *
  12     *********************************************************************
  13     *
  14     *  Copyright 2000,2001,2002,2003
  15     *  Broadcom Corporation. All rights reserved.
  16     *
  17     *  This software is furnished under license and may be used and
  18     *  copied only in accordance with the following terms and
  19     *  conditions.  Subject to these conditions, you may download,
  20     *  copy, install, use, modify and distribute modified or unmodified
  21     *  copies of this software in source and/or binary form.  No title
  22     *  or ownership is transferred hereby.
  23     *
  24     *  1) Any source code used, modified or distributed must reproduce
  25     *     and retain this copyright notice and list of conditions
  26     *     as they appear in the source file.
  27     *
  28     *  2) No right is granted to use any trade name, trademark, or
  29     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  30     *     name may not be used to endorse or promote products derived
  31     *     from this software without the prior written permission of
  32     *     Broadcom Corporation.
  33     *
  34     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  35     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  36     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  37     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  38     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  39     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  40     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  41     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  42     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  43     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  44     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  45     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  46     *     THE POSSIBILITY OF SUCH DAMAGE.
  47     ********************************************************************* */
  48
  49
  50 /*
  51  * I/O Address assignments for the carmel board
  52  *
  53  * Summary of address map:
  54  *
  55  * Address         Size   CSel    Description
  56  * --------------- ----   ------  --------------------------------
  57  * 0x1FC00000      16MB    CS0    Boot ROM
  58  * 0x100F0000      64KB    CS1    A/D converters on FPGA
  59  * 0x100C0000      64KB    CS2    7-segment LED display
  60  * 0x100A0000      64KB    CS3    4-char LED display on Monterey
  61  * 0x100D0000      64KB    CS4    Quad UART
  62  * 0x11000000      128MB   CS5    FPGA on Monterey/LittleSur/BigSur
  63  * 0x100B0000      64KB    CS6    CompactFlash
  64  * 0x100E0000      64KB    CS7    FPGA (for JTAG region)
  65  *
  66  * GPIO assignments
  67  *
  68  * GPIO#    Direction   Description
  69  * -------  ---------   ------------------------------------------
  70  * GPIO0    Input       Not used
  71  * GPIO1    Input       Not used
  72  * GPIO2    Input       PHY Interrupt               (interrupt)
  73  * GPIO3    Input       Nonmaskable Interrupt       (interrupt)
  74  * GPIO4    Input       Not used
  75  * GPIO5    Input       Not used
  76  * GPIO6    Input       CF Inserted (high = inserted)
  77  * GPIO7    Output      Monterey Reset (active low)
  78  * GPIO8    Input       Quad UART Interrupt         (interrupt)
  79  * GPIO9    Input       CF Interrupt                (interrupt)
  80  * GPIO10   Output      FPGA CCLK
  81  * GPIO11   Input       FPGA DOUT
  82  * GPIO12   Output      FPGA DIN
  83  * GPIO13   Output      FPGA PGM
  84  * GPIO14   Input       FPGA DONE
  85  * GPIO15   Output      FPGA INIT
  86  */
  87
  88 /*  *********************************************************************
  89     *  Macros
  90     ********************************************************************* */
  91
  92 #define MB (1024*1024)
  93 #define K64 65536
  94 #define NUM64K(x) (((x)+(K64-1))/K64)
  95
  96
  97 /*  *********************************************************************
  98     *  GPIO pins
  99     ********************************************************************* */
 100
 101 #define GPIO_PHY_INTERRUPT      2
 102 #define GPIO_NONMASKABLE_INT    3
 103 #define GPIO_CF_INSERTED        6
 104 #define GPIO_MONTEREY_RESET     7
 105 #define GPIO_QUADUART_INT       8
 106 #define GPIO_CF_INT             9
 107
 108 #define GPIO_FPGA_CCLK          10      /* output */
 109 #define GPIO_FPGA_DOUT          11      /* input */
 110 #define GPIO_FPGA_DIN           12      /* output */
 111 #define GPIO_FPGA_PGM           13      /* output */
 112 #define GPIO_FPGA_DONE          14      /* input */
 113 #define GPIO_FPGA_INIT          15      /* output */
 114
 115 #define GPIO_FPGACONV_CCLK      10
 116 #define GPIO_FPGACONV_DIN       12
 117 #define GPIO_FPGACONV_PGM       5
 118 #define GPIO_FPGACONV_DONE      14
 119 #define GPIO_FPGACONV_INIT      15
 120
 121 #define M_GPIO_PHY_INTERRUPT    _SB_MAKEMASK1(GPIO_PHY_INTERRUPT)
 122 #define M_GPIO_NONMASKABLE_INT  _SB_MAKEMASK1(GPIO_NONMASKABLE_INT)
 123 #define M_GPIO_CF_INSERTED      _SB_MAKEMASK1(GPIO_CF_INSERTED)
 124 #define M_GPIO_MONTEREY_RESET   _SB_MAKEMASK1(GPIO_MONTEREY_RESET)
 125 #define M_GPIO_QUADUART_INT     _SB_MAKEMASK1(GPIO_QUADUART_INT)
 126 #define M_GPIO_CF_INT           _SB_MAKEMASK1(GPIO_CF_INT)
 127
 128 #define M_GPIO_FPGA_CCLK        _SB_MAKEMASK1(GPIO_FPGA_CCLK)
 129 #define M_GPIO_FPGA_DOUT        _SB_MAKEMASK1(GPIO_FPGA_DOUT)
 130 #define M_GPIO_FPGA_DIN         _SB_MAKEMASK1(GPIO_FPGA_DIN)
 131 #define M_GPIO_FPGA_PGM         _SB_MAKEMASK1(GPIO_FPGA_PGM)
 132 #define M_GPIO_FPGA_DONE        _SB_MAKEMASK1(GPIO_FPGA_DONE)
 133 #define M_GPIO_FPGA_INIT        _SB_MAKEMASK1(GPIO_FPGA_INIT)
 134
 135 #define M_GPIO_FPGACONV_CCLK    _SB_MAKEMASK1(GPIO_FPGACONV_CCLK)
 136 #define M_GPIO_FPGACONV_DIN     _SB_MAKEMASK1(GPIO_FPGACONV_DIN)
 137 #define M_GPIO_FPGACONV_PGM     _SB_MAKEMASK1(GPIO_FPGACONV_PGM)
 138 #define M_GPIO_FPGACONV_DONE    _SB_MAKEMASK1(GPIO_FPGACONV_DONE)
 139 #define M_GPIO_FPGACONV_INIT    _SB_MAKEMASK1(GPIO_FPGACONV_INIT)
 140
 141
 142 #define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
 143                              (V_GPIO_INTR_TYPEX(GPIO_QUADUART_INT,K_GPIO_INTR_LEVEL)))
 144
 145 #define GPIO_INVERT_MASK (M_GPIO_QUADUART_INT)
 146
 147 #define GPIO_OUTPUT_MASK (M_GPIO_MONTEREY_RESET)
 148 /* | M_GPIO_FPGA_CCLK | M_GPIO_FPGA_DIN | \
 149                           M_GPIO_FPGA_PGM | M_GPIO_FPGA_INIT)
 150 */
 151
 152
 153 /*  *********************************************************************
 154     *  Generic Bus
 155     ********************************************************************* */
 156
 157 #define BOOTROM_CS              0
 158 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 159 #define BOOTROM_SIZE            NUM64K(16*MB)   /* size of boot ROM */
 160 #define BOOTROM_TIMING0         V_IO_ALE_WIDTH(4) | \
 161                                 V_IO_ALE_TO_CS(2) | \
 162                                 V_IO_CS_WIDTH(24) | \
 163                                 V_IO_RDY_SMPLE(1)
 164 #define BOOTROM_TIMING1         V_IO_ALE_TO_WRITE(7) | \
 165                                 V_IO_WRITE_WIDTH(7) | \
 166                                 V_IO_IDLE_CYCLE(6) | \
 167                                 V_IO_CS_TO_OE(0) | \
 168                                 V_IO_OE_TO_CS(0)
 169 #define BOOTROM_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 170
 171
 172 /*
 173  * ADC: non-multiplexed, word(16) width, no parity, ack mode
 174  */
 175 #define ADC_CS                  1
 176 #define ADC_PHYS                0x100F0000
 177 #define ADC_SIZE                NUM64K(65536)
 178 #define ADC_TIMING0             V_IO_ALE_WIDTH(3) | \
 179                                 V_IO_ALE_TO_CS(1) | \
 180                                 V_IO_CS_WIDTH(8) | \
 181                                 V_IO_RDY_SMPLE(2)
 182 #define ADC_TIMING1             V_IO_ALE_TO_WRITE(4) | \
 183                                 V_IO_WRITE_WIDTH(0xA) | \
 184                                 V_IO_IDLE_CYCLE(1) | \
 185                                 V_IO_CS_TO_OE(3) | \
 186                                 V_IO_OE_TO_CS(2)
 187 #define ADC_CONFIG              V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \
 188                                 M_IO_RDY_ACTIVE | \
 189                                 M_IO_ENA_RDY
 190
 191
 192
 193 /*
 194  * LEDs:  non-multiplexed, byte width, no parity, no ack
 195  */
 196 #define LEDS_CS                 2
 197 #define LEDS_PHYS               0x100C0000
 198 #define LEDS_SIZE               NUM64K(4)
 199 #define LEDS_TIMING0            V_IO_ALE_WIDTH(4) | \
 200                                 V_IO_ALE_TO_CS(2) | \
 201                                 V_IO_CS_WIDTH(13) | \
 202                                 V_IO_RDY_SMPLE(1)
 203 #define LEDS_TIMING1            V_IO_ALE_TO_WRITE(2) | \
 204                                 V_IO_WRITE_WIDTH(8) | \
 205                                 V_IO_IDLE_CYCLE(6) | \
 206                                 V_IO_CS_TO_OE(0) | \
 207                                 V_IO_OE_TO_CS(0)
 208 #define LEDS_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 209
 210
 211 /*
 212  * MLEDs:  non-multiplexed, byte width, no parity, no ack
 213  * This is the LED display on the Monterey board.
 214  */
 215 #define MLEDS_CS                3
 216 #define MLEDS_PHYS              0x100A0000      /* same address as SWARM */
 217 #define MLEDS_SIZE              NUM64K(4)
 218 #define MLEDS_TIMING0           V_IO_ALE_WIDTH(4) | \
 219                                 V_IO_ALE_TO_CS(2) | \
 220                                 V_IO_CS_WIDTH(13) | \
 221                                 V_IO_RDY_SMPLE(1)
 222 #define MLEDS_TIMING1           V_IO_ALE_TO_WRITE(2) | \
 223                                 V_IO_WRITE_WIDTH(8) | \
 224                                 V_IO_IDLE_CYCLE(6) | \
 225                                 V_IO_CS_TO_OE(0) | \
 226                                 V_IO_OE_TO_CS(0)
 227 #define MLEDS_CONFIG            V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 228
 229 /*
 230  * Quad UART:  non-multiplexed, byte width, no parity, no ack
 231  * This is the Exar quad uart on the Monterey board.
 232  */
 233
 234 #define UART_CS                 4
 235 #define UART_PHYS               0x100D0000
 236 #define UART_SIZE               NUM64K(32)
 237 #define UART_TIMING0            V_IO_ALE_WIDTH(4) | \
 238                                 V_IO_ALE_TO_CS(2) | \
 239                                 V_IO_CS_WIDTH(24) | \
 240                                 V_IO_RDY_SMPLE(1)
 241 #define UART_TIMING1            V_IO_ALE_TO_WRITE(7) | \
 242                                 V_IO_WRITE_WIDTH(7) | \
 243                                 V_IO_IDLE_CYCLE(6) | \
 244                                 V_IO_CS_TO_OE(0) | \
 245                                 V_IO_OE_TO_CS(0)
 246 #define UART_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 247
 248
 249 /*
 250  * ARAVALI:  multiplexed, 8-bit width, no parity, ack
 251  * 128MB region
 252  */
 253 #define ARAVALI_CS              5
 254 #define ARAVALI_PHYS            0x11000000
 255 #define ARAVALI_SIZE            NUM64K(128*1024*1024)
 256 #define ARAVALI_TIMING0         V_IO_ALE_WIDTH(4) | \
 257                                 V_IO_ALE_TO_CS(2) | \
 258                                 V_IO_CS_WIDTH(6) | \
 259                                 V_IO_RDY_SMPLE(1)
 260 #define ARAVALI_TIMING1         V_IO_ALE_TO_WRITE(2) | \
 261                                 V_IO_WRITE_WIDTH(8) | \
 262                                 V_IO_IDLE_CYCLE(6) | \
 263                                 V_IO_CS_TO_OE(0) | \
 264                                 V_IO_OE_TO_CS(0)
 265 #define ARAVALI_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_ENA_RDY | V_IO_TIMEOUT(8)
 266
 267
 268 /*
 269  * IDE: non-multiplexed, word(16) width, no parity, ack mode
 270  * See BCM12500 Application Note: "BCM12500 Generic Bus Interface
 271  * to ATA/ATAPI PIO Mode 3 (IDE) Hard Disk"
 272  */
 273 #define IDE_CS                  6
 274 #define IDE_PHYS                0x100B0000      /* same address as SWARM */
 275 #define IDE_SIZE                NUM64K(256)
 276 #define IDE_TIMING0             V_IO_ALE_WIDTH(3) | \
 277                                 V_IO_ALE_TO_CS(1) | \
 278                                 V_IO_CS_WIDTH(8) | \
 279                                 V_IO_RDY_SMPLE(2)
 280 #define IDE_TIMING1             V_IO_ALE_TO_WRITE(4) | \
 281                                 V_IO_WRITE_WIDTH(0xA) | \
 282                                 V_IO_IDLE_CYCLE(1) | \
 283                                 V_IO_CS_TO_OE(3) | \
 284                                 V_IO_OE_TO_CS(2)
 285 #define IDE_CONFIG              V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \
 286                                 M_IO_RDY_ACTIVE | \
 287                                 M_IO_ENA_RDY
 288
 289
 290
 291 /*
 292  * ARAVALI2: (JTAG region)  multiplexed, 32-bit width, no parity, ack
 293  * 64KB region
 294  */
 295 #define ARAVALI2_CS             7
 296 #define ARAVALI2_PHYS           0x100E0000
 297 #define ARAVALI2_SIZE           NUM64K(65536)
 298 #define ARAVALI2_TIMING0        V_IO_ALE_WIDTH(4) | \
 299                                 V_IO_ALE_TO_CS(2) | \
 300                                 V_IO_CS_WIDTH(6) | \
 301                                 V_IO_RDY_SMPLE(1)
 302 #define ARAVALI2_TIMING1        V_IO_ALE_TO_WRITE(2) | \
 303                                 V_IO_WRITE_WIDTH(8) | \
 304                                 V_IO_IDLE_CYCLE(6) | \
 305                                 V_IO_CS_TO_OE(0) | \
 306                                 V_IO_OE_TO_CS(0)
 307 #define ARAVALI2_CONFIG         V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_4) | M_IO_ENA_RDY | V_IO_TIMEOUT(8)
 308
 309
 310
 311
 312 /*  *********************************************************************
 313     *  SMBus Devices
 314     ********************************************************************* */
 315
 316 /*
 317  * SMBus 0
 318  */
 319
 320 #define SPDEEPROM_SMBUS_CHAN    0               /* SPD for memory chips */
 321 #define SPDEEPROM_SMBUS_DEV     0x54
 322
 323 #define ENVEEPROM_SMBUS_CHAN    0               /* CFE's environment */
 324 #define ENVEEPROM_SMBUS_DEV     0x50
 325
 326 #define IDEEPROM_SMBUS_CHAN     0               /* On Monterey board */
 327 #define IDEEPROM_SMBUS_CHAN_ALT 1               /* On LittleSur board */
 328 #define IDEEPROM_SMBUS_DEV      0x51