2 * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
5 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * $Id: sbsdpcmdev.h,v 13.38 2009-09-22 22:56:45 Exp $
22 #ifndef _sbsdpcmdev_h_
23 #define _sbsdpcmdev_h_
25 /* cpp contortions to concatenate w/arg prescan */
27 #define _PADLINE(line) pad ## line
28 #define _XSTR(line) _PADLINE(line)
29 #define PAD _XSTR(__LINE__)
33 typedef volatile struct {
34 dma64regs_t xmt
; /* dma tx */
36 dma64regs_t rcv
; /* dma rx */
40 /* dma64 sdiod corerev >= 1 */
41 typedef volatile struct {
42 dma64p_t dma64regs
[2];
43 dma64diag_t dmafifo
; /* DMA Diagnostic Regs, 0x280-0x28c */
47 /* dma32 sdiod corerev == 0 */
48 typedef volatile struct {
49 dma32regp_t dma32regs
[2]; /* dma tx & rx, 0x200-0x23c */
50 dma32diag_t dmafifo
; /* DMA Diagnostic Regs, 0x240-0x24c */
54 /* dma32 regs for pcmcia core */
55 typedef volatile struct {
56 dma32regp_t dmaregs
; /* DMA Regs, 0x200-0x21c, rev8 */
57 dma32diag_t dmafifo
; /* DMA Diagnostic Regs, 0x220-0x22c */
62 typedef volatile struct {
63 uint32 corecontrol
; /* CoreControl, 0x000, rev8 */
64 uint32 corestatus
; /* CoreStatus, 0x004, rev8 */
66 uint32 biststatus
; /* BistStatus, 0x00c, rev8 */
69 uint16 pcmciamesportaladdr
; /* PcmciaMesPortalAddr, 0x010, rev8 */
71 uint16 pcmciamesportalmask
; /* PcmciaMesPortalMask, 0x014, rev8 */
73 uint16 pcmciawrframebc
; /* PcmciaWrFrameBC, 0x018, rev8 */
75 uint16 pcmciaunderflowtimer
; /* PcmciaUnderflowTimer, 0x01c, rev8 */
79 uint32 intstatus
; /* IntStatus, 0x020, rev8 */
80 uint32 hostintmask
; /* IntHostMask, 0x024, rev8 */
81 uint32 intmask
; /* IntSbMask, 0x028, rev8 */
82 uint32 sbintstatus
; /* SBIntStatus, 0x02c, rev8 */
83 uint32 sbintmask
; /* SBIntMask, 0x030, rev8 */
84 uint32 funcintmask
; /* SDIO Function Interrupt Mask, SDIO rev4 */
86 uint32 tosbmailbox
; /* ToSBMailbox, 0x040, rev8 */
87 uint32 tohostmailbox
; /* ToHostMailbox, 0x044, rev8 */
88 uint32 tosbmailboxdata
; /* ToSbMailboxData, 0x048, rev8 */
89 uint32 tohostmailboxdata
; /* ToHostMailboxData, 0x04c, rev8 */
91 /* synchronized access to registers in SDIO clock domain */
92 uint32 sdioaccess
; /* SdioAccess, 0x050, rev8 */
95 /* PCMCIA frame control */
96 uint8 pcmciaframectrl
; /* pcmciaFrameCtrl, 0x060, rev8 */
98 uint8 pcmciawatermark
; /* pcmciaWaterMark, 0x064, rev8 */
101 /* interrupt batching control */
102 uint32 intrcvlazy
; /* IntRcvLazy, 0x100, rev8 */
106 uint32 cmd52rd
; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
107 uint32 cmd52wr
; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
108 uint32 cmd53rd
; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
109 uint32 cmd53wr
; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
110 uint32 abort
; /* AbortCount, 0x120, rev8, SDIO: aborts */
111 uint32 datacrcerror
; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
112 uint32 rdoutofsync
; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
113 uint32 wroutofsync
; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
114 uint32 writebusy
; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
115 uint32 readwait
; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
116 uint32 readterm
; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
117 uint32 writeterm
; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
119 uint32 clockctlstatus
; /* ClockCtlStatus, 0x1e0, rev8 */
129 /* SDIO/PCMCIA CIS region */
130 char cis
[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
132 /* PCMCIA function control registers */
133 char pcmciafcr
[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
136 /* PCMCIA backplane access */
137 uint16 backplanecsr
; /* BackplaneCSR, 0x76E, rev6 */
138 uint16 backplaneaddr0
; /* BackplaneAddr0, 0x770, rev6 */
139 uint16 backplaneaddr1
; /* BackplaneAddr1, 0x772, rev6 */
140 uint16 backplaneaddr2
; /* BackplaneAddr2, 0x774, rev6 */
141 uint16 backplaneaddr3
; /* BackplaneAddr3, 0x776, rev6 */
142 uint16 backplanedata0
; /* BackplaneData0, 0x778, rev6 */
143 uint16 backplanedata1
; /* BackplaneData1, 0x77a, rev6 */
144 uint16 backplanedata2
; /* BackplaneData2, 0x77c, rev6 */
145 uint16 backplanedata3
; /* BackplaneData3, 0x77e, rev6 */
148 /* sprom "size" & "blank" info */
149 uint16 spromstatus
; /* SPROMStatus, 0x7BE, rev2 */
152 /* Sonics SiliconBackplane registers */
153 sbconfig_t sbconfig
; /* SbConfig Regs, 0xf00-0xfff, rev8 */
157 #define CC_CISRDY (1 << 0) /* CIS Ready */
158 #define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
159 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
160 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
161 #define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */
162 #define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */
165 #define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
166 #define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
167 #define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
169 #define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
170 #define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
171 #define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
172 #define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
175 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
176 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
177 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
178 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
179 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
180 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
181 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
182 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
183 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
184 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
185 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
186 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
187 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
188 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
189 #define I_PC (1 << 10) /* descriptor error */
190 #define I_PD (1 << 11) /* data error */
191 #define I_DE (1 << 12) /* Descriptor protocol Error */
192 #define I_RU (1 << 13) /* Receive descriptor Underflow */
193 #define I_RO (1 << 14) /* Receive fifo Overflow */
194 #define I_XU (1 << 15) /* Transmit fifo Underflow */
195 #define I_RI (1 << 16) /* Receive Interrupt */
196 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
197 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
198 #define I_XI (1 << 24) /* Transmit Interrupt */
199 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
200 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
201 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
202 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
203 #define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
204 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
205 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
206 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
207 #define I_DMA (I_RI | I_XI | I_ERRORS)
210 #define I_SB_SERR (1 << 8) /* Backplane SError (write) */
211 #define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
212 #define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
215 #define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
216 #define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
217 #define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
218 #define SDA_WRITE 0x01000000 /* Write bit */
219 #define SDA_READ 0x00000000 /* Write bit cleared for Read */
220 #define SDA_BUSY 0x80000000 /* Busy bit */
222 /* sdioaccess-accessible register address spaces */
223 #define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
224 #define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
225 #define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
226 #define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
228 /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
229 #define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
230 #define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
231 #define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
232 #define SDA_DEVICECONTROL 0x009 /* DeviceControl */
233 #define SDA_SBADDRLOW 0x00a /* SbAddrLow */
234 #define SDA_SBADDRMID 0x00b /* SbAddrMid */
235 #define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
236 #define SDA_FRAMECTRL 0x00d /* FrameCtrl */
237 #define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
238 #define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
239 #define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
240 #define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
241 #define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
242 #define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
244 /* SDA_F2WATERMARK */
245 #define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
248 #define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
251 #define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
254 #define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
257 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
258 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
259 #define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
260 #define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
262 /* pcmciaframectrl */
263 #define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
264 #define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
267 #define IRL_TO_MASK 0x00ffffff /* timeout */
268 #define IRL_FC_MASK 0xff000000 /* frame count */
269 #define IRL_FC_SHIFT 24 /* frame count */
272 typedef volatile struct {
277 /* rx header flags */
278 #define RXF_CRC 0x0001 /* CRC error detected */
279 #define RXF_WOOS 0x0002 /* write frame out of sync */
280 #define RXF_WF_TERM 0x0004 /* write frame terminated */
281 #define RXF_ABORT 0x0008 /* write frame aborted */
282 #define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
285 #define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
287 #endif /* _sbsdpcmdev_h_ */