2 * au1550_i2s.c -- Sound driver for Alchemy Au1550 MIPS
3 * Internet Edge Processor.
5 * Copyright 2004 Embedded Edge, LLC
7 * Copyright 2005 Matt Porter <mporter@kernel.crashing.org>
9 * Mostly copied from the au1550_psc.c driver and some from the
10 * PowerMac dbdma driver.
11 * We assume the processor can do memory coherent DMA.
13 * WM8731 mixer support, codec framework, cleanup, and 2.6 port
14 * Matt Porter <mporter@kernel.crashing.org>
16 * The SMBus (I2C) is required for the control of the
17 * appears at I2C address 0x36 (I2C binary 0011011). The Pb1550
18 * uses the Wolfson WM8731 codec, which is controlled over the I2C.
19 * It's connected to a 12MHz clock, so we can only reliably support
20 * 96KHz, 48KHz, 32KHz, and 8KHz data rates. Variable rate audio is
21 * unsupported, we currently force it to 48KHz.
23 * This program is free software; you can redistribute it and/or modify it
24 * under the terms of the GNU General Public License as published by the
25 * Free Software Foundation; either version 2 of the License, or (at your
26 * option) any later version.
28 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
31 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
34 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * You should have received a copy of the GNU General Public License along
40 * with this program; if not, write to the Free Software Foundation, Inc.,
41 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 #include <linux/module.h>
45 #include <linux/string.h>
46 #include <linux/ioport.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
50 #include <linux/hardirq.h>
51 #include <linux/sound.h>
52 #include <linux/slab.h>
53 #include <linux/soundcard.h>
54 #include <linux/init.h>
55 #include <linux/poll.h>
56 #include <linux/pci.h>
57 #include <linux/bitops.h>
58 #include <linux/proc_fs.h>
59 #include <linux/spinlock.h>
60 #include <linux/smp_lock.h>
63 #include <asm/uaccess.h>
64 #include <asm/hardirq.h>
66 #include <asm/mach-au1x00/au1000.h>
67 #include <asm/mach-au1x00/au1xxx_psc.h>
68 #include <asm/mach-au1x00/au1xxx_dbdma.h>
69 #include <asm/mach-pb1x00/pb1550.h>
71 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
73 #define AU1550_MODULE_NAME "Au1550 I2S Audio"
74 #define PFX AU1550_MODULE_NAME
76 /* Define this if you want to try running at the 44.1 KHz rate.
77 * It's just a little off, I think it's actually 44117 or something.
78 * I did this for debugging, since many programs, including this
79 * driver, will try to upsample from 44.1 to 48 KHz.
80 * Seems to work well, we'll just leave it this way.
85 #define SAMP_RATE 44100
87 #define SAMP_RATE 48000
90 /* The number of DBDMA ring descriptors to allocate. No sense making
91 * this too large....if you can't keep up with a few you aren't likely
92 * to be able to with lots of them, either.
94 #define NUM_DBDMA_DESCRIPTORS 4
96 #define pr_error(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
99 au1550_delay(int msec
)
107 tmo
= jiffies
+ (msec
* HZ
) / 1000;
109 tmo2
= tmo
- jiffies
;
112 schedule_timeout(tmo2
);
117 * Codec framework. If somebody supports another codec, they
118 * should hopefully be able to define another struct i2s_codec
119 * definition, and #ifdef the support for it and the WM8731 so
120 * they can be selected via a CONFIG option. For now, we just
121 * hardcode WM8731_CODEC.
123 #define i2s_supported_mixer(CODEC,FOO) ((FOO >= 0) && \
124 (FOO < SOUND_MIXER_NRDEVICES) && \
125 (CODEC)->supported_mixers & (1<<FOO) )
129 int supported_mixers
;
132 unsigned int mixer_state
[SOUND_MIXER_NRDEVICES
];
134 int (*set_mixer
) (struct i2s_codec
*codec
, unsigned int oss_mixer
, unsigned int val
);
135 void (*init_codec
) (struct i2s_codec
*codec
);
141 * WM8731 codec support
143 #define WM8731_SUPPORTED_MASK (WM8731_STEREO_MASK|WM8731_RECORD_MASK)
144 #define WM8731_STEREO_MASK (SOUND_MASK_VOLUME|SOUND_MASK_LINE)
145 #define WM8731_RECORD_MASK (SOUND_MASK_MIC|SOUND_MASK_LINE)
147 static struct codec_data
{
152 wm8731_wrcodec(u8 ctlreg
, u8 val
)
155 extern int pb1550_wm_codec_write(u8 addr
, u8 reg
, u8 val
);
157 /* The codec is a write only device, with a 16-bit control/data
158 * word. Although it is written as two bytes on the I2C, the
159 * format is actually 7 bits of register and 9 bits of data.
160 * The ls bit of the first byte is the ms bit of the data.
163 while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg
, val
) != 1)
170 wm8731_set_mixer(struct i2s_codec
*codec
, unsigned int oss_mixer
, unsigned int val
)
172 unsigned int lvol
, rvol
;
173 struct codec_data
*cdata
= (struct codec_data
*)codec
->data
;
176 case SOUND_MIXER_VOLUME
:
177 /* normalize OSS range to fit codec volume control */
178 lvol
= ((((val
& 0x7f00) >> 8) * 0x60) / 0x64) + 0x1f;
179 rvol
= (((val
& 0x7f) * 0x60) / 0x64) + 0x1f;
182 wm8731_wrcodec(0x04, lvol
);
184 wm8731_wrcodec(0x06, rvol
);
186 codec
->mixer_state
[oss_mixer
] = val
;
188 case SOUND_MIXER_LINE
:
189 /* normalize OSS range to fit codec line control */
190 lvol
= ((((val
& 0x7f00) >> 8) * 0x1f) / 0x64);
191 rvol
= (((val
& 0x7f) * 0x1f) / 0x64);
200 wm8731_wrcodec(0x00, lvol
);
202 wm8731_wrcodec(0x02, rvol
);
204 codec
->mixer_state
[oss_mixer
] = val
;
206 case SOUND_MIXER_MIC
:
208 cdata
->audio_path
|= 0x02;
211 cdata
->audio_path
|= 0x01;
213 cdata
->audio_path
&= ~0x01;
214 cdata
->audio_path
&= ~0x02;
216 wm8731_wrcodec(0x08, cdata
->audio_path
);
218 codec
->mixer_state
[oss_mixer
] = val
;
220 case SOUND_MIXER_RECSRC
:
221 if (val
& SOUND_MASK_LINE
)
222 cdata
->audio_path
&= ~0x04;
224 cdata
->audio_path
|= 0x04;
225 wm8731_wrcodec(0x08, cdata
->audio_path
);
227 codec
->mixer_state
[oss_mixer
] = val
;
237 wm8731_init_codec(struct i2s_codec
*codec
)
239 struct codec_data
*cdata
= (struct codec_data
*)codec
->data
;
241 wm8731_wrcodec(0x1e, 0x00); /* Reset */
243 wm8731_wrcodec(0x0c, 0x00); /* Power up everything */
245 wm8731_wrcodec(0x12, 0x00); /* Deactivate codec */
247 cdata
->audio_path
= 0x10;
248 /* Select DAC outputs to line out */
249 wm8731_wrcodec(0x08, cdata
->audio_path
);
251 wm8731_wrcodec(0x0a, 0x00); /* Disable output mute */
253 wm8731_wrcodec(0x0e, 0x02); /* Set slave, 16-bit, I2S modes */
255 wm8731_wrcodec(0x10, 0x01); /* 12MHz (USB), 250fs */
257 wm8731_wrcodec(0x12, 0x01); /* Activate codec */
260 codec
->set_mixer(codec
, SOUND_MIXER_VOLUME
, 0x5050);
261 codec
->set_mixer(codec
, SOUND_MIXER_LINE
, 0x0000);
262 codec
->set_mixer(codec
, SOUND_MIXER_MIC
, 0x00);
263 codec
->mixer_state
[SOUND_MIXER_RECSRC
] = SOUND_MIXER_LINE
;
266 static struct i2s_codec au1550_i2s_codec
= {
267 .supported_mixers
= WM8731_SUPPORTED_MASK
,
268 .stereo_mixers
= WM8731_STEREO_MASK
,
269 .record_sources
= WM8731_RECORD_MASK
,
270 .init_codec
= &wm8731_init_codec
,
271 .set_mixer
= &wm8731_set_mixer
,
272 .data
= &wm8731_data
,
274 #endif /* WM8731_CODEC */
276 static struct au1550_state
{
277 /* soundcore stuff */
282 struct semaphore open_sem
;
283 struct semaphore sem
;
285 wait_queue_head_t open_wait
;
286 volatile psc_i2s_t
*psc_addr
;
287 struct i2s_codec
*codec
;
291 unsigned sample_rate
;
293 unsigned sample_size
;
295 int dma_bytes_per_sample
;
296 int user_bytes_per_sample
;
306 unsigned total_bytes
;
308 wait_queue_head_t wait
;
310 /* redundant, but makes calculations easier */
312 unsigned dma_fragsize
;
320 unsigned ossfragshift
;
322 unsigned subdivision
;
355 /* stop the ADC before calling */
357 set_adc_rate(struct au1550_state
*s
, unsigned rate
)
359 struct dmabuf
*adc
= &s
->dma_adc
;
361 /* calc SRC factor */
362 adc
->src_factor
= (((SAMP_RATE
*2) / rate
) + 1) >> 1;
363 adc
->sample_rate
= SAMP_RATE
/ adc
->src_factor
;
369 /* stop the DAC before calling */
371 set_dac_rate(struct au1550_state
*s
, unsigned rate
)
373 struct dmabuf
*dac
= &s
->dma_dac
;
375 /* calc SRC factor */
376 dac
->src_factor
= (((SAMP_RATE
*2) / rate
) + 1) >> 1;
377 dac
->sample_rate
= SAMP_RATE
/ dac
->src_factor
;
384 stop_dac(struct au1550_state
*s
)
386 struct dmabuf
*db
= &s
->dma_dac
;
389 volatile psc_i2s_t
*ip
;
395 spin_lock_irqsave(&s
->lock
, flags
);
397 ip
->psc_i2spcr
= PSC_I2SPCR_TP
;
400 /* Wait for Transmit Busy to show disabled.
403 stat
= ip
->psc_i2sstat
;
405 } while ((stat
& PSC_I2SSTAT_TB
) != 0);
407 au1xxx_dbdma_reset(db
->dmanr
);
411 spin_unlock_irqrestore(&s
->lock
, flags
);
415 stop_adc(struct au1550_state
*s
)
417 struct dmabuf
*db
= &s
->dma_adc
;
420 volatile psc_i2s_t
*ip
;
426 spin_lock_irqsave(&s
->lock
, flags
);
428 ip
->psc_i2spcr
= PSC_I2SPCR_RP
;
431 /* Wait for Receive Busy to show disabled.
434 stat
= ip
->psc_i2sstat
;
436 } while ((stat
& PSC_I2SSTAT_RB
) != 0);
438 au1xxx_dbdma_reset(db
->dmanr
);
442 spin_unlock_irqrestore(&s
->lock
, flags
);
446 set_xmit_slots(int num_channels
)
448 /* This is here just as a place holder. The WM8731 only
449 * supports two fixed channels.
454 set_recv_slots(int num_channels
)
456 /* This is here just as a place holder. The WM8731 only
457 * supports two fixed channels.
462 start_dac(struct au1550_state
*s
)
464 struct dmabuf
*db
= &s
->dma_dac
;
466 volatile psc_i2s_t
*ip
;
471 spin_lock_irqsave(&s
->lock
, flags
);
474 set_xmit_slots(db
->num_channels
);
475 ip
->psc_i2spcr
= PSC_I2SPCR_TC
;
477 ip
->psc_i2spcr
= PSC_I2SPCR_TS
;
480 au1xxx_dbdma_start(db
->dmanr
);
484 spin_unlock_irqrestore(&s
->lock
, flags
);
488 start_adc(struct au1550_state
*s
)
490 struct dmabuf
*db
= &s
->dma_adc
;
492 volatile psc_i2s_t
*ip
;
497 /* Put two buffers on the ring to get things started.
499 for (i
=0; i
<2; i
++) {
500 au1xxx_dbdma_put_dest(db
->dmanr
, db
->nextIn
, db
->dma_fragsize
);
502 db
->nextIn
+= db
->dma_fragsize
;
503 if (db
->nextIn
>= db
->rawbuf
+ db
->dmasize
)
504 db
->nextIn
-= db
->dmasize
;
508 set_recv_slots(db
->num_channels
);
509 au1xxx_dbdma_start(db
->dmanr
);
510 ip
->psc_i2spcr
= PSC_I2SPCR_RC
;
512 ip
->psc_i2spcr
= PSC_I2SPCR_RS
;
519 prog_dmabuf(struct au1550_state
*s
, struct dmabuf
*db
)
521 unsigned user_bytes_per_sec
;
523 unsigned rate
= db
->sample_rate
;
526 db
->ready
= db
->mapped
= 0;
527 db
->buforder
= 5; /* 32 * PAGE_SIZE */
528 db
->rawbuf
= kmalloc((PAGE_SIZE
<< db
->buforder
), GFP_KERNEL
);
534 if (db
->sample_size
== 8)
536 if (db
->num_channels
== 1)
538 db
->cnt_factor
*= db
->src_factor
;
542 db
->nextIn
= db
->nextOut
= db
->rawbuf
;
544 db
->user_bytes_per_sample
= (db
->sample_size
>>3) * db
->num_channels
;
545 db
->dma_bytes_per_sample
= 2 * ((db
->num_channels
== 1) ?
546 2 : db
->num_channels
);
548 user_bytes_per_sec
= rate
* db
->user_bytes_per_sample
;
549 bufs
= PAGE_SIZE
<< db
->buforder
;
550 if (db
->ossfragshift
) {
551 if ((1000 << db
->ossfragshift
) < user_bytes_per_sec
)
552 db
->fragshift
= ld2(user_bytes_per_sec
/1000);
554 db
->fragshift
= db
->ossfragshift
;
556 db
->fragshift
= ld2(user_bytes_per_sec
/ 100 /
557 (db
->subdivision
? db
->subdivision
: 1));
558 if (db
->fragshift
< 3)
562 db
->fragsize
= 1 << db
->fragshift
;
563 db
->dma_fragsize
= db
->fragsize
* db
->cnt_factor
;
564 db
->numfrag
= bufs
/ db
->dma_fragsize
;
566 while (db
->numfrag
< 4 && db
->fragshift
> 3) {
568 db
->fragsize
= 1 << db
->fragshift
;
569 db
->dma_fragsize
= db
->fragsize
* db
->cnt_factor
;
570 db
->numfrag
= bufs
/ db
->dma_fragsize
;
573 if (db
->ossmaxfrags
>= 4 && db
->ossmaxfrags
< db
->numfrag
)
574 db
->numfrag
= db
->ossmaxfrags
;
576 db
->dmasize
= db
->dma_fragsize
* db
->numfrag
;
577 memset(db
->rawbuf
, 0, bufs
);
579 #ifdef AU1000_VERBOSE_DEBUG
580 dbg("rate=%d, samplesize=%d, channels=%d",
581 rate
, db
->sample_size
, db
->num_channels
);
582 dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
583 db
->fragsize
, db
->cnt_factor
, db
->dma_fragsize
);
584 dbg("numfrag=%d, dmasize=%d", db
->numfrag
, db
->dmasize
);
592 prog_dmabuf_adc(struct au1550_state
*s
)
595 return prog_dmabuf(s
, &s
->dma_adc
);
600 prog_dmabuf_dac(struct au1550_state
*s
)
603 return prog_dmabuf(s
, &s
->dma_dac
);
607 /* hold spinlock for the following */
609 dac_dma_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
611 struct au1550_state
*s
= (struct au1550_state
*) dev_id
;
612 struct dmabuf
*db
= &s
->dma_dac
;
614 volatile psc_i2s_t
*ip
;
617 i2s_stat
= ip
->psc_i2sstat
;
618 #ifdef AU1000_VERBOSE_DEBUG
619 if (i2s_stat
& (PSC_I2SSTAT_TF
| PSC_I2SSTAT_TR
| PSC_I2SSTAT_TF
))
620 dbg("I2S status = 0x%08x", i2s_stat
);
624 if (db
->count
>= db
->fragsize
) {
625 if (au1xxx_dbdma_put_source(db
->dmanr
, db
->nextOut
,
626 db
->fragsize
) == 0) {
627 pr_error("qcount < 2 and no ring room!");
629 db
->nextOut
+= db
->fragsize
;
630 if (db
->nextOut
>= db
->rawbuf
+ db
->dmasize
)
631 db
->nextOut
-= db
->dmasize
;
632 db
->count
-= db
->fragsize
;
633 db
->total_bytes
+= db
->dma_fragsize
;
637 /* wake up anybody listening */
638 if (waitqueue_active(&db
->wait
))
644 adc_dma_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
646 struct au1550_state
*s
= (struct au1550_state
*)dev_id
;
647 struct dmabuf
*dp
= &s
->dma_adc
;
651 /* Pull the buffer from the dma queue.
653 au1xxx_dbdma_get_dest(dp
->dmanr
, (void *)(&obuf
), &obytes
);
655 if ((dp
->count
+ obytes
) > dp
->dmasize
) {
656 /* Overrun. Stop ADC and log the error
660 pr_error("adc overrun");
664 /* Put a new empty buffer on the destination DMA.
666 au1xxx_dbdma_put_dest(dp
->dmanr
, dp
->nextIn
, dp
->dma_fragsize
);
668 dp
->nextIn
+= dp
->dma_fragsize
;
669 if (dp
->nextIn
>= dp
->rawbuf
+ dp
->dmasize
)
670 dp
->nextIn
-= dp
->dmasize
;
673 dp
->total_bytes
+= obytes
;
675 /* wake up anybody listening
677 if (waitqueue_active(&dp
->wait
))
683 au1550_llseek(struct file
*file
, loff_t offset
, int origin
)
689 au1550_open_mixdev(struct inode
*inode
, struct file
*file
)
691 file
->private_data
= &au1550_state
;
696 au1550_release_mixdev(struct inode
*inode
, struct file
*file
)
701 #define I2S_CODEC "Wolfson WM8731"
704 au1550_ioctl_mixdev(struct inode
*inode
, struct file
*file
,
705 unsigned int cmd
, unsigned long arg
)
707 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
708 struct i2s_codec
*codec
= s
->codec
;
711 if (cmd
== SOUND_MIXER_INFO
) {
713 memset(&info
, 0, sizeof(info
));
714 strlcpy(info
.id
, I2S_CODEC
, sizeof(info
.id
));
715 strlcpy(info
.name
, I2S_CODEC
, sizeof(info
.name
));
716 info
.modify_counter
= codec
->modcnt
;
717 if (copy_to_user((void __user
*)arg
, &info
, sizeof(info
)))
721 if (cmd
== SOUND_OLD_MIXER_INFO
) {
722 _old_mixer_info info
;
723 memset(&info
, 0, sizeof(info
));
724 strlcpy(info
.id
, I2S_CODEC
, sizeof(info
.id
));
725 strlcpy(info
.name
, I2S_CODEC
, sizeof(info
.name
));
726 if (copy_to_user((void __user
*)arg
, &info
, sizeof(info
)))
731 if (_IOC_TYPE(cmd
) != 'M' || _SIOC_SIZE(cmd
) != sizeof(int))
734 if (cmd
== OSS_GETVERSION
)
735 return put_user(SOUND_VERSION
, (int __user
*)arg
);
737 if (_SIOC_DIR(cmd
) == _SIOC_READ
) {
738 switch (_IOC_NR(cmd
)) {
739 case SOUND_MIXER_RECSRC
: /* give them the current record source */
740 val
= codec
->mixer_state
[SOUND_MIXER_RECSRC
];
743 case SOUND_MIXER_DEVMASK
: /* give them the supported mixers */
744 val
= codec
->supported_mixers
;
747 case SOUND_MIXER_RECMASK
: /* Arg contains a bit for each supported recording source */
748 val
= codec
->record_sources
;
751 case SOUND_MIXER_STEREODEVS
: /* Mixer channels supporting stereo */
752 val
= codec
->stereo_mixers
;
755 case SOUND_MIXER_CAPS
:
756 val
= SOUND_CAP_EXCL_INPUT
;
759 default: /* read a specific mixer */
762 if (!i2s_supported_mixer(codec
, i
))
765 val
= codec
->mixer_state
[i
];
768 return put_user(val
, (int __user
*)arg
);
771 if (_SIOC_DIR(cmd
) == (_SIOC_WRITE
|_SIOC_READ
)) {
773 if (get_user(val
, (int __user
*)arg
))
776 switch (_IOC_NR(cmd
)) {
777 case SOUND_MIXER_RECSRC
: /* Arg contains a bit for each recording source */
779 if (!(val
&= codec
->record_sources
)) return -EINVAL
;
781 codec
->set_mixer(codec
, SOUND_MIXER_RECSRC
, val
);
784 default: /* write a specific mixer */
787 if (!i2s_supported_mixer(codec
, i
))
790 codec
->set_mixer(codec
, i
, val
);
798 static struct file_operations au1550_mixer_fops
= {
800 llseek
:au1550_llseek
,
801 ioctl
:au1550_ioctl_mixdev
,
802 open
:au1550_open_mixdev
,
803 release
:au1550_release_mixdev
,
807 drain_dac(struct au1550_state
*s
, int nonblock
)
812 if (s
->dma_dac
.mapped
|| !s
->dma_dac
.ready
|| s
->dma_dac
.stopped
)
816 spin_lock_irqsave(&s
->lock
, flags
);
817 count
= s
->dma_dac
.count
;
818 spin_unlock_irqrestore(&s
->lock
, flags
);
821 if (signal_pending(current
))
825 tmo
= 1000 * count
/ SAMP_RATE
;
826 tmo
/= s
->dma_dac
.dma_bytes_per_sample
;
829 if (signal_pending(current
))
834 static inline u8
S16_TO_U8(s16 ch
)
836 return (u8
) (ch
>> 8) + 0x80;
838 static inline s16
U8_TO_S16(u8 ch
)
840 return (s16
) (ch
- 0x80) << 8;
844 * Translates user samples to dma buffer suitable for audio DAC data:
845 * If mono, copy left channel to right channel in dma buffer.
846 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
847 * If interpolating (no VRA), duplicate every audio frame src_factor times.
850 translate_from_user(struct dmabuf
*db
, char* dmabuf
, char* userbuf
,
854 int interp_bytes_per_sample
;
856 int mono
= (db
->num_channels
== 1);
858 s16 ch
, dmasample
[6];
860 if (db
->sample_size
== 16 && !mono
&& db
->src_factor
== 1) {
861 /* no translation necessary, just copy
863 if (copy_from_user(dmabuf
, userbuf
, dmacount
))
868 interp_bytes_per_sample
= db
->dma_bytes_per_sample
* db
->src_factor
;
869 num_samples
= dmacount
/ interp_bytes_per_sample
;
871 for (sample
= 0; sample
< num_samples
; sample
++) {
872 if (copy_from_user(usersample
, userbuf
,
873 db
->user_bytes_per_sample
)) {
877 for (i
= 0; i
< db
->num_channels
; i
++) {
878 if (db
->sample_size
== 8)
879 ch
= U8_TO_S16(usersample
[i
]);
881 ch
= *((s16
*) (&usersample
[i
* 2]));
884 dmasample
[i
+ 1] = ch
; /* right channel */
887 /* duplicate every audio frame src_factor times
889 for (i
= 0; i
< db
->src_factor
; i
++)
890 memcpy(dmabuf
, dmasample
, db
->dma_bytes_per_sample
);
892 userbuf
+= db
->user_bytes_per_sample
;
893 dmabuf
+= interp_bytes_per_sample
;
896 return num_samples
* interp_bytes_per_sample
;
900 * Translates audio ADC samples to user buffer:
901 * If mono, send only left channel to user buffer.
902 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
903 * If decimating (no VRA), skip over src_factor audio frames.
906 translate_to_user(struct dmabuf
*db
, char* userbuf
, char* dmabuf
,
910 int interp_bytes_per_sample
;
912 int mono
= (db
->num_channels
== 1);
915 if (db
->sample_size
== 16 && !mono
&& db
->src_factor
== 1) {
916 /* no translation necessary, just copy
918 if (copy_to_user(userbuf
, dmabuf
, dmacount
))
923 interp_bytes_per_sample
= db
->dma_bytes_per_sample
* db
->src_factor
;
924 num_samples
= dmacount
/ interp_bytes_per_sample
;
926 for (sample
= 0; sample
< num_samples
; sample
++) {
927 for (i
= 0; i
< db
->num_channels
; i
++) {
928 if (db
->sample_size
== 8)
930 S16_TO_U8(*((s16
*) (&dmabuf
[i
* 2])));
932 *((s16
*) (&usersample
[i
* 2])) =
933 *((s16
*) (&dmabuf
[i
* 2]));
936 if (copy_to_user(userbuf
, usersample
,
937 db
->user_bytes_per_sample
)) {
941 userbuf
+= db
->user_bytes_per_sample
;
942 dmabuf
+= interp_bytes_per_sample
;
945 return num_samples
* interp_bytes_per_sample
;
949 * Copy audio data to/from user buffer from/to dma buffer, taking care
950 * that we wrap when reading/writing the dma buffer. Returns actual byte
951 * count written to or read from the dma buffer.
954 copy_dmabuf_user(struct dmabuf
*db
, char* userbuf
, int count
, int to_user
)
956 char *bufptr
= to_user
? db
->nextOut
: db
->nextIn
;
957 char *bufend
= db
->rawbuf
+ db
->dmasize
;
960 if (bufptr
+ count
> bufend
) {
961 int partial
= (int) (bufend
- bufptr
);
963 if ((cnt
= translate_to_user(db
, userbuf
,
964 bufptr
, partial
)) < 0)
967 if ((cnt
= translate_to_user(db
, userbuf
+ partial
,
969 count
- partial
)) < 0)
973 if ((cnt
= translate_from_user(db
, bufptr
, userbuf
,
977 if ((cnt
= translate_from_user(db
, db
->rawbuf
,
979 count
- partial
)) < 0)
985 ret
= translate_to_user(db
, userbuf
, bufptr
, count
);
987 ret
= translate_from_user(db
, bufptr
, userbuf
, count
);
994 au1550_read(struct file
*file
, char *buffer
, size_t count
, loff_t
*ppos
)
996 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
997 struct dmabuf
*db
= &s
->dma_adc
;
998 DECLARE_WAITQUEUE(wait
, current
);
1000 unsigned long flags
;
1001 int cnt
, usercnt
, avail
;
1005 if (!access_ok(VERIFY_WRITE
, buffer
, count
))
1009 count
*= db
->cnt_factor
;
1012 add_wait_queue(&db
->wait
, &wait
);
1015 /* wait for samples in ADC dma buffer
1020 spin_lock_irqsave(&s
->lock
, flags
);
1023 __set_current_state(TASK_INTERRUPTIBLE
);
1024 spin_unlock_irqrestore(&s
->lock
, flags
);
1026 if (file
->f_flags
& O_NONBLOCK
) {
1033 if (signal_pending(current
)) {
1040 } while (avail
<= 0);
1042 /* copy from nextOut to user
1044 if ((cnt
= copy_dmabuf_user(db
, buffer
,
1046 avail
: count
, 1)) < 0) {
1052 spin_lock_irqsave(&s
->lock
, flags
);
1055 if (db
->nextOut
>= db
->rawbuf
+ db
->dmasize
)
1056 db
->nextOut
-= db
->dmasize
;
1057 spin_unlock_irqrestore(&s
->lock
, flags
);
1060 usercnt
= cnt
/ db
->cnt_factor
;
1063 } /* while (count > 0) */
1068 remove_wait_queue(&db
->wait
, &wait
);
1069 set_current_state(TASK_RUNNING
);
1074 au1550_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
* ppos
)
1076 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
1077 struct dmabuf
*db
= &s
->dma_dac
;
1078 DECLARE_WAITQUEUE(wait
, current
);
1080 unsigned long flags
;
1081 int cnt
, usercnt
, avail
;
1083 #ifdef AU1000_VERBOSE_DEBUG
1084 dbg("write: count=%d", count
);
1089 if (!access_ok(VERIFY_READ
, buffer
, count
))
1092 count
*= db
->cnt_factor
;
1095 add_wait_queue(&db
->wait
, &wait
);
1098 /* wait for space in playback buffer
1101 spin_lock_irqsave(&s
->lock
, flags
);
1102 avail
= (int) db
->dmasize
- db
->count
;
1104 __set_current_state(TASK_INTERRUPTIBLE
);
1105 spin_unlock_irqrestore(&s
->lock
, flags
);
1107 if (file
->f_flags
& O_NONBLOCK
) {
1114 if (signal_pending(current
)) {
1121 } while (avail
<= 0);
1123 /* copy from user to nextIn
1125 if ((cnt
= copy_dmabuf_user(db
, (char *) buffer
,
1127 avail
: count
, 0)) < 0) {
1133 spin_lock_irqsave(&s
->lock
, flags
);
1136 if (db
->nextIn
>= db
->rawbuf
+ db
->dmasize
)
1137 db
->nextIn
-= db
->dmasize
;
1139 /* If the data is available, we want to keep two buffers
1140 * on the dma queue. If the queue count reaches zero,
1141 * we know the dma has stopped.
1143 while ((db
->dma_qcount
< 2) && (db
->count
>= db
->fragsize
)) {
1144 if (au1xxx_dbdma_put_source(db
->dmanr
, db
->nextOut
,
1145 db
->fragsize
) == 0) {
1146 pr_error("qcount < 2 and no ring room!");
1148 db
->nextOut
+= db
->fragsize
;
1149 if (db
->nextOut
>= db
->rawbuf
+ db
->dmasize
)
1150 db
->nextOut
-= db
->dmasize
;
1151 db
->count
-= db
->fragsize
;
1152 db
->total_bytes
+= db
->dma_fragsize
;
1153 if (db
->dma_qcount
== 0)
1157 spin_unlock_irqrestore(&s
->lock
, flags
);
1160 usercnt
= cnt
/ db
->cnt_factor
;
1163 } /* while (count > 0) */
1168 remove_wait_queue(&db
->wait
, &wait
);
1169 set_current_state(TASK_RUNNING
);
1174 /* No kernel lock - we have our own spinlock */
1176 au1550_poll(struct file
*file
, struct poll_table_struct
*wait
)
1178 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
1179 unsigned long flags
;
1180 unsigned int mask
= 0;
1182 if (file
->f_mode
& FMODE_WRITE
) {
1183 if (!s
->dma_dac
.ready
)
1185 poll_wait(file
, &s
->dma_dac
.wait
, wait
);
1187 if (file
->f_mode
& FMODE_READ
) {
1188 if (!s
->dma_adc
.ready
)
1190 poll_wait(file
, &s
->dma_adc
.wait
, wait
);
1193 spin_lock_irqsave(&s
->lock
, flags
);
1195 if (file
->f_mode
& FMODE_READ
) {
1196 if (s
->dma_adc
.count
>= (signed)s
->dma_adc
.dma_fragsize
)
1197 mask
|= POLLIN
| POLLRDNORM
;
1199 if (file
->f_mode
& FMODE_WRITE
) {
1200 if (s
->dma_dac
.mapped
) {
1201 if (s
->dma_dac
.count
>=
1202 (signed)s
->dma_dac
.dma_fragsize
)
1203 mask
|= POLLOUT
| POLLWRNORM
;
1205 if ((signed) s
->dma_dac
.dmasize
>=
1206 s
->dma_dac
.count
+ (signed)s
->dma_dac
.dma_fragsize
)
1207 mask
|= POLLOUT
| POLLWRNORM
;
1210 spin_unlock_irqrestore(&s
->lock
, flags
);
1215 au1550_mmap(struct file
*file
, struct vm_area_struct
*vma
)
1217 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
1224 if (vma
->vm_flags
& VM_WRITE
)
1226 else if (vma
->vm_flags
& VM_READ
)
1232 if (vma
->vm_pgoff
!= 0) {
1236 size
= vma
->vm_end
- vma
->vm_start
;
1237 if (size
> (PAGE_SIZE
<< db
->buforder
)) {
1241 if (remap_pfn_range(vma
, vma
->vm_start
,
1242 page_to_pfn(virt_to_page(db
->rawbuf
)),
1243 size
, vma
->vm_page_prot
)) {
1247 vma
->vm_flags
&= ~VM_IO
;
1256 #ifdef AU1000_VERBOSE_DEBUG
1257 static struct ioctl_str_t
{
1261 {SNDCTL_DSP_RESET
, "SNDCTL_DSP_RESET"},
1262 {SNDCTL_DSP_SYNC
, "SNDCTL_DSP_SYNC"},
1263 {SNDCTL_DSP_SPEED
, "SNDCTL_DSP_SPEED"},
1264 {SNDCTL_DSP_STEREO
, "SNDCTL_DSP_STEREO"},
1265 {SNDCTL_DSP_GETBLKSIZE
, "SNDCTL_DSP_GETBLKSIZE"},
1266 {SNDCTL_DSP_SAMPLESIZE
, "SNDCTL_DSP_SAMPLESIZE"},
1267 {SNDCTL_DSP_CHANNELS
, "SNDCTL_DSP_CHANNELS"},
1268 {SOUND_PCM_WRITE_CHANNELS
, "SOUND_PCM_WRITE_CHANNELS"},
1269 {SOUND_PCM_WRITE_FILTER
, "SOUND_PCM_WRITE_FILTER"},
1270 {SNDCTL_DSP_POST
, "SNDCTL_DSP_POST"},
1271 {SNDCTL_DSP_SUBDIVIDE
, "SNDCTL_DSP_SUBDIVIDE"},
1272 {SNDCTL_DSP_SETFRAGMENT
, "SNDCTL_DSP_SETFRAGMENT"},
1273 {SNDCTL_DSP_GETFMTS
, "SNDCTL_DSP_GETFMTS"},
1274 {SNDCTL_DSP_SETFMT
, "SNDCTL_DSP_SETFMT"},
1275 {SNDCTL_DSP_GETOSPACE
, "SNDCTL_DSP_GETOSPACE"},
1276 {SNDCTL_DSP_GETISPACE
, "SNDCTL_DSP_GETISPACE"},
1277 {SNDCTL_DSP_NONBLOCK
, "SNDCTL_DSP_NONBLOCK"},
1278 {SNDCTL_DSP_GETCAPS
, "SNDCTL_DSP_GETCAPS"},
1279 {SNDCTL_DSP_GETTRIGGER
, "SNDCTL_DSP_GETTRIGGER"},
1280 {SNDCTL_DSP_SETTRIGGER
, "SNDCTL_DSP_SETTRIGGER"},
1281 {SNDCTL_DSP_GETIPTR
, "SNDCTL_DSP_GETIPTR"},
1282 {SNDCTL_DSP_GETOPTR
, "SNDCTL_DSP_GETOPTR"},
1283 {SNDCTL_DSP_MAPINBUF
, "SNDCTL_DSP_MAPINBUF"},
1284 {SNDCTL_DSP_MAPOUTBUF
, "SNDCTL_DSP_MAPOUTBUF"},
1285 {SNDCTL_DSP_SETSYNCRO
, "SNDCTL_DSP_SETSYNCRO"},
1286 {SNDCTL_DSP_SETDUPLEX
, "SNDCTL_DSP_SETDUPLEX"},
1287 {SNDCTL_DSP_GETODELAY
, "SNDCTL_DSP_GETODELAY"},
1288 {SNDCTL_DSP_GETCHANNELMASK
, "SNDCTL_DSP_GETCHANNELMASK"},
1289 {SNDCTL_DSP_BIND_CHANNEL
, "SNDCTL_DSP_BIND_CHANNEL"},
1290 {OSS_GETVERSION
, "OSS_GETVERSION"},
1291 {SOUND_PCM_READ_RATE
, "SOUND_PCM_READ_RATE"},
1292 {SOUND_PCM_READ_CHANNELS
, "SOUND_PCM_READ_CHANNELS"},
1293 {SOUND_PCM_READ_BITS
, "SOUND_PCM_READ_BITS"},
1294 {SOUND_PCM_READ_FILTER
, "SOUND_PCM_READ_FILTER"}
1299 dma_count_done(struct dmabuf
*db
)
1304 return db
->dma_fragsize
- au1xxx_get_dma_residue(db
->dmanr
);
1309 au1550_ioctl(struct inode
*inode
, struct file
*file
, unsigned int cmd
,
1312 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
1313 unsigned long flags
;
1314 audio_buf_info abinfo
;
1317 int val
, mapped
, ret
, diff
;
1319 mapped
= ((file
->f_mode
& FMODE_WRITE
) && s
->dma_dac
.mapped
) ||
1320 ((file
->f_mode
& FMODE_READ
) && s
->dma_adc
.mapped
);
1322 #ifdef AU1000_VERBOSE_DEBUG
1323 for (count
=0; count
<sizeof(ioctl_str
)/sizeof(ioctl_str
[0]); count
++) {
1324 if (ioctl_str
[count
].cmd
== cmd
)
1327 if (count
< sizeof(ioctl_str
) / sizeof(ioctl_str
[0]))
1328 dbg("ioctl %s, arg=0x%lx", ioctl_str
[count
].str
, arg
);
1330 dbg("ioctl 0x%x unknown, arg=0x%lx", cmd
, arg
);
1334 case OSS_GETVERSION
:
1335 return put_user(SOUND_VERSION
, (int *) arg
);
1337 case SNDCTL_DSP_SYNC
:
1338 if (file
->f_mode
& FMODE_WRITE
)
1339 return drain_dac(s
, file
->f_flags
& O_NONBLOCK
);
1342 case SNDCTL_DSP_SETDUPLEX
:
1345 case SNDCTL_DSP_GETCAPS
:
1346 return put_user(DSP_CAP_DUPLEX
| DSP_CAP_REALTIME
|
1347 DSP_CAP_TRIGGER
| DSP_CAP_MMAP
, (int *)arg
);
1349 case SNDCTL_DSP_RESET
:
1350 if (file
->f_mode
& FMODE_WRITE
) {
1353 s
->dma_dac
.count
= s
->dma_dac
.total_bytes
= 0;
1354 s
->dma_dac
.nextIn
= s
->dma_dac
.nextOut
=
1357 if (file
->f_mode
& FMODE_READ
) {
1360 s
->dma_adc
.count
= s
->dma_adc
.total_bytes
= 0;
1361 s
->dma_adc
.nextIn
= s
->dma_adc
.nextOut
=
1366 case SNDCTL_DSP_SPEED
:
1367 if (get_user(val
, (int *) arg
))
1370 if (file
->f_mode
& FMODE_READ
) {
1372 set_adc_rate(s
, val
);
1374 if (file
->f_mode
& FMODE_WRITE
) {
1376 set_dac_rate(s
, val
);
1378 if (s
->open_mode
& FMODE_READ
)
1379 if ((ret
= prog_dmabuf_adc(s
)))
1381 if (s
->open_mode
& FMODE_WRITE
)
1382 if ((ret
= prog_dmabuf_dac(s
)))
1385 return put_user((file
->f_mode
& FMODE_READ
) ?
1386 s
->dma_adc
.sample_rate
:
1387 s
->dma_dac
.sample_rate
,
1390 case SNDCTL_DSP_STEREO
:
1391 if (get_user(val
, (int *) arg
))
1393 if (file
->f_mode
& FMODE_READ
) {
1395 s
->dma_adc
.num_channels
= val
? 2 : 1;
1396 if ((ret
= prog_dmabuf_adc(s
)))
1399 if (file
->f_mode
& FMODE_WRITE
) {
1401 s
->dma_dac
.num_channels
= val
? 2 : 1;
1402 if ((ret
= prog_dmabuf_dac(s
)))
1407 case SNDCTL_DSP_CHANNELS
:
1408 if (get_user(val
, (int *) arg
))
1411 if (file
->f_mode
& FMODE_READ
) {
1412 if (val
< 0 || val
> 2)
1415 s
->dma_adc
.num_channels
= val
;
1416 if ((ret
= prog_dmabuf_adc(s
)))
1419 if (file
->f_mode
& FMODE_WRITE
) {
1429 s
->dma_dac
.num_channels
= val
;
1430 if ((ret
= prog_dmabuf_dac(s
)))
1434 return put_user(val
, (int *) arg
);
1436 case SNDCTL_DSP_GETFMTS
: /* Returns a mask */
1437 return put_user(AFMT_S16_LE
| AFMT_U8
, (int *) arg
);
1439 case SNDCTL_DSP_SETFMT
: /* Selects ONE fmt */
1440 if (get_user(val
, (int *) arg
))
1442 if (val
!= AFMT_QUERY
) {
1443 if (file
->f_mode
& FMODE_READ
) {
1445 if (val
== AFMT_S16_LE
)
1446 s
->dma_adc
.sample_size
= 16;
1449 s
->dma_adc
.sample_size
= 8;
1451 if ((ret
= prog_dmabuf_adc(s
)))
1454 if (file
->f_mode
& FMODE_WRITE
) {
1456 if (val
== AFMT_S16_LE
)
1457 s
->dma_dac
.sample_size
= 16;
1460 s
->dma_dac
.sample_size
= 8;
1462 if ((ret
= prog_dmabuf_dac(s
)))
1466 if (file
->f_mode
& FMODE_READ
)
1467 val
= (s
->dma_adc
.sample_size
== 16) ?
1468 AFMT_S16_LE
: AFMT_U8
;
1470 val
= (s
->dma_dac
.sample_size
== 16) ?
1471 AFMT_S16_LE
: AFMT_U8
;
1473 return put_user(val
, (int *) arg
);
1475 case SNDCTL_DSP_POST
:
1478 case SNDCTL_DSP_GETTRIGGER
:
1480 spin_lock_irqsave(&s
->lock
, flags
);
1481 if (file
->f_mode
& FMODE_READ
&& !s
->dma_adc
.stopped
)
1482 val
|= PCM_ENABLE_INPUT
;
1483 if (file
->f_mode
& FMODE_WRITE
&& !s
->dma_dac
.stopped
)
1484 val
|= PCM_ENABLE_OUTPUT
;
1485 spin_unlock_irqrestore(&s
->lock
, flags
);
1486 return put_user(val
, (int *) arg
);
1488 case SNDCTL_DSP_SETTRIGGER
:
1489 if (get_user(val
, (int *) arg
))
1491 if (file
->f_mode
& FMODE_READ
) {
1492 if (val
& PCM_ENABLE_INPUT
)
1497 if (file
->f_mode
& FMODE_WRITE
) {
1498 if (val
& PCM_ENABLE_OUTPUT
)
1505 case SNDCTL_DSP_GETOSPACE
:
1506 if (!(file
->f_mode
& FMODE_WRITE
))
1508 abinfo
.fragsize
= s
->dma_dac
.fragsize
;
1509 spin_lock_irqsave(&s
->lock
, flags
);
1510 count
= s
->dma_dac
.count
;
1511 count
-= dma_count_done(&s
->dma_dac
);
1512 spin_unlock_irqrestore(&s
->lock
, flags
);
1515 abinfo
.bytes
= (s
->dma_dac
.dmasize
- count
) /
1516 s
->dma_dac
.cnt_factor
;
1517 abinfo
.fragstotal
= s
->dma_dac
.numfrag
;
1518 abinfo
.fragments
= abinfo
.bytes
>> s
->dma_dac
.fragshift
;
1519 #ifdef AU1000_VERBOSE_DEBUG
1520 dbg("bytes=%d, fragments=%d", abinfo
.bytes
, abinfo
.fragments
);
1522 return copy_to_user((void *) arg
, &abinfo
,
1523 sizeof(abinfo
)) ? -EFAULT
: 0;
1525 case SNDCTL_DSP_GETISPACE
:
1526 if (!(file
->f_mode
& FMODE_READ
))
1528 abinfo
.fragsize
= s
->dma_adc
.fragsize
;
1529 spin_lock_irqsave(&s
->lock
, flags
);
1530 count
= s
->dma_adc
.count
;
1531 count
+= dma_count_done(&s
->dma_adc
);
1532 spin_unlock_irqrestore(&s
->lock
, flags
);
1535 abinfo
.bytes
= count
/ s
->dma_adc
.cnt_factor
;
1536 abinfo
.fragstotal
= s
->dma_adc
.numfrag
;
1537 abinfo
.fragments
= abinfo
.bytes
>> s
->dma_adc
.fragshift
;
1538 return copy_to_user((void *) arg
, &abinfo
,
1539 sizeof(abinfo
)) ? -EFAULT
: 0;
1541 case SNDCTL_DSP_NONBLOCK
:
1542 file
->f_flags
|= O_NONBLOCK
;
1545 case SNDCTL_DSP_GETODELAY
:
1546 if (!(file
->f_mode
& FMODE_WRITE
))
1548 spin_lock_irqsave(&s
->lock
, flags
);
1549 count
= s
->dma_dac
.count
;
1550 count
-= dma_count_done(&s
->dma_dac
);
1551 spin_unlock_irqrestore(&s
->lock
, flags
);
1554 count
/= s
->dma_dac
.cnt_factor
;
1555 return put_user(count
, (int *) arg
);
1557 case SNDCTL_DSP_GETIPTR
:
1558 if (!(file
->f_mode
& FMODE_READ
))
1560 spin_lock_irqsave(&s
->lock
, flags
);
1561 cinfo
.bytes
= s
->dma_adc
.total_bytes
;
1562 count
= s
->dma_adc
.count
;
1563 if (!s
->dma_adc
.stopped
) {
1564 diff
= dma_count_done(&s
->dma_adc
);
1566 cinfo
.bytes
+= diff
;
1567 cinfo
.ptr
= virt_to_phys(s
->dma_adc
.nextIn
) + diff
-
1568 virt_to_phys(s
->dma_adc
.rawbuf
);
1570 cinfo
.ptr
= virt_to_phys(s
->dma_adc
.nextIn
) -
1571 virt_to_phys(s
->dma_adc
.rawbuf
);
1572 if (s
->dma_adc
.mapped
)
1573 s
->dma_adc
.count
&= (s
->dma_adc
.dma_fragsize
-1);
1574 spin_unlock_irqrestore(&s
->lock
, flags
);
1577 cinfo
.blocks
= count
>> s
->dma_adc
.fragshift
;
1578 return copy_to_user((void *) arg
, &cinfo
, sizeof(cinfo
));
1580 case SNDCTL_DSP_GETOPTR
:
1581 if (!(file
->f_mode
& FMODE_READ
))
1583 spin_lock_irqsave(&s
->lock
, flags
);
1584 cinfo
.bytes
= s
->dma_dac
.total_bytes
;
1585 count
= s
->dma_dac
.count
;
1586 if (!s
->dma_dac
.stopped
) {
1587 diff
= dma_count_done(&s
->dma_dac
);
1589 cinfo
.bytes
+= diff
;
1590 cinfo
.ptr
= virt_to_phys(s
->dma_dac
.nextOut
) + diff
-
1591 virt_to_phys(s
->dma_dac
.rawbuf
);
1593 cinfo
.ptr
= virt_to_phys(s
->dma_dac
.nextOut
) -
1594 virt_to_phys(s
->dma_dac
.rawbuf
);
1595 if (s
->dma_dac
.mapped
)
1596 s
->dma_dac
.count
&= (s
->dma_dac
.dma_fragsize
-1);
1597 spin_unlock_irqrestore(&s
->lock
, flags
);
1600 cinfo
.blocks
= count
>> s
->dma_dac
.fragshift
;
1601 return copy_to_user((void *) arg
, &cinfo
, sizeof(cinfo
));
1603 case SNDCTL_DSP_GETBLKSIZE
:
1604 if (file
->f_mode
& FMODE_WRITE
)
1605 return put_user(s
->dma_dac
.fragsize
, (int *) arg
);
1607 return put_user(s
->dma_adc
.fragsize
, (int *) arg
);
1609 case SNDCTL_DSP_SETFRAGMENT
:
1610 if (get_user(val
, (int *) arg
))
1612 if (file
->f_mode
& FMODE_READ
) {
1614 s
->dma_adc
.ossfragshift
= val
& 0xffff;
1615 s
->dma_adc
.ossmaxfrags
= (val
>> 16) & 0xffff;
1616 if (s
->dma_adc
.ossfragshift
< 4)
1617 s
->dma_adc
.ossfragshift
= 4;
1618 if (s
->dma_adc
.ossfragshift
> 15)
1619 s
->dma_adc
.ossfragshift
= 15;
1620 if (s
->dma_adc
.ossmaxfrags
< 4)
1621 s
->dma_adc
.ossmaxfrags
= 4;
1622 if ((ret
= prog_dmabuf_adc(s
)))
1625 if (file
->f_mode
& FMODE_WRITE
) {
1627 s
->dma_dac
.ossfragshift
= val
& 0xffff;
1628 s
->dma_dac
.ossmaxfrags
= (val
>> 16) & 0xffff;
1629 if (s
->dma_dac
.ossfragshift
< 4)
1630 s
->dma_dac
.ossfragshift
= 4;
1631 if (s
->dma_dac
.ossfragshift
> 15)
1632 s
->dma_dac
.ossfragshift
= 15;
1633 if (s
->dma_dac
.ossmaxfrags
< 4)
1634 s
->dma_dac
.ossmaxfrags
= 4;
1635 if ((ret
= prog_dmabuf_dac(s
)))
1640 case SNDCTL_DSP_SUBDIVIDE
:
1641 if ((file
->f_mode
& FMODE_READ
&& s
->dma_adc
.subdivision
) ||
1642 (file
->f_mode
& FMODE_WRITE
&& s
->dma_dac
.subdivision
))
1644 if (get_user(val
, (int *) arg
))
1646 if (val
!= 1 && val
!= 2 && val
!= 4)
1648 if (file
->f_mode
& FMODE_READ
) {
1650 s
->dma_adc
.subdivision
= val
;
1651 if ((ret
= prog_dmabuf_adc(s
)))
1654 if (file
->f_mode
& FMODE_WRITE
) {
1656 s
->dma_dac
.subdivision
= val
;
1657 if ((ret
= prog_dmabuf_dac(s
)))
1662 case SOUND_PCM_READ_RATE
:
1663 return put_user((file
->f_mode
& FMODE_READ
) ?
1664 s
->dma_adc
.sample_rate
:
1665 s
->dma_dac
.sample_rate
,
1668 case SOUND_PCM_READ_CHANNELS
:
1669 if (file
->f_mode
& FMODE_READ
)
1670 return put_user(s
->dma_adc
.num_channels
, (int *)arg
);
1672 return put_user(s
->dma_dac
.num_channels
, (int *)arg
);
1674 case SOUND_PCM_READ_BITS
:
1675 if (file
->f_mode
& FMODE_READ
)
1676 return put_user(s
->dma_adc
.sample_size
, (int *)arg
);
1678 return put_user(s
->dma_dac
.sample_size
, (int *)arg
);
1680 case SOUND_PCM_WRITE_FILTER
:
1681 case SNDCTL_DSP_SETSYNCRO
:
1682 case SOUND_PCM_READ_FILTER
:
1691 au1550_open(struct inode
*inode
, struct file
*file
)
1693 int minor
= MINOR(inode
->i_rdev
);
1694 DECLARE_WAITQUEUE(wait
, current
);
1695 struct au1550_state
*s
= &au1550_state
;
1698 #ifdef AU1000_VERBOSE_DEBUG
1699 if (file
->f_flags
& O_NONBLOCK
)
1700 dbg(__FUNCTION__
": non-blocking");
1702 dbg(__FUNCTION__
": blocking");
1705 file
->private_data
= s
;
1706 /* wait for device to become free */
1708 while (s
->open_mode
& file
->f_mode
) {
1709 if (file
->f_flags
& O_NONBLOCK
) {
1713 add_wait_queue(&s
->open_wait
, &wait
);
1714 __set_current_state(TASK_INTERRUPTIBLE
);
1717 remove_wait_queue(&s
->open_wait
, &wait
);
1718 set_current_state(TASK_RUNNING
);
1719 if (signal_pending(current
))
1720 return -ERESTARTSYS
;
1727 if (file
->f_mode
& FMODE_READ
) {
1728 s
->dma_adc
.ossfragshift
= s
->dma_adc
.ossmaxfrags
=
1729 s
->dma_adc
.subdivision
= s
->dma_adc
.total_bytes
= 0;
1730 s
->dma_adc
.num_channels
= 1;
1731 s
->dma_adc
.sample_size
= 8;
1732 set_adc_rate(s
, 8000);
1733 if ((minor
& 0xf) == SND_DEV_DSP16
)
1734 s
->dma_adc
.sample_size
= 16;
1737 if (file
->f_mode
& FMODE_WRITE
) {
1738 s
->dma_dac
.ossfragshift
= s
->dma_dac
.ossmaxfrags
=
1739 s
->dma_dac
.subdivision
= s
->dma_dac
.total_bytes
= 0;
1740 s
->dma_dac
.num_channels
= 1;
1741 s
->dma_dac
.sample_size
= 8;
1742 set_dac_rate(s
, 8000);
1743 if ((minor
& 0xf) == SND_DEV_DSP16
)
1744 s
->dma_dac
.sample_size
= 16;
1747 if (file
->f_mode
& FMODE_READ
) {
1748 if ((ret
= prog_dmabuf_adc(s
)))
1751 if (file
->f_mode
& FMODE_WRITE
) {
1752 if ((ret
= prog_dmabuf_dac(s
)))
1756 s
->open_mode
|= file
->f_mode
& (FMODE_READ
| FMODE_WRITE
);
1758 init_MUTEX(&s
->sem
);
1763 au1550_release(struct inode
*inode
, struct file
*file
)
1765 struct au1550_state
*s
= (struct au1550_state
*)file
->private_data
;
1769 if (file
->f_mode
& FMODE_WRITE
) {
1771 drain_dac(s
, file
->f_flags
& O_NONBLOCK
);
1776 if (file
->f_mode
& FMODE_WRITE
) {
1778 kfree(s
->dma_dac
.rawbuf
);
1779 s
->dma_dac
.rawbuf
= NULL
;
1781 if (file
->f_mode
& FMODE_READ
) {
1783 kfree(s
->dma_adc
.rawbuf
);
1784 s
->dma_adc
.rawbuf
= NULL
;
1786 s
->open_mode
&= ((~file
->f_mode
) & (FMODE_READ
|FMODE_WRITE
));
1788 wake_up(&s
->open_wait
);
1793 static struct file_operations au1550_audio_fops
= {
1795 llseek
: au1550_llseek
,
1797 write
: au1550_write
,
1799 ioctl
: au1550_ioctl
,
1802 release
: au1550_release
,
1805 /* Set up an internal clock for the PSC3. This will then get
1806 * driven out of the Au1550 as the master.
1813 /* Wire up Freq4 as a clock for the PSC3.
1814 * We know SMBus uses Freq3.
1815 * By making changes to this rate, plus the word strobe
1816 * size, we can make fine adjustments to the actual data rate.
1818 rate
= get_au1x00_speed();
1820 rate
/= (11 * 1000000);
1822 rate
/= (12 * 1000000);
1825 /* The FRDIV in the frequency control is (FRDIV + 1) * 2
1829 clk
= au_readl(SYS_FREQCTRL1
);
1831 clk
&= ~(SYS_FC_FRDIV4_MASK
| SYS_FC_FS4
);;
1832 clk
|= (rate
<< SYS_FC_FRDIV4_BIT
);
1834 au_writel(clk
, SYS_FREQCTRL1
);
1837 /* Set up the clock source routing to get Freq4 to PSC3_intclk.
1839 clk
= au_readl(SYS_CLKSRC
);
1843 au_writel(clk
, SYS_CLKSRC
);
1847 static int __devinit
1850 struct au1550_state
*s
= &au1550_state
;
1852 volatile psc_i2s_t
*ip
;
1857 memset(s
, 0, sizeof(struct au1550_state
));
1859 init_waitqueue_head(&s
->dma_adc
.wait
);
1860 init_waitqueue_head(&s
->dma_dac
.wait
);
1861 init_waitqueue_head(&s
->open_wait
);
1862 init_MUTEX(&s
->open_sem
);
1863 spin_lock_init(&s
->lock
);
1865 s
->codec
= &au1550_i2s_codec
;
1866 s
->psc_addr
= (volatile psc_i2s_t
*)I2S_PSC_BASE
;
1869 if (!request_region(CPHYSADDR(ip
),
1870 0x30, AU1550_MODULE_NAME
)) {
1871 pr_error("I2S Audio ports in use");
1874 /* Allocate the DMA Channels
1876 if ((s
->dma_dac
.dmanr
= au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN
,
1877 DBDMA_I2S_TX_CHAN
, dac_dma_interrupt
, (void *)s
)) == 0) {
1878 pr_error("Can't get DAC DMA");
1881 au1xxx_dbdma_set_devwidth(s
->dma_dac
.dmanr
, 16);
1882 if (au1xxx_dbdma_ring_alloc(s
->dma_dac
.dmanr
,
1883 NUM_DBDMA_DESCRIPTORS
) == 0) {
1884 pr_error("Can't get DAC DMA descriptors");
1888 if ((s
->dma_adc
.dmanr
= au1xxx_dbdma_chan_alloc(DBDMA_I2S_RX_CHAN
,
1889 DBDMA_MEM_CHAN
, adc_dma_interrupt
, (void *)s
)) == 0) {
1890 pr_error("Can't get ADC DMA");
1893 au1xxx_dbdma_set_devwidth(s
->dma_adc
.dmanr
, 16);
1894 if (au1xxx_dbdma_ring_alloc(s
->dma_adc
.dmanr
,
1895 NUM_DBDMA_DESCRIPTORS
) == 0) {
1896 pr_error("Can't get ADC DMA descriptors");
1900 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_I2S_TX_CHAN
, DBDMA_I2S_RX_CHAN
);
1902 /* register devices */
1904 if ((s
->dev_audio
= register_sound_dsp(&au1550_audio_fops
, -1)) < 0)
1907 if ((s
->dev_mixer
= register_sound_mixer(&au1550_mixer_fops
, -1)) < 0)
1911 /* intialize the debug proc device */
1912 s
->ps
= create_proc_read_entry(AU1000_MODULE_NAME
, 0, NULL
,
1913 proc_au1550_dump
, NULL
);
1914 #endif /* AU1550_DEBUG */
1918 /* The GPIO for the appropriate PSC was configured by the
1919 * board specific start up.
1921 * configure PSC for I2S Audio
1923 ip
->psc_ctrl
= PSC_CTRL_DISABLE
; /* Disable PSC */
1925 ip
->psc_sel
= (PSC_SEL_CLK_INTCLK
| PSC_SEL_PS_I2SMODE
);
1930 ip
->psc_ctrl
= PSC_CTRL_ENABLE
;
1933 /* Wait for PSC ready.
1936 val
= ip
->psc_i2sstat
;
1938 } while ((val
& PSC_I2SSTAT_SR
) == 0);
1940 /* Configure I2S controller.
1941 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
1942 * Actual I2S mode (first bit delayed by one clock).
1943 * Master mode (We provide the clock from the PSC).
1945 val
= PSC_I2SCFG_SET_LEN(16);
1947 /* This really should be 250, but it appears that all of the
1948 * PLLs, dividers and so on in the chain shift it. That's the
1949 * problem with sourceing the clock instead of letting the very
1950 * stable codec provide it. But, the PSC doesn't appear to want
1951 * to work in slave mode, so this is what we get. It's not
1952 * studio quality timing, but it's good enough for listening
1955 val
|= PSC_I2SCFG_SET_WS(252);
1957 val
|= PSC_I2SCFG_SET_WS(250);
1959 val
|= PSC_I2SCFG_RT_FIFO8
| PSC_I2SCFG_TT_FIFO8
| \
1960 PSC_I2SCFG_BI
| PSC_I2SCFG_XM
;
1962 ip
->psc_i2scfg
= val
;
1964 val
|= PSC_I2SCFG_DE_ENABLE
;
1965 ip
->psc_i2scfg
= val
;
1968 /* Wait for Device ready.
1971 val
= ip
->psc_i2sstat
;
1973 } while ((val
& PSC_I2SSTAT_DR
) == 0);
1975 val
= ip
->psc_i2scfg
;
1978 s
->codec
->init_codec(s
->codec
);
1983 unregister_sound_dsp(s
->dev_audio
);
1985 au1xxx_dbdma_chan_free(s
->dma_adc
.dmanr
);
1987 au1xxx_dbdma_chan_free(s
->dma_dac
.dmanr
);
1989 release_region(CPHYSADDR(I2S_PSC_BASE
), 0x30);
1994 static void __devinit
1997 struct au1550_state
*s
= &au1550_state
;
2003 remove_proc_entry(AU1000_MODULE_NAME
, NULL
);
2004 #endif /* AU1000_DEBUG */
2006 au1xxx_dbdma_chan_free(s
->dma_adc
.dmanr
);
2007 au1xxx_dbdma_chan_free(s
->dma_dac
.dmanr
);
2008 release_region(CPHYSADDR(I2S_PSC_BASE
), 0x30);
2009 unregister_sound_dsp(s
->dev_audio
);
2010 unregister_sound_mixer(s
->dev_mixer
);
2016 return au1550_probe();
2020 cleanup_au1550(void)
2025 module_init(init_au1550
);
2026 module_exit(cleanup_au1550
);
2028 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
2029 MODULE_DESCRIPTION("Au1550 I2S Audio Driver");