release/src-rt-6.x/linux/linux-2.6/include/asm-sh/cpu-sh2/cache.h

   1 /*
   2  * include/asm-sh/cpu-sh2/cache.h
   3  *
   4  * Copyright (C) 2003 Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #ifndef __ASM_CPU_SH2_CACHE_H
  11 #define __ASM_CPU_SH2_CACHE_H
  12
  13 #define L1_CACHE_SHIFT  4
  14
  15 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
  16 #define CCR             0xfffffe92      /* Address of Cache Control Register */
  17
  18 #define CCR_CACHE_CE    0x01    /* Cache enable */
  19 #define CCR_CACHE_ID    0x02    /* Instruction Replacement disable */
  20 #define CCR_CACHE_OD    0x04    /* Data Replacement disable */
  21 #define CCR_CACHE_TW    0x08    /* Two-way mode */
  22 #define CCR_CACHE_CP    0x10    /* Cache purge */
  23
  24 #define CACHE_OC_ADDRESS_ARRAY  0x60000000
  25
  26 #define CCR_CACHE_ENABLE        CCR_CACHE_CE
  27 #define CCR_CACHE_INVALIDATE    CCR_CACHE_CP
  28 #define CCR_CACHE_ORA           CCR_CACHE_TW
  29 #define CCR_CACHE_WT            0x00    /* SH-2 is _always_ write-through */
  30
  31 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  32 #define CCR1            0xffffffec
  33 #define CCR             CCR1
  34
  35 #define CCR_CACHE_CE    0x01    /* Cache enable */
  36 #define CCR_CACHE_WT    0x06    /* CCR[bit1=1,bit2=1] */
  37                                 /* 0x00000000-0x7fffffff: Write-through  */
  38                                 /* 0x80000000-0x9fffffff: Write-back     */
  39                                 /* 0xc0000000-0xdfffffff: Write-through  */
  40 #define CCR_CACHE_CB    0x00    /* CCR[bit1=0,bit2=0] */
  41                                 /* 0x00000000-0x7fffffff: Write-back     */
  42                                 /* 0x80000000-0x9fffffff: Write-through  */
  43                                 /* 0xc0000000-0xdfffffff: Write-back     */
  44 #define CCR_CACHE_CF    0x08    /* Cache invalidate */
  45
  46 #define CACHE_OC_ADDRESS_ARRAY  0xf0000000
  47 #define CACHE_OC_DATA_ARRAY     0xf1000000
  48
  49 #define CCR_CACHE_ENABLE        CCR_CACHE_CE
  50 #define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
  51 #endif
  52 #endif /* __ASM_CPU_SH2_CACHE_H */
  53