RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / asm-ppc / system.h
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1 /*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4 #ifndef __PPC_SYSTEM_H
5 #define __PPC_SYSTEM_H
7 #include <linux/kernel.h>
9 #include <asm/hw_irq.h>
12 * Memory barrier.
13 * The sync instruction guarantees that all memory accesses initiated
14 * by this processor have been performed (with respect to all other
15 * mechanisms that access memory). The eieio instruction is a barrier
16 * providing an ordering (separately) for (a) cacheable stores and (b)
17 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 * mb() prevents loads and stores being reordered across this point.
20 * rmb() prevents loads being reordered across this point.
21 * wmb() prevents stores being reordered across this point.
22 * read_barrier_depends() prevents data-dependent loads being reordered
23 * across this point (nop on PPC).
25 * We can use the eieio instruction for wmb, but since it doesn't
26 * give any ordering guarantees about loads, we have to use the
27 * stronger but slower sync instruction for mb and rmb.
29 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
30 #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
31 #define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
32 #define read_barrier_depends() do { } while(0)
34 #define set_mb(var, value) do { var = value; mb(); } while (0)
36 #ifdef CONFIG_SMP
37 #define smp_mb() mb()
38 #define smp_rmb() rmb()
39 #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
40 #define smp_read_barrier_depends() read_barrier_depends()
41 #else
42 #define smp_mb() barrier()
43 #define smp_rmb() barrier()
44 #define smp_wmb() barrier()
45 #define smp_read_barrier_depends() do { } while(0)
46 #endif /* CONFIG_SMP */
48 #ifdef __KERNEL__
49 struct task_struct;
50 struct pt_regs;
52 extern void print_backtrace(unsigned long *);
53 extern void show_regs(struct pt_regs * regs);
54 extern void flush_instruction_cache(void);
55 extern void hard_reset_now(void);
56 extern void poweroff_now(void);
57 #ifdef CONFIG_6xx
58 extern long _get_L2CR(void);
59 extern long _get_L3CR(void);
60 extern void _set_L2CR(unsigned long);
61 extern void _set_L3CR(unsigned long);
62 #else
63 #define _get_L2CR() 0L
64 #define _get_L3CR() 0L
65 #define _set_L2CR(val) do { } while(0)
66 #define _set_L3CR(val) do { } while(0)
67 #endif
68 extern void via_cuda_init(void);
69 extern void pmac_nvram_init(void);
70 extern void chrp_nvram_init(void);
71 extern void read_rtc_time(void);
72 extern void pmac_find_display(void);
73 extern void giveup_fpu(struct task_struct *);
74 extern void disable_kernel_fp(void);
75 extern void enable_kernel_fp(void);
76 extern void flush_fp_to_thread(struct task_struct *);
77 extern void enable_kernel_altivec(void);
78 extern void giveup_altivec(struct task_struct *);
79 extern void load_up_altivec(struct task_struct *);
80 extern int emulate_altivec(struct pt_regs *);
81 extern void giveup_spe(struct task_struct *);
82 extern void load_up_spe(struct task_struct *);
83 extern int fix_alignment(struct pt_regs *);
84 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
85 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
87 #ifndef CONFIG_SMP
88 extern void discard_lazy_cpu_state(void);
89 #else
90 static inline void discard_lazy_cpu_state(void)
93 #endif
95 #ifdef CONFIG_ALTIVEC
96 extern void flush_altivec_to_thread(struct task_struct *);
97 #else
98 static inline void flush_altivec_to_thread(struct task_struct *t)
101 #endif
103 #ifdef CONFIG_SPE
104 extern void flush_spe_to_thread(struct task_struct *);
105 #else
106 static inline void flush_spe_to_thread(struct task_struct *t)
109 #endif
111 extern int call_rtas(const char *, int, int, unsigned long *, ...);
112 extern void cacheable_memzero(void *p, unsigned int nb);
113 extern void *cacheable_memcpy(void *, const void *, unsigned int);
114 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
115 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
116 extern int die(const char *, struct pt_regs *, long);
117 extern void _exception(int, struct pt_regs *, int, unsigned long);
118 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
120 #ifdef CONFIG_BOOKE_WDT
121 extern u32 booke_wdt_enabled;
122 extern u32 booke_wdt_period;
123 #endif /* CONFIG_BOOKE_WDT */
125 struct device_node;
126 extern void note_scsi_host(struct device_node *, void *);
128 extern struct task_struct *__switch_to(struct task_struct *,
129 struct task_struct *);
130 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
133 * On SMP systems, when the scheduler does migration-cost autodetection,
134 * it needs a way to flush as much of the CPU's caches as possible.
136 * TODO: fill this in!
138 static inline void sched_cacheflush(void)
142 struct thread_struct;
143 extern struct task_struct *_switch(struct thread_struct *prev,
144 struct thread_struct *next);
146 extern unsigned int rtas_data;
148 static __inline__ unsigned long
149 xchg_u32(volatile void *p, unsigned long val)
151 unsigned long prev;
153 __asm__ __volatile__ ("\n\
154 1: lwarx %0,0,%2 \n"
155 PPC405_ERR77(0,%2)
156 " stwcx. %3,0,%2 \n\
157 bne- 1b"
158 : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
159 : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
160 : "cc", "memory");
162 return prev;
166 * This function doesn't exist, so you'll get a linker error
167 * if something tries to do an invalid xchg().
169 extern void __xchg_called_with_bad_pointer(void);
171 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
173 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
175 switch (size) {
176 case 4:
177 return (unsigned long) xchg_u32(ptr, x);
178 #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */
179 case 8:
180 return (unsigned long) xchg_u64(ptr, x);
181 #endif /* 0 */
183 __xchg_called_with_bad_pointer();
184 return x;
189 extern inline void * xchg_ptr(void * m, void * val)
191 return (void *) xchg_u32(m, (unsigned long) val);
195 #define __HAVE_ARCH_CMPXCHG 1
197 static __inline__ unsigned long
198 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
200 unsigned int prev;
202 __asm__ __volatile__ ("\n\
203 1: lwarx %0,0,%2 \n\
204 cmpw 0,%0,%3 \n\
205 bne 2f \n"
206 PPC405_ERR77(0,%2)
207 " stwcx. %4,0,%2 \n\
208 bne- 1b\n"
209 #ifdef CONFIG_SMP
210 " sync\n"
211 #endif /* CONFIG_SMP */
212 "2:"
213 : "=&r" (prev), "=m" (*p)
214 : "r" (p), "r" (old), "r" (new), "m" (*p)
215 : "cc", "memory");
217 return prev;
220 /* This function doesn't exist, so you'll get a linker error
221 if something tries to do an invalid cmpxchg(). */
222 extern void __cmpxchg_called_with_bad_pointer(void);
224 static __inline__ unsigned long
225 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
227 switch (size) {
228 case 4:
229 return __cmpxchg_u32(ptr, old, new);
230 #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */
231 case 8:
232 return __cmpxchg_u64(ptr, old, new);
233 #endif /* 0 */
235 __cmpxchg_called_with_bad_pointer();
236 return old;
239 #define cmpxchg(ptr,o,n) \
240 ({ \
241 __typeof__(*(ptr)) _o_ = (o); \
242 __typeof__(*(ptr)) _n_ = (n); \
243 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
244 (unsigned long)_n_, sizeof(*(ptr))); \
247 #define arch_align_stack(x) (x)
249 #endif /* __KERNEL__ */
250 #endif /* __PPC_SYSTEM_H */