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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / asm-mips / system.h
blob6dc0815516ffdb761126b29f792bb8795b249141
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 */
12 #ifndef _ASM_SYSTEM_H
13 #define _ASM_SYSTEM_H
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/barrier.h>
21 #include <asm/cpu-features.h>
22 #include <asm/dsp.h>
23 #include <asm/war.h>
24
25
26 /*
27 * switch_to(n) should switch tasks to task nr n, first
28 * checking that n isn't the current task, in which case it does nothing.
29 */
30 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
31
32 struct task_struct;
33
34 #ifdef CONFIG_MIPS_MT_FPAFF
35
36 /*
37 * Handle the scheduler resume end of FPU affinity management. We do this
38 * inline to try to keep the overhead down. If we have been forced to run on
39 * a "CPU" with an FPU because of a previous high level of FP computation,
40 * but did not actually use the FPU during the most recent time-slice (CU1
41 * isn't set), we undo the restriction on cpus_allowed.
42 *
43 * We're not calling set_cpus_allowed() here, because we have no need to
44 * force prompt migration - we're already switching the current CPU to a
45 * different thread.
46 */
47
48 #define switch_to(prev,next,last) \
49 do { \
50 if (cpu_has_fpu && \
51 (prev->thread.mflags & MF_FPUBOUND) && \
52 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
53 prev->thread.mflags &= ~MF_FPUBOUND; \
54 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
55 } \
56 if (cpu_has_dsp) \
57 __save_dsp(prev); \
58 next->thread.emulated_fp = 0; \
59 (last) = resume(prev, next, task_thread_info(next)); \
60 } while(0)
61
62 #else
63 #define switch_to(prev,next,last) \
64 do { \
65 if (cpu_has_dsp) \
66 __save_dsp(prev); \
67 (last) = resume(prev, next, task_thread_info(next)); \
68 } while (0)
69 #endif
70
71 #define finish_arch_switch(prev) \
72 do { \
73 if (cpu_has_dsp) \
74 __restore_dsp(current); \
75 if (cpu_has_userlocal) \
76 write_c0_userlocal(current_thread_info()->tp_value); \
77 } while (0)
78
79 /*
80 * On SMP systems, when the scheduler does migration-cost autodetection,
81 * it needs a way to flush as much of the CPU's caches as possible.
82 *
83 * TODO: fill this in!
84 */
85 static inline void sched_cacheflush(void)
86 {
87 }
88
89 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
90 {
91 __u32 retval;
92
93 if (cpu_has_llsc && R10000_LLSC_WAR) {
94 unsigned long dummy;
95
96 __asm__ __volatile__(
97 " .set mips3 \n"
98 "1: ll %0, %3 # xchg_u32 \n"
99 " .set mips0 \n"
100 " move %2, %z4 \n"
101 " .set mips3 \n"
102 " sc %2, %1 \n"
103 " beqzl %2, 1b \n"
104 " .set mips0 \n"
105 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
106 : "R" (*m), "Jr" (val)
107 : "memory");
108 } else if (cpu_has_llsc) {
109 unsigned long dummy;
110
111 __asm__ __volatile__(
112 " .set mips3 \n"
113 "1: ll %0, %3 # xchg_u32 \n"
114 " .set mips0 \n"
115 " move %2, %z4 \n"
116 " .set mips3 \n"
117 " sc %2, %1 \n"
118 " beqz %2, 2f \n"
119 " .subsection 2 \n"
120 "2: b 1b \n"
121 " .previous \n"
122 " .set mips0 \n"
123 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
124 : "R" (*m), "Jr" (val)
125 : "memory");
126 } else {
127 unsigned long flags;
128
129 raw_local_irq_save(flags);
130 retval = *m;
131 *m = val;
132 raw_local_irq_restore(flags); /* implies memory barrier */
133 }
134
135 smp_mb();
136
137 return retval;
138 }
139
140 #ifdef CONFIG_64BIT
141 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
142 {
143 __u64 retval;
144
145 if (cpu_has_llsc && R10000_LLSC_WAR) {
146 unsigned long dummy;
147
148 __asm__ __volatile__(
149 " .set mips3 \n"
150 "1: lld %0, %3 # xchg_u64 \n"
151 " move %2, %z4 \n"
152 " scd %2, %1 \n"
153 " beqzl %2, 1b \n"
154 " .set mips0 \n"
155 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
156 : "R" (*m), "Jr" (val)
157 : "memory");
158 } else if (cpu_has_llsc) {
159 unsigned long dummy;
160
161 __asm__ __volatile__(
162 " .set mips3 \n"
163 "1: lld %0, %3 # xchg_u64 \n"
164 " move %2, %z4 \n"
165 " scd %2, %1 \n"
166 " beqz %2, 2f \n"
167 " .subsection 2 \n"
168 "2: b 1b \n"
169 " .previous \n"
170 " .set mips0 \n"
171 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
172 : "R" (*m), "Jr" (val)
173 : "memory");
174 } else {
175 unsigned long flags;
176
177 raw_local_irq_save(flags);
178 retval = *m;
179 *m = val;
180 raw_local_irq_restore(flags); /* implies memory barrier */
181 }
182
183 smp_mb();
184
185 return retval;
186 }
187 #else
188 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
189 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
190 #endif
191
192 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
193 {
194 switch (size) {
195 case 4:
196 return __xchg_u32(ptr, x);
197 case 8:
198 return __xchg_u64(ptr, x);
199 }
200
201 return x;
202 }
203
204 #define xchg(ptr, x) \
205 ({ \
206 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
207 \
208 ((__typeof__(*(ptr))) \
209 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
210 })
211
212 #define __HAVE_ARCH_CMPXCHG 1
213
214 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
215 unsigned long new)
216 {
217 __u32 retval;
218
219 if (cpu_has_llsc && R10000_LLSC_WAR) {
220 __asm__ __volatile__(
221 " .set push \n"
222 " .set noat \n"
223 " .set mips3 \n"
224 "1: ll %0, %2 # __cmpxchg_u32 \n"
225 " bne %0, %z3, 2f \n"
226 " .set mips0 \n"
227 " move $1, %z4 \n"
228 " .set mips3 \n"
229 " sc $1, %1 \n"
230 " beqzl $1, 1b \n"
231 "2: \n"
232 " .set pop \n"
233 : "=&r" (retval), "=R" (*m)
234 : "R" (*m), "Jr" (old), "Jr" (new)
235 : "memory");
236 } else if (cpu_has_llsc) {
237 __asm__ __volatile__(
238 " .set push \n"
239 " .set noat \n"
240 " .set mips3 \n"
241 "1: ll %0, %2 # __cmpxchg_u32 \n"
242 " bne %0, %z3, 2f \n"
243 " .set mips0 \n"
244 " move $1, %z4 \n"
245 " .set mips3 \n"
246 " sc $1, %1 \n"
247 " beqz $1, 3f \n"
248 "2: \n"
249 " .subsection 2 \n"
250 "3: b 1b \n"
251 " .previous \n"
252 " .set pop \n"
253 : "=&r" (retval), "=R" (*m)
254 : "R" (*m), "Jr" (old), "Jr" (new)
255 : "memory");
256 } else {
257 unsigned long flags;
258
259 raw_local_irq_save(flags);
260 retval = *m;
261 if (retval == old)
262 *m = new;
263 raw_local_irq_restore(flags); /* implies memory barrier */
264 }
265
266 smp_mb();
267
268 return retval;
269 }
270
271 static inline unsigned long __cmpxchg_u32_local(volatile int * m,
272 unsigned long old, unsigned long new)
273 {
274 __u32 retval;
275
276 if (cpu_has_llsc && R10000_LLSC_WAR) {
277 __asm__ __volatile__(
278 " .set push \n"
279 " .set noat \n"
280 " .set mips3 \n"
281 "1: ll %0, %2 # __cmpxchg_u32 \n"
282 " bne %0, %z3, 2f \n"
283 " .set mips0 \n"
284 " move $1, %z4 \n"
285 " .set mips3 \n"
286 " sc $1, %1 \n"
287 " beqzl $1, 1b \n"
288 "2: \n"
289 " .set pop \n"
290 : "=&r" (retval), "=R" (*m)
291 : "R" (*m), "Jr" (old), "Jr" (new)
292 : "memory");
293 } else if (cpu_has_llsc) {
294 __asm__ __volatile__(
295 " .set push \n"
296 " .set noat \n"
297 " .set mips3 \n"
298 "1: ll %0, %2 # __cmpxchg_u32 \n"
299 " bne %0, %z3, 2f \n"
300 " .set mips0 \n"
301 " move $1, %z4 \n"
302 " .set mips3 \n"
303 " sc $1, %1 \n"
304 " beqz $1, 1b \n"
305 "2: \n"
306 " .set pop \n"
307 : "=&r" (retval), "=R" (*m)
308 : "R" (*m), "Jr" (old), "Jr" (new)
309 : "memory");
310 } else {
311 unsigned long flags;
312
313 local_irq_save(flags);
314 retval = *m;
315 if (retval == old)
316 *m = new;
317 local_irq_restore(flags); /* implies memory barrier */
318 }
319
320 return retval;
321 }
322
323 #ifdef CONFIG_64BIT
324 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
325 unsigned long new)
326 {
327 __u64 retval;
328
329 if (cpu_has_llsc && R10000_LLSC_WAR) {
330 __asm__ __volatile__(
331 " .set push \n"
332 " .set noat \n"
333 " .set mips3 \n"
334 "1: lld %0, %2 # __cmpxchg_u64 \n"
335 " bne %0, %z3, 2f \n"
336 " move $1, %z4 \n"
337 " scd $1, %1 \n"
338 " beqzl $1, 1b \n"
339 "2: \n"
340 " .set pop \n"
341 : "=&r" (retval), "=R" (*m)
342 : "R" (*m), "Jr" (old), "Jr" (new)
343 : "memory");
344 } else if (cpu_has_llsc) {
345 __asm__ __volatile__(
346 " .set push \n"
347 " .set noat \n"
348 " .set mips3 \n"
349 "1: lld %0, %2 # __cmpxchg_u64 \n"
350 " bne %0, %z3, 2f \n"
351 " move $1, %z4 \n"
352 " scd $1, %1 \n"
353 " beqz $1, 3f \n"
354 "2: \n"
355 " .subsection 2 \n"
356 "3: b 1b \n"
357 " .previous \n"
358 " .set pop \n"
359 : "=&r" (retval), "=R" (*m)
360 : "R" (*m), "Jr" (old), "Jr" (new)
361 : "memory");
362 } else {
363 unsigned long flags;
364
365 raw_local_irq_save(flags);
366 retval = *m;
367 if (retval == old)
368 *m = new;
369 raw_local_irq_restore(flags); /* implies memory barrier */
370 }
371
372 smp_mb();
373
374 return retval;
375 }
376
377 static inline unsigned long __cmpxchg_u64_local(volatile int * m,
378 unsigned long old, unsigned long new)
379 {
380 __u64 retval;
381
382 if (cpu_has_llsc && R10000_LLSC_WAR) {
383 __asm__ __volatile__(
384 " .set push \n"
385 " .set noat \n"
386 " .set mips3 \n"
387 "1: lld %0, %2 # __cmpxchg_u64 \n"
388 " bne %0, %z3, 2f \n"
389 " move $1, %z4 \n"
390 " scd $1, %1 \n"
391 " beqzl $1, 1b \n"
392 "2: \n"
393 " .set pop \n"
394 : "=&r" (retval), "=R" (*m)
395 : "R" (*m), "Jr" (old), "Jr" (new)
396 : "memory");
397 } else if (cpu_has_llsc) {
398 __asm__ __volatile__(
399 " .set push \n"
400 " .set noat \n"
401 " .set mips3 \n"
402 "1: lld %0, %2 # __cmpxchg_u64 \n"
403 " bne %0, %z3, 2f \n"
404 " move $1, %z4 \n"
405 " scd $1, %1 \n"
406 " beqz $1, 1b \n"
407 "2: \n"
408 " .set pop \n"
409 : "=&r" (retval), "=R" (*m)
410 : "R" (*m), "Jr" (old), "Jr" (new)
411 : "memory");
412 } else {
413 unsigned long flags;
414
415 local_irq_save(flags);
416 retval = *m;
417 if (retval == old)
418 *m = new;
419 local_irq_restore(flags); /* implies memory barrier */
420 }
421
422 return retval;
423 }
424
425 #else
426 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
427 volatile int * m, unsigned long old, unsigned long new);
428 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
429 extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels(
430 volatile int * m, unsigned long old, unsigned long new);
431 #define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels
432 #endif
433
434 /* This function doesn't exist, so you'll get a linker error
435 if something tries to do an invalid cmpxchg(). */
436 extern void __cmpxchg_called_with_bad_pointer(void);
437
438 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
439 unsigned long new, int size)
440 {
441 switch (size) {
442 case 4:
443 return __cmpxchg_u32(ptr, old, new);
444 case 8:
445 return __cmpxchg_u64(ptr, old, new);
446 }
447 __cmpxchg_called_with_bad_pointer();
448 return old;
449 }
450
451 static inline unsigned long __cmpxchg_local(volatile void * ptr,
452 unsigned long old, unsigned long new, int size)
453 {
454 switch (size) {
455 case 4:
456 return __cmpxchg_u32_local(ptr, old, new);
457 case 8:
458 return __cmpxchg_u64_local(ptr, old, new);
459 }
460 __cmpxchg_called_with_bad_pointer();
461 return old;
462 }
463
464 #define cmpxchg(ptr,old,new) \
465 ((__typeof__(*(ptr)))__cmpxchg((ptr), \
466 (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
467
468 #define cmpxchg_local(ptr,old,new) \
469 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
470 (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
471
472 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
473 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
474
475 typedef void (*vi_handler_t)(void);
476 extern void *set_vi_handler (int n, vi_handler_t addr);
477
478 extern void *set_except_vector(int n, void *addr);
479 extern unsigned long ebase;
480 extern void per_cpu_trap_init(void);
481
482 extern int stop_a_enabled;
483
484 /*
485 * See include/asm-ia64/system.h; prevents deadlock on SMP
486 * systems.
487 */
488 #define __ARCH_WANT_UNLOCKED_CTXSW
489
490 #define arch_align_stack(x) (x)
491
492 #endif /* _ASM_SYSTEM_H */
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