release/src-rt-6.x/linux/linux-2.6/include/asm-mips/mach-generic/ide.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994-1996  Linus Torvalds & authors
   7  *
   8  * Copied from i386; many of the especially older MIPS or ISA-based platforms
   9  * are basically identical.  Using this file probably implies i8259 PIC
  10  * support in a system but the very least interrupt numbers 0 - 15 need to
  11  * be put aside for legacy devices.
  12  */
  13 #ifndef __ASM_MACH_GENERIC_IDE_H
  14 #define __ASM_MACH_GENERIC_IDE_H
  15
  16 #ifdef __KERNEL__
  17
  18 #include <linux/pci.h>
  19 #include <linux/stddef.h>
  20 #include <asm/processor.h>
  21
  22 #ifndef MAX_HWIFS
  23 # ifdef CONFIG_BLK_DEV_IDEPCI
  24 #define MAX_HWIFS       10
  25 # else
  26 #define MAX_HWIFS       6
  27 # endif
  28 #endif
  29
  30 #define IDE_ARCH_OBSOLETE_DEFAULTS
  31
  32 extern int mips_system_has_legacy_ide;
  33
  34 static __inline__ int ide_probe_legacy(void)
  35 {
  36 #ifdef CONFIG_PCI
  37         struct pci_dev *dev;
  38         /*
  39          * This can be called on the ide_setup() path, super-early in
  40          * boot.  But the down_read() will enable local interrupts,
  41          * which can cause some machines to crash.  So here we detect
  42          * and flag that situation and bail out early.
  43          */
  44         if (no_pci_devices())
  45                 return 0;
  46         dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
  47         if (dev)
  48                 goto found;
  49         dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  50         if (dev)
  51                 goto found;
  52         return 0;
  53 found:
  54         pci_dev_put(dev);
  55         return 1;
  56 #elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
  57         return 1;
  58 #else
  59         return 0;
  60 #endif
  61 }
  62
  63 static __inline__ int ide_default_irq(unsigned long base)
  64 {
  65         switch (base) {
  66                 case 0x1f0: return 14;
  67                 case 0x170: return 15;
  68                 case 0x1e8: return 11;
  69                 case 0x168: return 10;
  70                 case 0x1e0: return 8;
  71                 case 0x160: return 12;
  72                 default:
  73                         return 0;
  74         }
  75 }
  76
  77 static __inline__ unsigned long ide_default_io_base(int index)
  78 {
  79         if (!ide_probe_legacy())
  80                 return 0;
  81         /*
  82          *      If PCI is present then it is not safe to poke around
  83          *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
  84          *      defined compatibility mode ports for PCI. A user can
  85          *      override this using ide= but we must default safe.
  86          */
  87         if (no_pci_devices()) {
  88                 switch (index) {
  89                 case 2: return 0x1e8;
  90                 case 3: return 0x168;
  91                 case 4: return 0x1e0;
  92                 case 5: return 0x160;
  93                 }
  94         }
  95         switch (index) {
  96         case 0: return 0x1f0;
  97         case 1: return 0x170;
  98         default:
  99                 return 0;
 100         }
 101 }
 102
 103 #define IDE_ARCH_OBSOLETE_INIT
 104 #define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
 105
 106 #ifdef CONFIG_BLK_DEV_IDEPCI
 107 #define ide_init_default_irq(base)      (0)
 108 #else
 109 #define ide_init_default_irq(base)      ide_default_irq(base)
 110 #endif
 111
 112 /* MIPS port and memory-mapped I/O string operations.  */
 113 static inline void __ide_flush_prologue(void)
 114 {
 115 #ifdef CONFIG_SMP
 116         if (cpu_has_dc_aliases)
 117                 preempt_disable();
 118 #endif
 119 }
 120
 121 static inline void __ide_flush_epilogue(void)
 122 {
 123 #ifdef CONFIG_SMP
 124         if (cpu_has_dc_aliases)
 125                 preempt_enable();
 126 #endif
 127 }
 128
 129 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
 130 {
 131         if (cpu_has_dc_aliases) {
 132                 unsigned long end = addr + size;
 133
 134                 while (addr < end) {
 135                         local_flush_data_cache_page((void *)addr);
 136                         addr += PAGE_SIZE;
 137                 }
 138         }
 139 }
 140
 141 /*
 142  * insw() and gang might be called with interrupts disabled, so we can't
 143  * send IPIs for flushing due to the potencial of deadlocks, see the comment
 144  * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
 145  * problem by disabling preemption so we know we actually perform the flush
 146  * on the processor that actually has the lines to be flushed which hopefully
 147  * is even better for performance anyway.
 148  */
 149 static inline void __ide_insw(unsigned long port, void *addr,
 150         unsigned int count)
 151 {
 152         __ide_flush_prologue();
 153         insw(port, addr, count);
 154         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 155         __ide_flush_epilogue();
 156 }
 157
 158 static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
 159 {
 160         __ide_flush_prologue();
 161         insl(port, addr, count);
 162         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 163         __ide_flush_epilogue();
 164 }
 165
 166 static inline void __ide_outsw(unsigned long port, const void *addr,
 167         unsigned long count)
 168 {
 169         __ide_flush_prologue();
 170         outsw(port, addr, count);
 171         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 172         __ide_flush_epilogue();
 173 }
 174
 175 static inline void __ide_outsl(unsigned long port, const void *addr,
 176         unsigned long count)
 177 {
 178         __ide_flush_prologue();
 179         outsl(port, addr, count);
 180         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 181         __ide_flush_epilogue();
 182 }
 183
 184 static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
 185 {
 186         __ide_flush_prologue();
 187         readsw(port, addr, count);
 188         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 189         __ide_flush_epilogue();
 190 }
 191
 192 static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
 193 {
 194         __ide_flush_prologue();
 195         readsl(port, addr, count);
 196         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 197         __ide_flush_epilogue();
 198 }
 199
 200 static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
 201 {
 202         __ide_flush_prologue();
 203         writesw(port, addr, count);
 204         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 205         __ide_flush_epilogue();
 206 }
 207
 208 static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
 209 {
 210         __ide_flush_prologue();
 211         writesl(port, addr, count);
 212         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 213         __ide_flush_epilogue();
 214 }
 215
 216 /* ide_insw calls insw, not __ide_insw.  Why? */
 217 #undef insw
 218 #undef insl
 219 #undef outsw
 220 #undef outsl
 221 #define insw(port, addr, count) __ide_insw(port, addr, count)
 222 #define insl(port, addr, count) __ide_insl(port, addr, count)
 223 #define outsw(port, addr, count) __ide_outsw(port, addr, count)
 224 #define outsl(port, addr, count) __ide_outsl(port, addr, count)
 225
 226 #endif /* __KERNEL__ */
 227
 228 #endif /* __ASM_MACH_GENERIC_IDE_H */