release/src-rt-6.x/linux/linux-2.6/include/asm-m68knommu/mcfsim.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfsim.h -- ColdFire System Integration Module support.
   5  *
   6  *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcfsim_h
  12 #define mcfsim_h
  13 /****************************************************************************/
  14
  15
  16 /*
  17  *      Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282,
  18  *      5307 or 5407 specific addresses.
  19  */
  20 #if defined(CONFIG_M5204)
  21 #include <asm/m5204sim.h>
  22 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
  23 #include <asm/m5206sim.h>
  24 #elif defined(CONFIG_M520x)
  25 #include <asm/m520xsim.h>
  26 #elif defined(CONFIG_M523x)
  27 #include <asm/m523xsim.h>
  28 #elif defined(CONFIG_M5249)
  29 #include <asm/m5249sim.h>
  30 #elif defined(CONFIG_M527x)
  31 #include <asm/m527xsim.h>
  32 #elif defined(CONFIG_M5272)
  33 #include <asm/m5272sim.h>
  34 #elif defined(CONFIG_M528x)
  35 #include <asm/m528xsim.h>
  36 #elif defined(CONFIG_M5307)
  37 #include <asm/m5307sim.h>
  38 #elif defined(CONFIG_M532x)
  39 #include <asm/m532xsim.h>
  40 #elif defined(CONFIG_M5407)
  41 #include <asm/m5407sim.h>
  42 #endif
  43
  44
  45 /*
  46  *      Define the base address of the SIM within the MBAR address space.
  47  */
  48 #define MCFSIM_BASE             0x0             /* Base address of SIM */
  49
  50
  51 /*
  52  *      Bit definitions for the ICR family of registers.
  53  */
  54 #define MCFSIM_ICR_AUTOVEC      0x80            /* Auto-vectored intr */
  55 #define MCFSIM_ICR_LEVEL0       0x00            /* Level 0 intr */
  56 #define MCFSIM_ICR_LEVEL1       0x04            /* Level 1 intr */
  57 #define MCFSIM_ICR_LEVEL2       0x08            /* Level 2 intr */
  58 #define MCFSIM_ICR_LEVEL3       0x0c            /* Level 3 intr */
  59 #define MCFSIM_ICR_LEVEL4       0x10            /* Level 4 intr */
  60 #define MCFSIM_ICR_LEVEL5       0x14            /* Level 5 intr */
  61 #define MCFSIM_ICR_LEVEL6       0x18            /* Level 6 intr */
  62 #define MCFSIM_ICR_LEVEL7       0x1c            /* Level 7 intr */
  63
  64 #define MCFSIM_ICR_PRI0         0x00            /* Priority 0 intr */
  65 #define MCFSIM_ICR_PRI1         0x01            /* Priority 1 intr */
  66 #define MCFSIM_ICR_PRI2         0x02            /* Priority 2 intr */
  67 #define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
  68
  69 /*
  70  *      Bit definitions for the Interrupt Mask register (IMR).
  71  */
  72 #define MCFSIM_IMR_EINT1        0x0002          /* External intr # 1 */
  73 #define MCFSIM_IMR_EINT2        0x0004          /* External intr # 2 */
  74 #define MCFSIM_IMR_EINT3        0x0008          /* External intr # 3 */
  75 #define MCFSIM_IMR_EINT4        0x0010          /* External intr # 4 */
  76 #define MCFSIM_IMR_EINT5        0x0020          /* External intr # 5 */
  77 #define MCFSIM_IMR_EINT6        0x0040          /* External intr # 6 */
  78 #define MCFSIM_IMR_EINT7        0x0080          /* External intr # 7 */
  79
  80 #define MCFSIM_IMR_SWD          0x0100          /* Software Watchdog intr */
  81 #define MCFSIM_IMR_TIMER1       0x0200          /* TIMER 1 intr */
  82 #define MCFSIM_IMR_TIMER2       0x0400          /* TIMER 2 intr */
  83 #define MCFSIM_IMR_MBUS         0x0800          /* MBUS intr    */
  84 #define MCFSIM_IMR_UART1        0x1000          /* UART 1 intr */
  85 #define MCFSIM_IMR_UART2        0x2000          /* UART 2 intr */
  86
  87 #if defined(CONFIG_M5206e)
  88 #define MCFSIM_IMR_DMA1         0x4000          /* DMA 1 intr */
  89 #define MCFSIM_IMR_DMA2         0x8000          /* DMA 2 intr */
  90 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
  91 #define MCFSIM_IMR_DMA0         0x4000          /* DMA 0 intr */
  92 #define MCFSIM_IMR_DMA1         0x8000          /* DMA 1 intr */
  93 #define MCFSIM_IMR_DMA2         0x10000         /* DMA 2 intr */
  94 #define MCFSIM_IMR_DMA3         0x20000         /* DMA 3 intr */
  95 #endif
  96
  97 /*
  98  *      Mask for all of the SIM devices. Some parts have more or less
  99  *      SIM devices. This is a catchall for the sandard set.
 100  */
 101 #ifndef MCFSIM_IMR_MASKALL
 102 #define MCFSIM_IMR_MASKALL      0x3ffe          /* All intr sources */
 103 #endif
 104
 105
 106 /*
 107  *      PIT interrupt settings, if not found in mXXXXsim.h file.
 108  */
 109 #ifndef ICR_INTRCONF
 110 #define ICR_INTRCONF            0x2b            /* PIT1 level 5, priority 3 */
 111 #endif
 112 #ifndef MCFPIT_IMR
 113 #define MCFPIT_IMR              MCFINTC_IMRH
 114 #endif
 115 #ifndef MCFPIT_IMR_IBIT
 116 #define MCFPIT_IMR_IBIT         (1 << (MCFINT_PIT1 - 32))
 117 #endif
 118
 119
 120 #ifndef __ASSEMBLY__
 121 /*
 122  *      Definition for the interrupt auto-vectoring support.
 123  */
 124 extern void     mcf_autovector(unsigned int vec);
 125 #endif /* __ASSEMBLY__ */
 126
 127 /****************************************************************************/
 128 #endif  /* mcfsim_h */