release/src-rt-6.x/linux/linux-2.6/include/asm-m68k/system.h

   1 #ifndef _M68K_SYSTEM_H
   2 #define _M68K_SYSTEM_H
   3
   4 #include <linux/linkage.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7 #include <asm/entry.h>
   8
   9 #ifdef __KERNEL__
  10
  11 /*
  12  * switch_to(n) should switch tasks to task ptr, first checking that
  13  * ptr isn't the current task, in which case it does nothing.  This
  14  * also clears the TS-flag if the task we switched to has used the
  15  * math co-processor latest.
  16  */
  17 /*
  18  * switch_to() saves the extra registers, that are not saved
  19  * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
  20  * a0-a1. Some of these are used by schedule() and its predecessors
  21  * and so we might get see unexpected behaviors when a task returns
  22  * with unexpected register values.
  23  *
  24  * syscall stores these registers itself and none of them are used
  25  * by syscall after the function in the syscall has been called.
  26  *
  27  * Beware that resume now expects *next to be in d1 and the offset of
  28  * tss to be in a1. This saves a few instructions as we no longer have
  29  * to push them onto the stack and read them back right after.
  30  *
  31  * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
  32  *
  33  * Changed 96/09/19 by Andreas Schwab
  34  * pass prev in a0, next in a1
  35  */
  36 asmlinkage void resume(void);
  37 #define switch_to(prev,next,last) do { \
  38   register void *_prev __asm__ ("a0") = (prev); \
  39   register void *_next __asm__ ("a1") = (next); \
  40   register void *_last __asm__ ("d1"); \
  41   __asm__ __volatile__("jbsr resume" \
  42                        : "=a" (_prev), "=a" (_next), "=d" (_last) \
  43                        : "0" (_prev), "1" (_next) \
  44                        : "d0", "d2", "d3", "d4", "d5"); \
  45   (last) = _last; \
  46 } while (0)
  47
  48
  49 /* interrupt control.. */
  50 #if 0
  51 #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
  52 #else
  53 #include <linux/hardirq.h>
  54 #define local_irq_enable() ({                                                   \
  55         if (MACH_IS_Q40 || !hardirq_count())                                    \
  56                 asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory");    \
  57 })
  58 #endif
  59 #define local_irq_disable() asm volatile ("oriw  #0x0700,%%sr": : : "memory")
  60 #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
  61 #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
  62
  63 static inline int irqs_disabled(void)
  64 {
  65         unsigned long flags;
  66         local_save_flags(flags);
  67         return flags & ~ALLOWINT;
  68 }
  69
  70 /* For spinlocks etc */
  71 #define local_irq_save(x)       ({ local_save_flags(x); local_irq_disable(); })
  72
  73 /*
  74  * Force strict CPU ordering.
  75  * Not really required on m68k...
  76  */
  77 #define nop()           do { asm volatile ("nop"); barrier(); } while (0)
  78 #define mb()            barrier()
  79 #define rmb()           barrier()
  80 #define wmb()           barrier()
  81 #define read_barrier_depends()  ((void)0)
  82 #define set_mb(var, value)      ({ (var) = (value); wmb(); })
  83
  84 #define smp_mb()        barrier()
  85 #define smp_rmb()       barrier()
  86 #define smp_wmb()       barrier()
  87 #define smp_read_barrier_depends()      ((void)0)
  88
  89
  90 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  91
  92 struct __xchg_dummy { unsigned long a[100]; };
  93 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
  94
  95 #ifndef CONFIG_RMW_INSNS
  96 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
  97 {
  98         unsigned long flags, tmp;
  99
 100         local_irq_save(flags);
 101
 102         switch (size) {
 103         case 1:
 104                 tmp = *(u8 *)ptr;
 105                 *(u8 *)ptr = x;
 106                 x = tmp;
 107                 break;
 108         case 2:
 109                 tmp = *(u16 *)ptr;
 110                 *(u16 *)ptr = x;
 111                 x = tmp;
 112                 break;
 113         case 4:
 114                 tmp = *(u32 *)ptr;
 115                 *(u32 *)ptr = x;
 116                 x = tmp;
 117                 break;
 118         default:
 119                 BUG();
 120         }
 121
 122         local_irq_restore(flags);
 123         return x;
 124 }
 125 #else
 126 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 127 {
 128         switch (size) {
 129             case 1:
 130                 __asm__ __volatile__
 131                         ("moveb %2,%0\n\t"
 132                          "1:\n\t"
 133                          "casb %0,%1,%2\n\t"
 134                          "jne 1b"
 135                          : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
 136                 break;
 137             case 2:
 138                 __asm__ __volatile__
 139                         ("movew %2,%0\n\t"
 140                          "1:\n\t"
 141                          "casw %0,%1,%2\n\t"
 142                          "jne 1b"
 143                          : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
 144                 break;
 145             case 4:
 146                 __asm__ __volatile__
 147                         ("movel %2,%0\n\t"
 148                          "1:\n\t"
 149                          "casl %0,%1,%2\n\t"
 150                          "jne 1b"
 151                          : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
 152                 break;
 153         }
 154         return x;
 155 }
 156 #endif
 157
 158 /*
 159  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 160  * store NEW in MEM.  Return the initial value in MEM.  Success is
 161  * indicated by comparing RETURN with OLD.
 162  */
 163 #ifdef CONFIG_RMW_INSNS
 164 #define __HAVE_ARCH_CMPXCHG     1
 165
 166 static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
 167                                       unsigned long new, int size)
 168 {
 169         switch (size) {
 170         case 1:
 171                 __asm__ __volatile__ ("casb %0,%2,%1"
 172                                       : "=d" (old), "=m" (*(char *)p)
 173                                       : "d" (new), "0" (old), "m" (*(char *)p));
 174                 break;
 175         case 2:
 176                 __asm__ __volatile__ ("casw %0,%2,%1"
 177                                       : "=d" (old), "=m" (*(short *)p)
 178                                       : "d" (new), "0" (old), "m" (*(short *)p));
 179                 break;
 180         case 4:
 181                 __asm__ __volatile__ ("casl %0,%2,%1"
 182                                       : "=d" (old), "=m" (*(int *)p)
 183                                       : "d" (new), "0" (old), "m" (*(int *)p));
 184                 break;
 185         }
 186         return old;
 187 }
 188
 189 #define cmpxchg(ptr,o,n)\
 190         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 191                                         (unsigned long)(n),sizeof(*(ptr))))
 192 #endif
 193
 194 #define arch_align_stack(x) (x)
 195
 196 #endif /* __KERNEL__ */
 197
 198 #endif /* _M68K_SYSTEM_H */