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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / asm-blackfin / mach-common / def_LPBlackfin.h
blobbe1ece8c0c2775c277023ad74c88067054ee830e
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29 /* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31 #ifndef _DEF_LPBLACKFIN_H
32 #define _DEF_LPBLACKFIN_H
33
34 #include <asm/mach/anomaly.h>
35
36 /*#if !defined(__ADSPLPBLACKFIN__)
37 #warning def_LPBlackfin.h should only be included for 532 compatible chips.
38 #endif
39 */
40
41 #define MK_BMSK_(x) (1<<x)
42
43 #if defined(ANOMALY_05000198)
44
45 #define bfin_read8(addr) ({ unsigned char __v; \
46 __asm__ __volatile__ ("NOP;\n\t" \
47 "%0 = b[%1] (z);\n\t" \
48 : "=d"(__v) : "a"(addr)); \
49 __v; })
50
51 #define bfin_read16(addr) ({ unsigned __v; \
52 __asm__ __volatile__ ("NOP;\n\t"\
53 "%0 = w[%1] (z);\n\t"\
54 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
55
56 #define bfin_read32(addr) ({ unsigned __v; \
57 __asm__ __volatile__ ("NOP;\n\t"\
58 "%0 = [%1];\n\t"\
59 : "=d"(__v) : "a"(addr)); __v; })
60
61 #define bfin_write8(addr, val) ({ \
62 __asm__ __volatile__ ("NOP;\n\t" \
63 "b[%0] = %1;\n\t" \
64 : : "a"(addr), "d"(val) : "memory");})
65
66 #define bfin_write16(addr,val) ({\
67 __asm__ __volatile__ ("NOP;\n\t"\
68 "w[%0] = %1;\n\t"\
69 : : "a"(addr) , "d"(val) : "memory");})
70
71 #define bfin_write32(addr,val) ({\
72 __asm__ __volatile__ ("NOP;\n\t"\
73 "[%0] = %1;\n\t"\
74 : : "a"(addr) , "d"(val) : "memory");})
75
76 #else
77
78 #define bfin_read8(addr) ({ unsigned char __v; \
79 __asm__ __volatile__ ( \
80 "%0 = b[%1] (z);\n\t" \
81 :"=d"(__v) : "a"(addr)); \
82 __v; })
83
84 #define bfin_read16(addr) ({ unsigned __v; \
85 __asm__ __volatile__ (\
86 "%0 = w[%1] (z);\n\t"\
87 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
88
89 #define bfin_read32(addr) ({ unsigned __v; \
90 __asm__ __volatile__ (\
91 "%0 = [%1];\n\t"\
92 : "=d"(__v) : "a"(addr)); __v; })
93
94 #define bfin_write8(addr, val) ({ \
95 __asm__ __volatile__ ( \
96 "b[%0] = %1; \n\t" \
97 ::"a"(addr), "d"(val) : "memory");})
98
99 #define bfin_write16(addr,val) ({\
100 __asm__ __volatile__ (\
101 "w[%0] = %1;\n\t"\
102 : : "a"(addr) , "d"(val) : "memory");})
103
104 #define bfin_write32(addr,val) ({\
105 __asm__ __volatile__ (\
106 "[%0] = %1;\n\t"\
107 : : "a"(addr) , "d"(val) : "memory");})
108
109 #endif
110
111 /**************************************************
112 * System Register Bits
113 **************************************************/
114
115 /**************************************************
116 * ASTAT register
117 **************************************************/
118
119 /* definitions of ASTAT bit positions*/
120
121 /*Result of last ALU0 or shifter operation is zero*/
122 #define ASTAT_AZ_P 0x00000000
123 /*Result of last ALU0 or shifter operation is negative*/
124 #define ASTAT_AN_P 0x00000001
125 /*Condition Code, used for holding comparison results*/
126 #define ASTAT_CC_P 0x00000005
127 /*Quotient Bit*/
128 #define ASTAT_AQ_P 0x00000006
129 /*Rounding mode, set for biased, clear for unbiased*/
130 #define ASTAT_RND_MOD_P 0x00000008
131 /*Result of last ALU0 operation generated a carry*/
132 #define ASTAT_AC0_P 0x0000000C
133 /*Result of last ALU0 operation generated a carry*/
134 #define ASTAT_AC0_COPY_P 0x00000002
135 /*Result of last ALU1 operation generated a carry*/
136 #define ASTAT_AC1_P 0x0000000D
137 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
138 #define ASTAT_AV0_P 0x00000010
139 /*Sticky version of ASTAT_AV0 */
140 #define ASTAT_AV0S_P 0x00000011
141 /*Result of last MAC1 operation overflowed, sticky for MAC*/
142 #define ASTAT_AV1_P 0x00000012
143 /*Sticky version of ASTAT_AV1 */
144 #define ASTAT_AV1S_P 0x00000013
145 /*Result of last ALU0 or MAC0 operation overflowed*/
146 #define ASTAT_V_P 0x00000018
147 /*Result of last ALU0 or MAC0 operation overflowed*/
148 #define ASTAT_V_COPY_P 0x00000003
149 /*Sticky version of ASTAT_V*/
150 #define ASTAT_VS_P 0x00000019
151
152 /* Masks */
153
154 /*Result of last ALU0 or shifter operation is zero*/
155 #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
156 /*Result of last ALU0 or shifter operation is negative*/
157 #define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
158 /*Result of last ALU0 operation generated a carry*/
159 #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
160 /*Result of last ALU0 operation generated a carry*/
161 #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
162 /*Result of last ALU0 operation generated a carry*/
163 #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
164 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
165 #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
166 /*Result of last MAC1 operation overflowed, sticky for MAC*/
167 #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
168 /*Condition Code, used for holding comparison results*/
169 #define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
170 /*Quotient Bit*/
171 #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
172 /*Rounding mode, set for biased, clear for unbiased*/
173 #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
174 /*Overflow Bit*/
175 #define ASTAT_V MK_BMSK_(ASTAT_V_P)
176 /*Overflow Bit*/
177 #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
178
179 /**************************************************
180 * SEQSTAT register
181 **************************************************/
182
183 /* Bit Positions */
184 #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
185 #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
186 #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
187 #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
188 #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
189 #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
190 #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
191 * set by IDLE instruction.
192 */
193 #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
194 * reset was a software reset
195 * (=1)
196 */
197 #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
198 #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
199 #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
200 #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
201 #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
202 /* Masks */
203 /* Exception cause */
204 #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
205 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
206 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
207 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
208 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
209 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
210 0)
211
212 /* Indicates whether the last reset was a software reset (=1) */
213 #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
214
215 /* Last hw error cause */
216 #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
217 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
218 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
219 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
220 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
221 0)
222
223 /* Translate bits to something useful */
224
225 /* Last hw error cause */
226 #define SEQSTAT_HWERRCAUSE_SHIFT (14)
227 #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
228 #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
229 #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
230 #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
231
232 /**************************************************
233 * SYSCFG register
234 **************************************************/
235
236 /* Bit Positions */
237 #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
238 * set it forces an exception
239 * for each instruction executed
240 */
241 #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
242 #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
243
244 /* Masks */
245
246 /* Supervisor single step, when set it forces an exception for each
247 *instruction executed
248 */
249 #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
250 /* Enable cycle counter (=1) */
251 #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
252 /* Self Nesting Interrupt Enable */
253 #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
254 /* Backward-compatibility for typos in prior releases */
255 #define SYSCFG_SSSSTEP SYSCFG_SSSTEP
256 #define SYSCFG_CCCEN SYSCFG_CCEN
257
258 /****************************************************
259 * Core MMR Register Map
260 ****************************************************/
261
262 /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
263
264 #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
265 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */
266 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
267 * Buffer Status
268 */
269 #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
270 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
271 * Buffer Fault Address
272 */
273 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
274 * Buffer 0
275 */
276 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
277 * Buffer 1
278 */
279 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
280 * Buffer 2
281 */
282 #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
283 * Lookaside Buffer 3
284 */
285 #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
286 * Lookaside Buffer 4
287 */
288 #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
289 * Lookaside Buffer 5
290 */
291 #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
292 * Lookaside Buffer 6
293 */
294 #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
295 * Lookaside Buffer 7
296 */
297 #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
298 * Lookaside Buffer 8
299 */
300 #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
301 * Lookaside Buffer 9
302 */
303 #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
304 * Lookaside Buffer 10
305 */
306 #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
307 * Lookaside Buffer 11
308 */
309 #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
310 * Lookaside Buffer 12
311 */
312 #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
313 * Lookaside Buffer 13
314 */
315 #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
316 * Lookaside Buffer 14
317 */
318 #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
319 * Lookaside Buffer 15
320 */
321 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
322 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
323 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
324 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
325 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
326 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
327 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
328 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
329 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
330 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
331 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
332 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
333 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
334 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
335 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
336 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
337 #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
338
339 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
340 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
341 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
342
343 /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
344
345 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
346 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
347 #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
348 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
349 #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
350 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
351 * Protection Lookaside Buffer 0
352 */
353 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
354 * Protection Lookaside Buffer 1
355 */
356 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
357 * Protection Lookaside Buffer 2
358 */
359 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
360 * Protection Lookaside Buffer 3
361 */
362 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
363 * Protection Lookaside Buffer 4
364 */
365 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
366 * Protection Lookaside Buffer 5
367 */
368 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
369 * Protection Lookaside Buffer 6
370 */
371 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
372 * Protection Lookaside Buffer 7
373 */
374 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
375 * Protection Lookaside Buffer 8
376 */
377 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
378 * Protection Lookaside Buffer 9
379 */
380 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
381 * Protection Lookaside Buffer 10
382 */
383 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
384 * Protection Lookaside Buffer 11
385 */
386 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
387 * Protection Lookaside Buffer 12
388 */
389 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
390 * Protection Lookaside Buffer 13
391 */
392 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
393 * Protection Lookaside Buffer 14
394 */
395 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
396 * Protection Lookaside Buffer 15
397 */
398 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
399 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
400 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
401 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
402 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
403 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
404 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
405 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
406 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
407 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
408 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
409 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
410 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
411 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
412 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
413 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
414 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
415 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
416 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
417
418 /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
419
420 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
421 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
422 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
423 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
424 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
425 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
426 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
427 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
428 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
429 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
430 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
431 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
432 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
433 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
434 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
435 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
436 #define IMASK 0xFFE02104 /* Interrupt Mask Register */
437 #define IPEND 0xFFE02108 /* Interrupt Pending Register */
438 #define ILAT 0xFFE0210C /* Interrupt Latch Register */
439 #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
440
441 /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
442
443 #define TCNTL 0xFFE03000 /* Core Timer Control Register */
444 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */
445 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */
446 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */
447
448 /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
449 #define DSPID 0xFFE05000 /* DSP Processor ID Register for
450 * MP implementations
451 */
452
453 #define DBGSTAT 0xFFE05008 /* Debug Status Register */
454
455 /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
456
457 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
458 #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
459 #define TBUF 0xFFE06100 /* Trace Buffer */
460
461 /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
462
463 /* Watchpoint Instruction Address Control Register */
464 #define WPIACTL 0xFFE07000
465 /* Watchpoint Instruction Address Register 0 */
466 #define WPIA0 0xFFE07040
467 /* Watchpoint Instruction Address Register 1 */
468 #define WPIA1 0xFFE07044
469 /* Watchpoint Instruction Address Register 2 */
470 #define WPIA2 0xFFE07048
471 /* Watchpoint Instruction Address Register 3 */
472 #define WPIA3 0xFFE0704C
473 /* Watchpoint Instruction Address Register 4 */
474 #define WPIA4 0xFFE07050
475 /* Watchpoint Instruction Address Register 5 */
476 #define WPIA5 0xFFE07054
477 /* Watchpoint Instruction Address Count Register 0 */
478 #define WPIACNT0 0xFFE07080
479 /* Watchpoint Instruction Address Count Register 1 */
480 #define WPIACNT1 0xFFE07084
481 /* Watchpoint Instruction Address Count Register 2 */
482 #define WPIACNT2 0xFFE07088
483 /* Watchpoint Instruction Address Count Register 3 */
484 #define WPIACNT3 0xFFE0708C
485 /* Watchpoint Instruction Address Count Register 4 */
486 #define WPIACNT4 0xFFE07090
487 /* Watchpoint Instruction Address Count Register 5 */
488 #define WPIACNT5 0xFFE07094
489 /* Watchpoint Data Address Control Register */
490 #define WPDACTL 0xFFE07100
491 /* Watchpoint Data Address Register 0 */
492 #define WPDA0 0xFFE07140
493 /* Watchpoint Data Address Register 1 */
494 #define WPDA1 0xFFE07144
495 /* Watchpoint Data Address Count Value Register 0 */
496 #define WPDACNT0 0xFFE07180
497 /* Watchpoint Data Address Count Value Register 1 */
498 #define WPDACNT1 0xFFE07184
499 /* Watchpoint Status Register */
500 #define WPSTAT 0xFFE07200
501
502 /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
503
504 /* Performance Monitor Control Register */
505 #define PFCTL 0xFFE08000
506 /* Performance Monitor Counter Register 0 */
507 #define PFCNTR0 0xFFE08100
508 /* Performance Monitor Counter Register 1 */
509 #define PFCNTR1 0xFFE08104
510
511 /****************************************************
512 * Core MMR Register Bits
513 ****************************************************/
514
515 /**************************************************
516 * EVT registers (ILAT, IMASK, and IPEND).
517 **************************************************/
518
519 /* Bit Positions */
520 #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
521 #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
522 #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
523 #define EVT_EVX_P 0x00000003 /* Exception bit position */
524 #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
525 #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
526 #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
527 #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
528 #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
529 #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
530 #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
531 #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
532 #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
533 #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
534 #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
535 #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
536
537 /* Masks */
538 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
539 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
540 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
541 #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
542 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
543 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
544 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
545 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
546 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
547 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
548 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
549 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
550 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
551 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
552 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
553 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
554
555 /**************************************************
556 * DMEM_CONTROL Register
557 **************************************************/
558 /* Bit Positions */
559 #define ENDM_P 0x00 /* (doesn't really exist) Enable
560 *Data Memory L1
561 */
562 #define DMCTL_ENDM_P ENDM_P /* "" (older define) */
563
564 #define ENDCPLB_P 0x01 /* Enable DCPLBS */
565 #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
566 #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
567 #define DMCTL_DMC0_P DMC0_P /* "" (older define) */
568 #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
569 #define DMCTL_DMC1_P DMC1_P /* "" (older define) */
570 #define DCBS_P 0x04 /* L1 Data Cache Bank Select */
571 #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
572 #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
573
574 /* Masks */
575 #define ENDM 0x00000001 /* (doesn't really exist) Enable
576 * Data Memory L1
577 */
578 #define ENDCPLB 0x00000002 /* Enable DCPLB */
579 #define ASRAM_BSRAM 0x00000000
580 #define ACACHE_BSRAM 0x00000008
581 #define ACACHE_BCACHE 0x0000000C
582 #define DCBS 0x00000010 /* L1 Data Cache Bank Select */
583 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
584 #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
585
586 /* IMEM_CONTROL Register */
587 /* Bit Positions */
588 #define ENIM_P 0x00 /* Enable L1 Code Memory */
589 #define IMCTL_ENIM_P 0x00 /* "" (older define) */
590 #define ENICPLB_P 0x01 /* Enable ICPLB */
591 #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
592 #define IMC_P 0x02 /* Enable */
593 #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
594 * cache (0=SRAM)
595 */
596 #define ILOC0_P 0x03 /* Lock Way 0 */
597 #define ILOC1_P 0x04 /* Lock Way 1 */
598 #define ILOC2_P 0x05 /* Lock Way 2 */
599 #define ILOC3_P 0x06 /* Lock Way 3 */
600 #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
601 * Priority
602 */
603 /* Masks */
604 #define ENIM 0x00000001 /* Enable L1 Code Memory */
605 #define ENICPLB 0x00000002 /* Enable ICPLB */
606 #define IMC 0x00000004 /* Configure L1 code memory as
607 * cache (0=SRAM)
608 */
609 #define ILOC0 0x00000008 /* Lock Way 0 */
610 #define ILOC1 0x00000010 /* Lock Way 1 */
611 #define ILOC2 0x00000020 /* Lock Way 2 */
612 #define ILOC3 0x00000040 /* Lock Way 3 */
613 #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
614 * Priority
615 */
616
617 /* TCNTL Masks */
618 #define TMPWR 0x00000001 /* Timer Low Power Control,
619 * 0=low power mode, 1=active state
620 */
621 #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
622 #define TAUTORLD 0x00000004 /* Timer auto reload */
623 #define TINT 0x00000008 /* Timer generated interrupt 0=no
624 * interrupt has been generated,
625 * 1=interrupt has been generated
626 * (sticky)
627 */
628
629 /* DCPLB_DATA and ICPLB_DATA Registers */
630 /* Bit Positions */
631 #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
632 #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
633 * locked
634 */
635 #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
636 * allowed (user mode)
637 */
638 /* Masks */
639 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
640 #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
641 * locked
642 */
643 #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
644 * allowed (user mode)
645 */
646 #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
647 #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
648 #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
649 #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
650 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
651 * mapped to L1
652 */
653 #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
654 * priority port
655 */
656 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
657 * in L1
658 */
659 /* ICPLB_DATA only */
660 #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
661 * 1=priority for non-replacement
662 */
663 /* DCPLB_DATA only */
664 #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
665 * access allowed (user mode)
666 */
667 #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
668 * access allowed (supervisor mode)
669 */
670 #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
671 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
672 * write-through writes,
673 * 1= allocate cache lines on
674 * write-through writes.
675 */
676 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
677
678 /* TBUFCTL Masks */
679 #define TBUFPWR 0x0001
680 #define TBUFEN 0x0002
681 #define TBUFOVF 0x0004
682 #define TBUFCMPLP_SINGLE 0x0008
683 #define TBUFCMPLP_DOUBLE 0x0010
684 #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
685
686 /* TBUFSTAT Masks */
687 #define TBUFCNT 0x001F
688
689 /* ITEST_COMMAND and DTEST_COMMAND Registers */
690 /* Masks */
691 #define TEST_READ 0x00000000 /* Read Access */
692 #define TEST_WRITE 0x00000002 /* Write Access */
693 #define TEST_TAG 0x00000000 /* Access TAG */
694 #define TEST_DATA 0x00000004 /* Access DATA */
695 #define TEST_DW0 0x00000000 /* Select Double Word 0 */
696 #define TEST_DW1 0x00000008 /* Select Double Word 1 */
697 #define TEST_DW2 0x00000010 /* Select Double Word 2 */
698 #define TEST_DW3 0x00000018 /* Select Double Word 3 */
699 #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
700 #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
701 #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
702 #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
703 #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
704 #define TEST_WAY0 0x00000000 /* Access Way0 */
705 #define TEST_WAY1 0x04000000 /* Access Way1 */
706 /* ITEST_COMMAND only */
707 #define TEST_WAY2 0x08000000 /* Access Way2 */
708 #define TEST_WAY3 0x0C000000 /* Access Way3 */
709 /* DTEST_COMMAND only */
710 #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
711 #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
712
713 #endif /* _DEF_LPBLACKFIN_H */
Tomato firmware and modifications.