release/src-rt-6.x/linux/linux-2.6/include/asm-avr32/arch-at32ap/smc.h

   1 /*
   2  * Static Memory Controller for AT32 chips
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * Inspired by the OMAP2 General-Purpose Memory Controller interface
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef __ARCH_AT32AP_SMC_H
  13 #define __ARCH_AT32AP_SMC_H
  14
  15 /*
  16  * All timing parameters are in nanoseconds.
  17  */
  18 struct smc_config {
  19         /* Delay from address valid to assertion of given strobe */
  20         u16             ncs_read_setup;
  21         u16             nrd_setup;
  22         u16             ncs_write_setup;
  23         u16             nwe_setup;
  24
  25         /* Pulse length of given strobe */
  26         u16             ncs_read_pulse;
  27         u16             nrd_pulse;
  28         u16             ncs_write_pulse;
  29         u16             nwe_pulse;
  30
  31         /* Total cycle length of given operation */
  32         u16             read_cycle;
  33         u16             write_cycle;
  34
  35         /* Bus width in bytes */
  36         u8              bus_width;
  37
  38         /*
  39          * 0: Data is sampled on rising edge of NCS
  40          * 1: Data is sampled on rising edge of NRD
  41          */
  42         unsigned int    nrd_controlled:1;
  43
  44         /*
  45          * 0: Data is driven on falling edge of NCS
  46          * 1: Data is driven on falling edge of NWR
  47          */
  48         unsigned int    nwe_controlled:1;
  49
  50         /*
  51          * 0: NWAIT is disabled
  52          * 1: Reserved
  53          * 2: NWAIT is frozen mode
  54          * 3: NWAIT in ready mode
  55          */
  56         unsigned int    nwait_mode:2;
  57
  58         /*
  59          * 0: Byte select access type
  60          * 1: Byte write access type
  61          */
  62         unsigned int    byte_write:1;
  63
  64         /*
  65          * Number of clock cycles before data is released after
  66          * the rising edge of the read controlling signal
  67          *
  68          * Total cycles from SMC is tdf_cycles + 1
  69          */
  70         unsigned int    tdf_cycles:4;
  71
  72         /*
  73          * 0: TDF optimization disabled
  74          * 1: TDF optimization enabled
  75          */
  76         unsigned int    tdf_mode:1;
  77 };
  78
  79 extern int smc_set_configuration(int cs, const struct smc_config *config);
  80 extern struct smc_config *smc_get_configuration(int cs);
  81
  82 #endif /* __ARCH_AT32AP_SMC_H */