?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / usb / host / r8a66597.h
blobfe9ceb077d9bbddaf38f7dd6998ca73d1bea7b1a
1 /*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26 #ifndef __R8A66597_H__
27 #define __R8A66597_H__
28
29 #define SYSCFG0 0x00
30 #define SYSCFG1 0x02
31 #define SYSSTS0 0x04
32 #define SYSSTS1 0x06
33 #define DVSTCTR0 0x08
34 #define DVSTCTR1 0x0A
35 #define TESTMODE 0x0C
36 #define PINCFG 0x0E
37 #define DMA0CFG 0x10
38 #define DMA1CFG 0x12
39 #define CFIFO 0x14
40 #define D0FIFO 0x18
41 #define D1FIFO 0x1C
42 #define CFIFOSEL 0x20
43 #define CFIFOCTR 0x22
44 #define CFIFOSIE 0x24
45 #define D0FIFOSEL 0x28
46 #define D0FIFOCTR 0x2A
47 #define D1FIFOSEL 0x2C
48 #define D1FIFOCTR 0x2E
49 #define INTENB0 0x30
50 #define INTENB1 0x32
51 #define INTENB2 0x34
52 #define BRDYENB 0x36
53 #define NRDYENB 0x38
54 #define BEMPENB 0x3A
55 #define SOFCFG 0x3C
56 #define INTSTS0 0x40
57 #define INTSTS1 0x42
58 #define INTSTS2 0x44
59 #define BRDYSTS 0x46
60 #define NRDYSTS 0x48
61 #define BEMPSTS 0x4A
62 #define FRMNUM 0x4C
63 #define UFRMNUM 0x4E
64 #define USBADDR 0x50
65 #define USBREQ 0x54
66 #define USBVAL 0x56
67 #define USBINDX 0x58
68 #define USBLENG 0x5A
69 #define DCPCFG 0x5C
70 #define DCPMAXP 0x5E
71 #define DCPCTR 0x60
72 #define PIPESEL 0x64
73 #define PIPECFG 0x68
74 #define PIPEBUF 0x6A
75 #define PIPEMAXP 0x6C
76 #define PIPEPERI 0x6E
77 #define PIPE1CTR 0x70
78 #define PIPE2CTR 0x72
79 #define PIPE3CTR 0x74
80 #define PIPE4CTR 0x76
81 #define PIPE5CTR 0x78
82 #define PIPE6CTR 0x7A
83 #define PIPE7CTR 0x7C
84 #define PIPE8CTR 0x7E
85 #define PIPE9CTR 0x80
86 #define PIPE1TRE 0x90
87 #define PIPE1TRN 0x92
88 #define PIPE2TRE 0x94
89 #define PIPE2TRN 0x96
90 #define PIPE3TRE 0x98
91 #define PIPE3TRN 0x9A
92 #define PIPE4TRE 0x9C
93 #define PIPE4TRN 0x9E
94 #define PIPE5TRE 0xA0
95 #define PIPE5TRN 0xA2
96 #define DEVADD0 0xD0
97 #define DEVADD1 0xD2
98 #define DEVADD2 0xD4
99 #define DEVADD3 0xD6
100 #define DEVADD4 0xD8
101 #define DEVADD5 0xDA
102 #define DEVADD6 0xDC
103 #define DEVADD7 0xDE
104 #define DEVADD8 0xE0
105 #define DEVADD9 0xE2
106 #define DEVADDA 0xE4
107
108 /* System Configuration Control Register */
109 #define XTAL 0xC000 /* b15-14: Crystal selection */
110 #define XTAL48 0x8000 /* 48MHz */
111 #define XTAL24 0x4000 /* 24MHz */
112 #define XTAL12 0x0000 /* 12MHz */
113 #define XCKE 0x2000 /* b13: External clock enable */
114 #define PLLC 0x0800 /* b11: PLL control */
115 #define SCKE 0x0400 /* b10: USB clock enable */
116 #define PCSDIS 0x0200 /* b9: not CS wakeup */
117 #define LPSME 0x0100 /* b8: Low power sleep mode */
118 #define HSE 0x0080 /* b7: Hi-speed enable */
119 #define DCFM 0x0040 /* b6: Controller function select */
120 #define DRPD 0x0020 /* b5: D+/- pull down control */
121 #define DPRPU 0x0010 /* b4: D+ pull up control */
122 #define USBE 0x0001 /* b0: USB module operation enable */
123
124 /* System Configuration Status Register */
125 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
126 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
127 #define SOFEA 0x0020 /* b5: SOF monitor */
128 #define IDMON 0x0004 /* b3: ID-pin monitor */
129 #define LNST 0x0003 /* b1-0: D+, D- line status */
130 #define SE1 0x0003 /* SE1 */
131 #define FS_KSTS 0x0002 /* Full-Speed K State */
132 #define FS_JSTS 0x0001 /* Full-Speed J State */
133 #define LS_JSTS 0x0002 /* Low-Speed J State */
134 #define LS_KSTS 0x0001 /* Low-Speed K State */
135 #define SE0 0x0000 /* SE0 */
136
137 /* Device State Control Register */
138 #define EXTLP0 0x0400 /* b10: External port */
139 #define VBOUT 0x0200 /* b9: VBUS output */
140 #define WKUP 0x0100 /* b8: Remote wakeup */
141 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
142 #define USBRST 0x0040 /* b6: USB reset enable */
143 #define RESUME 0x0020 /* b5: Resume enable */
144 #define UACT 0x0010 /* b4: USB bus enable */
145 #define RHST 0x0007 /* b1-0: Reset handshake status */
146 #define HSPROC 0x0004 /* HS handshake is processing */
147 #define HSMODE 0x0003 /* Hi-Speed mode */
148 #define FSMODE 0x0002 /* Full-Speed mode */
149 #define LSMODE 0x0001 /* Low-Speed mode */
150 #define UNDECID 0x0000 /* Undecided */
151
152 /* Test Mode Register */
153 #define UTST 0x000F /* b3-0: Test select */
154 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
155 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
156 #define H_TST_K 0x000A /* HOST TEST K */
157 #define H_TST_J 0x0009 /* HOST TEST J */
158 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
159 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
160 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
161 #define P_TST_K 0x0002 /* PERI TEST K */
162 #define P_TST_J 0x0001 /* PERI TEST J */
163 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
164
165 /* Data Pin Configuration Register */
166 #define LDRV 0x8000 /* b15: Drive Current Adjust */
167 #define VIF1 0x0000 /* VIF = 1.8V */
168 #define VIF3 0x8000 /* VIF = 3.3V */
169 #define INTA 0x0001 /* b1: USB INT-pin active */
170
171 /* DMAx Pin Configuration Register */
172 #define DREQA 0x4000 /* b14: Dreq active select */
173 #define BURST 0x2000 /* b13: Burst mode */
174 #define DACKA 0x0400 /* b10: Dack active select */
175 #define DFORM 0x0380 /* b9-7: DMA mode select */
176 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
177 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
178 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
179 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
180 #define DENDA 0x0040 /* b6: Dend active select */
181 #define PKTM 0x0020 /* b5: Packet mode */
182 #define DENDE 0x0010 /* b4: Dend enable */
183 #define OBUS 0x0004 /* b2: OUTbus mode */
184
185 /* CFIFO/DxFIFO Port Select Register */
186 #define RCNT 0x8000 /* b15: Read count mode */
187 #define REW 0x4000 /* b14: Buffer rewind */
188 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189 #define DREQE 0x1000 /* b12: DREQ output enable */
190 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
191 #define MBW_8 0x0000 /* 8bit */
192 #define MBW_16 0x0400 /* 16bit */
193 #define BIGEND 0x0100 /* b8: Big endian mode */
194 #define BYTE_LITTLE 0x0000 /* little dendian */
195 #define BYTE_BIG 0x0100 /* big endifan */
196 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
197 #define CURPIPE 0x000F /* b2-0: PIPE select */
198
199 /* CFIFO/DxFIFO Port Control Register */
200 #define BVAL 0x8000 /* b15: Buffer valid flag */
201 #define BCLR 0x4000 /* b14: Buffer clear */
202 #define FRDY 0x2000 /* b13: FIFO ready */
203 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
204
205 /* Interrupt Enable Register 0 */
206 #define VBSE 0x8000 /* b15: VBUS interrupt */
207 #define RSME 0x4000 /* b14: Resume interrupt */
208 #define SOFE 0x2000 /* b13: Frame update interrupt */
209 #define DVSE 0x1000 /* b12: Device state transition interrupt */
210 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
211 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
212 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
213 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
214
215 /* Interrupt Enable Register 1 */
216 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
217 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
218 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
219 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
220 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
221 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
222 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
223
224 /* BRDY Interrupt Enable/Status Register */
225 #define BRDY9 0x0200 /* b9: PIPE9 */
226 #define BRDY8 0x0100 /* b8: PIPE8 */
227 #define BRDY7 0x0080 /* b7: PIPE7 */
228 #define BRDY6 0x0040 /* b6: PIPE6 */
229 #define BRDY5 0x0020 /* b5: PIPE5 */
230 #define BRDY4 0x0010 /* b4: PIPE4 */
231 #define BRDY3 0x0008 /* b3: PIPE3 */
232 #define BRDY2 0x0004 /* b2: PIPE2 */
233 #define BRDY1 0x0002 /* b1: PIPE1 */
234 #define BRDY0 0x0001 /* b1: PIPE0 */
235
236 /* NRDY Interrupt Enable/Status Register */
237 #define NRDY9 0x0200 /* b9: PIPE9 */
238 #define NRDY8 0x0100 /* b8: PIPE8 */
239 #define NRDY7 0x0080 /* b7: PIPE7 */
240 #define NRDY6 0x0040 /* b6: PIPE6 */
241 #define NRDY5 0x0020 /* b5: PIPE5 */
242 #define NRDY4 0x0010 /* b4: PIPE4 */
243 #define NRDY3 0x0008 /* b3: PIPE3 */
244 #define NRDY2 0x0004 /* b2: PIPE2 */
245 #define NRDY1 0x0002 /* b1: PIPE1 */
246 #define NRDY0 0x0001 /* b1: PIPE0 */
247
248 /* BEMP Interrupt Enable/Status Register */
249 #define BEMP9 0x0200 /* b9: PIPE9 */
250 #define BEMP8 0x0100 /* b8: PIPE8 */
251 #define BEMP7 0x0080 /* b7: PIPE7 */
252 #define BEMP6 0x0040 /* b6: PIPE6 */
253 #define BEMP5 0x0020 /* b5: PIPE5 */
254 #define BEMP4 0x0010 /* b4: PIPE4 */
255 #define BEMP3 0x0008 /* b3: PIPE3 */
256 #define BEMP2 0x0004 /* b2: PIPE2 */
257 #define BEMP1 0x0002 /* b1: PIPE1 */
258 #define BEMP0 0x0001 /* b0: PIPE0 */
259
260 /* SOF Pin Configuration Register */
261 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
262 #define BRDYM 0x0040 /* b6: BRDY clear timing */
263 #define INTL 0x0020 /* b5: Interrupt sense select */
264 #define EDGESTS 0x0010 /* b4: */
265 #define SOFMODE 0x000C /* b3-2: SOF pin select */
266 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
267 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
268 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
269
270 /* Interrupt Status Register 0 */
271 #define VBINT 0x8000 /* b15: VBUS interrupt */
272 #define RESM 0x4000 /* b14: Resume interrupt */
273 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
274 #define DVST 0x1000 /* b12: Device state transition interrupt */
275 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
276 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
277 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
278 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
279 #define VBSTS 0x0080 /* b7: VBUS input port */
280 #define DVSQ 0x0070 /* b6-4: Device state */
281 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
282 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
283 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
284 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
285 #define DS_SUSP 0x0040 /* Suspend */
286 #define DS_CNFG 0x0030 /* Configured */
287 #define DS_ADDS 0x0020 /* Address */
288 #define DS_DFLT 0x0010 /* Default */
289 #define DS_POWR 0x0000 /* Powered */
290 #define DVSQS 0x0030 /* b5-4: Device state */
291 #define VALID 0x0008 /* b3: Setup packet detected flag */
292 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
293 #define CS_SQER 0x0006 /* Sequence error */
294 #define CS_WRND 0x0005 /* Control write nodata status stage */
295 #define CS_WRSS 0x0004 /* Control write status stage */
296 #define CS_WRDS 0x0003 /* Control write data stage */
297 #define CS_RDSS 0x0002 /* Control read status stage */
298 #define CS_RDDS 0x0001 /* Control read data stage */
299 #define CS_IDST 0x0000 /* Idle or setup stage */
300
301 /* Interrupt Status Register 1 */
302 #define OVRCR 0x8000 /* b15: Over-current interrupt */
303 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
304 #define DTCH 0x1000 /* b12: Detach sense interrupt */
305 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
306 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
307 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
308 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
309
310 /* Frame Number Register */
311 #define OVRN 0x8000 /* b15: Overrun error */
312 #define CRCE 0x4000 /* b14: Received data error */
313 #define FRNM 0x07FF /* b10-0: Frame number */
314
315 /* Micro Frame Number Register */
316 #define UFRNM 0x0007 /* b2-0: Micro frame number */
317
318 /* Default Control Pipe Maxpacket Size Register */
319 /* Pipe Maxpacket Size Register */
320 #define DEVSEL 0xF000 /* b15-14: Device address select */
321 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
322
323 /* Default Control Pipe Control Register */
324 #define BSTS 0x8000 /* b15: Buffer status */
325 #define SUREQ 0x4000 /* b14: Send USB request */
326 #define CSCLR 0x2000 /* b13: complete-split status clear */
327 #define CSSTS 0x1000 /* b12: complete-split status */
328 #define SUREQCLR 0x0800 /* b11: stop setup request */
329 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
330 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
331 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
332 #define PBUSY 0x0020 /* b5: pipe busy */
333 #define PINGE 0x0010 /* b4: ping enable */
334 #define CCPL 0x0004 /* b2: Enable control transfer complete */
335 #define PID 0x0003 /* b1-0: Response PID */
336 #define PID_STALL11 0x0003 /* STALL */
337 #define PID_STALL 0x0002 /* STALL */
338 #define PID_BUF 0x0001 /* BUF */
339 #define PID_NAK 0x0000 /* NAK */
340
341 /* Pipe Window Select Register */
342 #define PIPENM 0x0007 /* b2-0: Pipe select */
343
344 /* Pipe Configuration Register */
345 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
346 #define R8A66597_ISO 0xC000 /* Isochronous */
347 #define R8A66597_INT 0x8000 /* Interrupt */
348 #define R8A66597_BULK 0x4000 /* Bulk */
349 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
350 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
351 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
352 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
353 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
354 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
355
356 /* Pipe Buffer Configuration Register */
357 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
358 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
359 #define PIPE0BUF 256
360 #define PIPExBUF 64
361
362 /* Pipe Maxpacket Size Register */
363 #define MXPS 0x07FF /* b10-0: Maxpacket size */
364
365 /* Pipe Cycle Configuration Register */
366 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
367 #define IITV 0x0007 /* b2-0: Isochronous interval */
368
369 /* Pipex Control Register */
370 #define BSTS 0x8000 /* b15: Buffer status */
371 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
372 #define CSCLR 0x2000 /* b13: complete-split status clear */
373 #define CSSTS 0x1000 /* b12: complete-split status */
374 #define ATREPM 0x0400 /* b10: Auto repeat mode */
375 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
376 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
377 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
378 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
379 #define PBUSY 0x0020 /* b5: pipe busy */
380 #define PID 0x0003 /* b1-0: Response PID */
381
382 /* PIPExTRE */
383 #define TRENB 0x0200 /* b9: Transaction counter enable */
384 #define TRCLR 0x0100 /* b8: Transaction counter clear */
385
386 /* PIPExTRN */
387 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
388
389 /* DEVADDx */
390 #define UPPHUB 0x7800
391 #define HUBPORT 0x0700
392 #define USBSPD 0x00C0
393 #define RTPORT 0x0001
394
395 #define R8A66597_MAX_NUM_PIPE 10
396 #define R8A66597_BUF_BSIZE 8
397 #define R8A66597_MAX_DEVICE 10
398 #define R8A66597_MAX_ROOT_HUB 2
399 #define R8A66597_MAX_SAMPLING 10
400 #define R8A66597_MAX_DMA_CHANNEL 2
401 #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
402 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
403 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
404 #define make_devsel(addr) (addr << 12)
405
406 struct r8a66597_pipe_info {
407 u16 pipenum;
408 u16 address; /* R8A66597 HCD usb addres */
409 u16 epnum;
410 u16 maxpacket;
411 u16 type;
412 u16 bufnum;
413 u16 buf_bsize;
414 u16 interval;
415 u16 dir_in;
416 };
417
418 struct r8a66597_pipe {
419 struct r8a66597_pipe_info info;
420
421 unsigned long fifoaddr;
422 unsigned long fifosel;
423 unsigned long fifoctr;
424 unsigned long pipectr;
425 unsigned long pipetre;
426 unsigned long pipetrn;
427 };
428
429 struct r8a66597_td {
430 struct r8a66597_pipe *pipe;
431 struct urb *urb;
432 struct list_head queue;
433
434 u16 type;
435 u16 pipenum;
436 int iso_cnt;
437
438 u16 address; /* R8A66597's USB address */
439 u16 maxpacket;
440
441 unsigned zero_packet:1;
442 unsigned short_packet:1;
443 unsigned set_address:1;
444 };
445
446 struct r8a66597_device {
447 u16 address; /* R8A66597's USB address */
448 u16 hub_port;
449 u16 root_port;
450
451 unsigned short ep_in_toggle;
452 unsigned short ep_out_toggle;
453 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
454 unsigned char dma_map;
455
456 enum usb_device_state state;
457
458 struct usb_device *udev;
459 int usb_address;
460 struct list_head device_list;
461 };
462
463 struct r8a66597_root_hub {
464 u32 port;
465 u16 old_syssts;
466 int scount;
467
468 struct r8a66597_device *dev;
469 };
470
471 struct r8a66597 {
472 spinlock_t lock;
473 unsigned long reg;
474
475 struct r8a66597_device device0;
476 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
477 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
478
479 struct timer_list rh_timer;
480 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
481
482 unsigned short address_map;
483 unsigned short timeout_map;
484 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
485 unsigned char dma_map;
486
487 struct list_head child_device;
488 unsigned long child_connect_map[4];
489 };
490
491 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
492 {
493 return (struct r8a66597 *)(hcd->hcd_priv);
494 }
495
496 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
497 {
498 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
499 }
500
501 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
502 u16 pipenum)
503 {
504 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
505 return NULL;
506
507 return list_entry(r8a66597->pipe_queue[pipenum].next,
508 struct r8a66597_td, queue);
509 }
510
511 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
512 u16 pipenum)
513 {
514 struct r8a66597_td *td;
515
516 td = r8a66597_get_td(r8a66597, pipenum);
517 return (td ? td->urb : NULL);
518 }
519
520 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
521 {
522 return inw(r8a66597->reg + offset);
523 }
524
525 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
526 unsigned long offset, u16 *buf,
527 int len)
528 {
529 len = (len + 1) / 2;
530 insw(r8a66597->reg + offset, buf, len);
531 }
532
533 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
534 unsigned long offset)
535 {
536 outw(val, r8a66597->reg + offset);
537 }
538
539 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
540 unsigned long offset, u16 *buf,
541 int len)
542 {
543 unsigned long fifoaddr = r8a66597->reg + offset;
544 int odd = len & 0x0001;
545
546 len = len / 2;
547 outsw(fifoaddr, buf, len);
548 if (unlikely(odd)) {
549 buf = &buf[len];
550 outb((unsigned char)*buf, fifoaddr);
551 }
552 }
553
554 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
555 u16 val, u16 pat, unsigned long offset)
556 {
557 u16 tmp;
558 tmp = r8a66597_read(r8a66597, offset);
559 tmp = tmp & (~pat);
560 tmp = tmp | val;
561 r8a66597_write(r8a66597, tmp, offset);
562 }
563
564 #define r8a66597_bclr(r8a66597, val, offset) \
565 r8a66597_mdfy(r8a66597, 0, val, offset)
566 #define r8a66597_bset(r8a66597, val, offset) \
567 r8a66597_mdfy(r8a66597, val, 0, offset)
568
569 static inline unsigned long get_syscfg_reg(int port)
570 {
571 return port == 0 ? SYSCFG0 : SYSCFG1;
572 }
573
574 static inline unsigned long get_syssts_reg(int port)
575 {
576 return port == 0 ? SYSSTS0 : SYSSTS1;
577 }
578
579 static inline unsigned long get_dvstctr_reg(int port)
580 {
581 return port == 0 ? DVSTCTR0 : DVSTCTR1;
582 }
583
584 static inline unsigned long get_intenb_reg(int port)
585 {
586 return port == 0 ? INTENB1 : INTENB2;
587 }
588
589 static inline unsigned long get_intsts_reg(int port)
590 {
591 return port == 0 ? INTSTS1 : INTSTS2;
592 }
593
594 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
595 {
596 unsigned long dvstctr_reg = get_dvstctr_reg(port);
597
598 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
599 }
600
601 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
602 int power)
603 {
604 unsigned long dvstctr_reg = get_dvstctr_reg(port);
605
606 if (power)
607 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
608 else
609 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
610 }
611
612 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
613 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
614 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
615 #define get_devadd_addr(address) (DEVADD0 + address * 2)
616
617 #define enable_irq_ready(r8a66597, pipenum) \
618 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
619 #define disable_irq_ready(r8a66597, pipenum) \
620 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
621 #define enable_irq_empty(r8a66597, pipenum) \
622 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
623 #define disable_irq_empty(r8a66597, pipenum) \
624 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
625 #define enable_irq_nrdy(r8a66597, pipenum) \
626 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
627 #define disable_irq_nrdy(r8a66597, pipenum) \
628 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
629
630 #endif /* __R8A66597_H__ */
631
Tomato firmware and modifications.