release/src-rt-6.x/linux/linux-2.6/drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         u32                     temp;
  31         int                     retval;
  32
  33         /* optional debug port, normally in the first BAR */
  34         temp = pci_find_capability(pdev, 0x0a);
  35         if (temp) {
  36                 pci_read_config_dword(pdev, temp, &temp);
  37                 temp >>= 16;
  38                 if ((temp & (3 << 13)) == (1 << 13)) {
  39                         temp &= 0x1fff;
  40                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
  41                         temp = ehci_readl(ehci, &ehci->debug->control);
  42                         ehci_info(ehci, "debug port %d%s\n",
  43                                 HCS_DEBUG_PORT(ehci->hcs_params),
  44                                 (temp & DBGP_ENABLED)
  45                                         ? " IN USE"
  46                                         : "");
  47                         if (!(temp & DBGP_ENABLED))
  48                                 ehci->debug = NULL;
  49                 }
  50         }
  51
  52         /* we expect static quirk code to handle the "extended capabilities"
  53          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  54          */
  55
  56         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  57         retval = pci_set_mwi(pdev);
  58         if (!retval)
  59                 ehci_dbg(ehci, "MWI active\n");
  60
  61         return 0;
  62 }
  63
  64 /* called during probe() after chip reset completes */
  65 static int ehci_pci_setup(struct usb_hcd *hcd)
  66 {
  67         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  68         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  69         u32                     temp;
  70         int                     retval;
  71
  72         switch (pdev->vendor) {
  73         case PCI_VENDOR_ID_TOSHIBA_2:
  74                 /* celleb's companion chip */
  75                 if (pdev->device == 0x01b5) {
  76 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  77                         ehci->big_endian_mmio = 1;
  78 #else
  79                         ehci_warn(ehci,
  80                                   "unsupported big endian Toshiba quirk\n");
  81 #endif
  82                 }
  83                 break;
  84         }
  85
  86         ehci->caps = hcd->regs;
  87         ehci->regs = hcd->regs +
  88                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  89
  90         dbg_hcs_params(ehci, "reset");
  91         dbg_hcc_params(ehci, "reset");
  92
  93         /* ehci_init() causes memory for DMA transfers to be
  94          * allocated.  Thus, any vendor-specific workarounds based on
  95          * limiting the type of memory used for DMA transfers must
  96          * happen before ehci_init() is called. */
  97         switch (pdev->vendor) {
  98         case PCI_VENDOR_ID_NVIDIA:
  99                 /* NVidia reports that certain chips don't handle
 100                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 101                  * data buffer, and periodic schedule are normal.)
 102                  */
 103                 switch (pdev->device) {
 104                 case 0x003c:    /* MCP04 */
 105                 case 0x005b:    /* CK804 */
 106                 case 0x00d8:    /* CK8 */
 107                 case 0x00e8:    /* CK8S */
 108                         if (pci_set_consistent_dma_mask(pdev,
 109                                                 DMA_31BIT_MASK) < 0)
 110                                 ehci_warn(ehci, "can't enable NVidia "
 111                                         "workaround for >2GB RAM\n");
 112                         break;
 113                 }
 114                 break;
 115         }
 116
 117         /* cache this readonly data; minimize chip reads */
 118         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 119
 120         retval = ehci_halt(ehci);
 121         if (retval)
 122                 return retval;
 123
 124         if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
 125             (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
 126                 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 127                  * read/write memory space which does not belong to it when
 128                  * there is NULL pointer with T-bit set to 1 in the frame list
 129                  * table. To avoid the issue, the frame list link pointer
 130                  * should always contain a valid pointer to a inactive qh.
 131                  */
 132                 ehci->use_dummy_qh = 1;
 133                 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
 134                                 "dummy qh workaround\n");
 135         }
 136
 137         /* data structure init */
 138         retval = ehci_init(hcd);
 139         if (retval)
 140                 return retval;
 141
 142         switch (pdev->vendor) {
 143         case PCI_VENDOR_ID_NEC:
 144                 ehci->need_io_watchdog = 0;
 145                 break;
 146         case PCI_VENDOR_ID_INTEL:
 147                 ehci->need_io_watchdog = 0;
 148                 ehci->fs_i_thresh = 1;
 149                 if (pdev->device == 0x27cc) {
 150                         ehci->broken_periodic = 1;
 151                         ehci_info(ehci, "using broken periodic workaround\n");
 152                 }
 153                 break;
 154         case PCI_VENDOR_ID_TDI:
 155                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 156                         hcd->has_tt = 1;
 157                         tdi_reset(ehci);
 158                 }
 159                 break;
 160         case PCI_VENDOR_ID_AMD:
 161                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 162                 if (pdev->device == 0x7463) {
 163                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 164                         retval = -EIO;
 165                         goto done;
 166                 }
 167                 break;
 168         case PCI_VENDOR_ID_NVIDIA:
 169                 switch (pdev->device) {
 170                 /* Some NForce2 chips have problems with selective suspend;
 171                  * fixed in newer silicon.
 172                  */
 173                 case 0x0068:
 174                         pci_read_config_dword(pdev, PCI_REVISION_ID, &temp);
 175                         if ((temp & 0xff) < 0xa4)
 176                                 ehci->no_selective_suspend = 1;
 177                         break;
 178                 }
 179                 break;
 180         case PCI_VENDOR_ID_VIA:
 181                 pci_read_config_dword(pdev, PCI_REVISION_ID, &temp);
 182                 if (pdev->device == 0x3104 && ((temp & 0xff) & 0xf0) == 0x60) {
 183                         u8 tmp;
 184
 185                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 186                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 187                          * that sleep time use the conventional 10 usec.
 188                          */
 189                         pci_read_config_byte(pdev, 0x4b, &tmp);
 190                         if (tmp & 0x20)
 191                                 break;
 192                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 193                 }
 194                 break;
 195         }
 196
 197         ehci_reset(ehci);
 198
 199         /* at least the Genesys GL880S needs fixup here */
 200         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 201         temp &= 0x0f;
 202         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 203                 ehci_dbg(ehci, "bogus port configuration: "
 204                         "cc=%d x pcc=%d < ports=%d\n",
 205                         HCS_N_CC(ehci->hcs_params),
 206                         HCS_N_PCC(ehci->hcs_params),
 207                         HCS_N_PORTS(ehci->hcs_params));
 208
 209                 switch (pdev->vendor) {
 210                 case 0x17a0:            /* GENESYS */
 211                         /* GL880S: should be PORTS=2 */
 212                         temp |= (ehci->hcs_params & ~0xf);
 213                         ehci->hcs_params = temp;
 214                         break;
 215                 case PCI_VENDOR_ID_NVIDIA:
 216                         /* NF4: should be PCC=10 */
 217                         break;
 218                 }
 219         }
 220
 221         /* Serial Bus Release Number is at PCI 0x60 offset */
 222         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 223
 224         /* Workaround current PCI init glitch:  wakeup bits aren't
 225          * being set from PCI PM capability.
 226          */
 227         if (!device_can_wakeup(&pdev->dev)) {
 228                 u16     port_wake;
 229
 230                 pci_read_config_word(pdev, 0x62, &port_wake);
 231                 if (port_wake & 0x0001)
 232                         device_init_wakeup(&pdev->dev, 1);
 233         }
 234
 235 #ifdef  CONFIG_USB_SUSPEND
 236         /* REVISIT: the controller works fine for wakeup iff the root hub
 237          * itself is "globally" suspended, but usbcore currently doesn't
 238          * understand such things.
 239          *
 240          * System suspend currently expects to be able to suspend the entire
 241          * device tree, device-at-a-time.  If we failed selective suspend
 242          * reports, system suspend would fail; so the root hub code must claim
 243          * success.  That's lying to usbcore, and it matters for for runtime
 244          * PM scenarios with selective suspend and remote wakeup...
 245          */
 246         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 247                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 248 #endif
 249
 250         ehci_port_power(ehci, 1);
 251         retval = ehci_pci_reinit(ehci, pdev);
 252 done:
 253         return retval;
 254 }
 255
 256 /*-------------------------------------------------------------------------*/
 257
 258 #ifdef  CONFIG_PM
 259
 260 /* suspend/resume, section 4.3 */
 261
 262 /* These routines rely on the PCI bus glue
 263  * to handle powerdown and wakeup, and currently also on
 264  * transceivers that don't need any software attention to set up
 265  * the right sort of wakeup.
 266  * Also they depend on separate root hub suspend/resume.
 267  */
 268
 269 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
 270 {
 271         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 272         unsigned long           flags;
 273         int                     rc = 0;
 274
 275         if (time_before(jiffies, ehci->next_statechange))
 276                 msleep(10);
 277
 278         /* Root hub was already suspended. Disable irq emission and
 279          * mark HW unaccessible, bail out if RH has been resumed. Use
 280          * the spinlock to properly synchronize with possible pending
 281          * RH suspend or resume activity.
 282          *
 283          * This is still racy as hcd->state is manipulated outside of
 284          * any locks =P But that will be a different fix.
 285          */
 286         spin_lock_irqsave (&ehci->lock, flags);
 287         if (hcd->state != HC_STATE_SUSPENDED) {
 288                 rc = -EINVAL;
 289                 goto bail;
 290         }
 291         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 292         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 293
 294         /* make sure snapshot being resumed re-enumerates everything */
 295         if (message.event == PM_EVENT_PRETHAW) {
 296                 ehci_halt(ehci);
 297                 ehci_reset(ehci);
 298         }
 299
 300         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 301  bail:
 302         spin_unlock_irqrestore (&ehci->lock, flags);
 303
 304         // could save FLADJ in case of Vaux power loss
 305         // ... we'd only use it to handle clock skew
 306
 307         return rc;
 308 }
 309
 310 static int ehci_pci_resume(struct usb_hcd *hcd)
 311 {
 312         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 313         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 314
 315         // maybe restore FLADJ
 316
 317         if (time_before(jiffies, ehci->next_statechange))
 318                 msleep(100);
 319
 320         /* Mark hardware accessible again as we are out of D3 state by now */
 321         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 322
 323         /* If CF is still set, we maintained PCI Vaux power.
 324          * Just undo the effect of ehci_pci_suspend().
 325          */
 326         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
 327                 int     mask = INTR_MASK;
 328
 329                 if (!hcd->self.root_hub->do_remote_wakeup)
 330                         mask &= ~STS_PCD;
 331                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 332                 ehci_readl(ehci, &ehci->regs->intr_enable);
 333                 return 0;
 334         }
 335
 336         ehci_dbg(ehci, "lost power, restarting\n");
 337         usb_root_hub_lost_power(hcd->self.root_hub);
 338
 339         /* Else reset, to cope with power loss or flush-to-storage
 340          * style "resume" having let BIOS kick in during reboot.
 341          */
 342         (void) ehci_halt(ehci);
 343         (void) ehci_reset(ehci);
 344         (void) ehci_pci_reinit(ehci, pdev);
 345
 346         /* emptying the schedule aborts any urbs */
 347         spin_lock_irq(&ehci->lock);
 348         if (ehci->reclaim)
 349                 end_unlink_async(ehci);
 350         ehci_work(ehci);
 351         spin_unlock_irq(&ehci->lock);
 352
 353         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 354         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 355         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 356
 357         /* here we "know" root ports should always stay powered */
 358         ehci_port_power(ehci, 1);
 359
 360         hcd->state = HC_STATE_SUSPENDED;
 361         return 0;
 362 }
 363 #endif
 364
 365 static const struct hc_driver ehci_pci_hc_driver = {
 366         .description =          hcd_name,
 367         .product_desc =         "EHCI Host Controller",
 368         .hcd_priv_size =        sizeof(struct ehci_hcd),
 369
 370         /*
 371          * generic hardware linkage
 372          */
 373         .irq =                  ehci_irq,
 374         .flags =                HCD_MEMORY | HCD_USB2,
 375
 376         /*
 377          * basic lifecycle operations
 378          */
 379         .reset =                ehci_pci_setup,
 380         .start =                ehci_run,
 381 #ifdef  CONFIG_PM
 382         .pci_suspend =          ehci_pci_suspend,
 383         .pci_resume =           ehci_pci_resume,
 384 #endif
 385         .stop =                 ehci_stop,
 386         .shutdown =             ehci_shutdown,
 387
 388         /*
 389          * managing i/o requests and associated device resources
 390          */
 391         .urb_enqueue =          ehci_urb_enqueue,
 392         .urb_dequeue =          ehci_urb_dequeue,
 393         .endpoint_disable =     ehci_endpoint_disable,
 394
 395         /*
 396          * scheduling support
 397          */
 398         .get_frame_number =     ehci_get_frame,
 399
 400         /*
 401          * root hub support
 402          */
 403         .hub_status_data =      ehci_hub_status_data,
 404         .hub_control =          ehci_hub_control,
 405         .bus_suspend =          ehci_bus_suspend,
 406         .bus_resume =           ehci_bus_resume,
 407         .relinquish_port =      ehci_relinquish_port,
 408         .port_handed_over =     ehci_port_handed_over,
 409 };
 410
 411 /*-------------------------------------------------------------------------*/
 412
 413 /* PCI driver selection metadata; PCI hotplugging uses this */
 414 static const struct pci_device_id pci_ids [] = { {
 415         /* handle any USB 2.0 EHCI controller */
 416         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 417         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 418         },
 419         { /* end: all zeroes */ }
 420 };
 421 MODULE_DEVICE_TABLE(pci, pci_ids);
 422
 423 /* pci driver glue; this is a "new style" PCI driver module */
 424 static struct pci_driver ehci_pci_driver = {
 425         .name =         (char *) hcd_name,
 426         .id_table =     pci_ids,
 427
 428         .probe =        usb_hcd_pci_probe,
 429         .remove =       usb_hcd_pci_remove,
 430
 431 #ifdef  CONFIG_PM
 432         .suspend =      usb_hcd_pci_suspend,
 433         .resume =       usb_hcd_pci_resume,
 434 #endif
 435         .shutdown =     usb_hcd_pci_shutdown,
 436 };