2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/ktime.h>
32 #include <linux/list.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
35 #include <linux/usb.h>
36 #include <linux/moduleparam.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/debugfs.h>
40 #include "../core/hcd.h"
42 #include <asm/byteorder.h>
45 #include <asm/system.h>
46 #include <asm/unaligned.h>
48 /*-------------------------------------------------------------------------*/
51 * EHCI hc_driver implementation ... experimental, incomplete.
52 * Based on the final 1.0 register interface specification.
54 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
55 * First was PCMCIA, like ISA; then CardBus, which is PCI.
56 * Next comes "CardBay", using USB 2.0 signals.
58 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
59 * Special thanks to Intel and VIA for providing host controllers to
60 * test this driver on, and Cypress (including In-System Design) for
61 * providing early devices for those host controllers to talk to!
64 #define DRIVER_AUTHOR "David Brownell"
65 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
67 static const char hcd_name
[] = "ehci_hcd";
77 /* magic numbers that can affect system performance */
78 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
79 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
80 #define EHCI_TUNE_RL_TT 0
81 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
82 #define EHCI_TUNE_MULT_TT 1
84 * Some drivers think it's safe to schedule isochronous transfers more than
85 * 256 ms into the future (partly as a result of an old bug in the scheduling
86 * code). In an attempt to avoid trouble, we will use a minimum scheduling
87 * length of 512 frames instead of 256.
89 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
91 #define EHCI_IAA_MSECS 10 /* arbitrary */
92 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
93 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
94 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
96 /* Initial IRQ latency: faster than hw default */
97 static int log2_irq_thresh
= 0; // 0 to 6
98 module_param (log2_irq_thresh
, int, S_IRUGO
);
99 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
101 /* initial park setting: slower than hw default */
102 static unsigned park
= 0;
103 module_param (park
, uint
, S_IRUGO
);
104 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
106 /* for flakey hardware, ignore overcurrent indicators */
107 static int ignore_oc
= 0;
108 module_param (ignore_oc
, bool, S_IRUGO
);
109 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
111 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
113 /*-------------------------------------------------------------------------*/
116 #include "ehci-dbg.c"
118 /*-------------------------------------------------------------------------*/
121 timer_action(struct ehci_hcd
*ehci
, enum ehci_timer_action action
)
123 /* Don't override timeouts which shrink or (later) disable
124 * the async ring; just the I/O watchdog. Note that if a
125 * SHRINK were pending, OFF would never be requested.
127 if (timer_pending(&ehci
->watchdog
)
128 && ((BIT(TIMER_ASYNC_SHRINK
) | BIT(TIMER_ASYNC_OFF
))
132 if (!test_and_set_bit(action
, &ehci
->actions
)) {
136 case TIMER_IO_WATCHDOG
:
137 if (!ehci
->need_io_watchdog
)
141 case TIMER_ASYNC_OFF
:
142 t
= EHCI_ASYNC_JIFFIES
;
144 /* case TIMER_ASYNC_SHRINK: */
146 /* add a jiffie since we synch against the
147 * 8 KHz uframe counter.
149 t
= DIV_ROUND_UP(EHCI_SHRINK_FRAMES
* HZ
, 1000) + 1;
152 mod_timer(&ehci
->watchdog
, t
+ jiffies
);
156 /*-------------------------------------------------------------------------*/
159 * handshake - spin reading hc until handshake completes or fails
160 * @ptr: address of hc register to be read
161 * @mask: bits to look at in result of read
162 * @done: value of those bits when handshake succeeds
163 * @usec: timeout in microseconds
165 * Returns negative errno, or zero on success
167 * Success happens when the "mask" bits have the specified value (hardware
168 * handshake done). There are two failure modes: "usec" have passed (major
169 * hardware flakeout), or the register reads as all-ones (hardware removed).
171 * That last failure should_only happen in cases like physical cardbus eject
172 * before driver shutdown. But it also seems to be caused by bugs in cardbus
173 * bridge shutdown: shutting down the bridge before the devices using it.
175 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
176 u32 mask
, u32 done
, int usec
)
181 result
= ehci_readl(ehci
, ptr
);
182 if (result
== ~(u32
)0) /* card removed */
193 /* force HC to halt state from unknown (EHCI spec section 2.3) */
194 static int ehci_halt (struct ehci_hcd
*ehci
)
196 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
198 /* disable any irqs left enabled by previous code */
199 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
201 if ((temp
& STS_HALT
) != 0)
204 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
206 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
207 return handshake (ehci
, &ehci
->regs
->status
,
208 STS_HALT
, STS_HALT
, 16 * 125);
211 static int handshake_on_error_set_halt(struct ehci_hcd
*ehci
, void __iomem
*ptr
,
212 u32 mask
, u32 done
, int usec
)
216 error
= handshake(ehci
, ptr
, mask
, done
, usec
);
219 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
220 ehci_err(ehci
, "force halt; handshake %p %08x %08x -> %d\n",
221 ptr
, mask
, done
, error
);
227 /* put TDI/ARC silicon into EHCI mode */
228 static void tdi_reset (struct ehci_hcd
*ehci
)
230 u32 __iomem
*reg_ptr
;
233 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + USBMODE
);
234 tmp
= ehci_readl(ehci
, reg_ptr
);
235 tmp
|= USBMODE_CM_HC
;
236 /* The default byte access to MMR space is LE after
237 * controller reset. Set the required endian mode
238 * for transfer buffers to match the host microprocessor
240 if (ehci_big_endian_mmio(ehci
))
242 ehci_writel(ehci
, tmp
, reg_ptr
);
245 /* reset a non-running (STS_HALT == 1) controller */
246 static int ehci_reset (struct ehci_hcd
*ehci
)
249 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
251 command
|= CMD_RESET
;
252 dbg_cmd (ehci
, "reset", command
);
253 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
254 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
255 ehci
->next_statechange
= jiffies
;
256 retval
= handshake (ehci
, &ehci
->regs
->command
,
257 CMD_RESET
, 0, 250 * 1000);
262 if (ehci_is_TDI(ehci
))
268 /* idle the controller (from running) */
269 static void ehci_quiesce (struct ehci_hcd
*ehci
)
274 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
278 /* wait for any schedule enables/disables to take effect */
279 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
280 temp
&= STS_ASS
| STS_PSS
;
281 if (handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
282 STS_ASS
| STS_PSS
, temp
, 16 * 125))
285 /* then disable anything that's still active */
286 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
287 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
288 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
290 /* hardware can take 16 microframes to turn off ... */
291 handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
292 STS_ASS
| STS_PSS
, 0, 16 * 125);
295 /*-------------------------------------------------------------------------*/
297 static void end_unlink_async(struct ehci_hcd
*ehci
);
298 static void ehci_work(struct ehci_hcd
*ehci
);
300 #include "ehci-hub.c"
301 #include "ehci-mem.c"
303 #include "ehci-sched.c"
305 /*-------------------------------------------------------------------------*/
307 static void ehci_iaa_watchdog(unsigned long param
)
309 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
312 spin_lock_irqsave (&ehci
->lock
, flags
);
314 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
315 * So we need this watchdog, but must protect it against both
316 * (a) SMP races against real IAA firing and retriggering, and
317 * (b) clean HC shutdown, when IAA watchdog was pending.
320 && !timer_pending(&ehci
->iaa_watchdog
)
321 && HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
)) {
324 /* If we get here, IAA is *REALLY* late. It's barely
325 * conceivable that the system is so busy that CMD_IAAD
326 * is still legitimately set, so let's be sure it's
327 * clear before we read STS_IAA. (The HC should clear
328 * CMD_IAAD when it sets STS_IAA.)
330 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
);
332 ehci_writel(ehci
, cmd
& ~CMD_IAAD
,
333 &ehci
->regs
->command
);
335 /* If IAA is set here it either legitimately triggered
336 * before we cleared IAAD above (but _way_ late, so we'll
337 * still count it as lost) ... or a silicon erratum:
338 * - VIA seems to set IAA without triggering the IRQ;
339 * - IAAD potentially cleared without setting IAA.
341 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
342 if ((status
& STS_IAA
) || !(cmd
& CMD_IAAD
)) {
343 COUNT (ehci
->stats
.lost_iaa
);
344 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
347 ehci_vdbg(ehci
, "IAA watchdog: status %x cmd %x\n",
349 end_unlink_async(ehci
);
352 spin_unlock_irqrestore(&ehci
->lock
, flags
);
355 static void ehci_watchdog(unsigned long param
)
357 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
360 spin_lock_irqsave(&ehci
->lock
, flags
);
362 /* stop async processing after it's idled a bit */
363 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
364 start_unlink_async (ehci
, ehci
->async
);
366 /* ehci could run by timer, without IRQs ... */
369 spin_unlock_irqrestore (&ehci
->lock
, flags
);
372 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
373 * The firmware seems to think that powering off is a wakeup event!
374 * This routine turns off remote wakeup and everything else, on all ports.
376 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
378 int port
= HCS_N_PORTS(ehci
->hcs_params
);
381 ehci_writel(ehci
, PORT_RWC_BITS
,
382 &ehci
->regs
->port_status
[port
]);
386 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
387 * Should be called with ehci->lock held.
389 static void ehci_silence_controller(struct ehci_hcd
*ehci
)
392 ehci_turn_off_all_ports(ehci
);
394 /* make BIOS/etc use companion controller during reboot */
395 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
397 /* unblock posted writes */
398 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
401 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
402 * This forcibly disables dma and IRQs, helping kexec and other cases
403 * where the next system software may expect clean state.
405 static void ehci_shutdown(struct usb_hcd
*hcd
)
407 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
409 del_timer_sync(&ehci
->watchdog
);
410 del_timer_sync(&ehci
->iaa_watchdog
);
412 spin_lock_irq(&ehci
->lock
);
413 ehci_silence_controller(ehci
);
414 spin_unlock_irq(&ehci
->lock
);
417 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
421 if (!HCS_PPC (ehci
->hcs_params
))
424 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
425 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
426 (void) ehci_hub_control(ehci_to_hcd(ehci
),
427 is_on
? SetPortFeature
: ClearPortFeature
,
430 /* Flush those writes */
431 ehci_readl(ehci
, &ehci
->regs
->command
);
435 /*-------------------------------------------------------------------------*/
438 * ehci_work is called from some interrupts, timers, and so on.
439 * it calls driver completion functions, after dropping ehci->lock.
441 static void ehci_work (struct ehci_hcd
*ehci
)
443 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
445 /* another CPU may drop ehci->lock during a schedule scan while
446 * it reports urb completions. this flag guards against bogus
447 * attempts at re-entrant schedule scanning.
453 if (ehci
->next_uframe
!= -1)
454 scan_periodic (ehci
);
457 /* the IO watchdog guards against hardware or driver bugs that
458 * misplace IRQs, and should let us run completely without IRQs.
459 * such lossage has been observed on both VT6202 and VT8235.
461 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
462 (ehci
->async
->qh_next
.ptr
!= NULL
||
463 ehci
->periodic_sched
!= 0))
464 timer_action (ehci
, TIMER_IO_WATCHDOG
);
468 * Called when the ehci_hcd module is removed.
470 static void ehci_stop (struct usb_hcd
*hcd
)
472 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
474 ehci_dbg (ehci
, "stop\n");
476 /* no more interrupts ... */
477 del_timer_sync (&ehci
->watchdog
);
478 del_timer_sync(&ehci
->iaa_watchdog
);
480 spin_lock_irq(&ehci
->lock
);
481 if (HC_IS_RUNNING (hcd
->state
))
484 ehci_silence_controller(ehci
);
486 spin_unlock_irq(&ehci
->lock
);
488 remove_companion_file(ehci
);
489 remove_debug_files (ehci
);
491 /* root hub is shut down separately (first, when possible) */
492 spin_lock_irq (&ehci
->lock
);
495 spin_unlock_irq (&ehci
->lock
);
496 ehci_mem_cleanup (ehci
);
499 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
500 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
501 ehci
->stats
.lost_iaa
);
502 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
503 ehci
->stats
.complete
, ehci
->stats
.unlink
);
506 dbg_status (ehci
, "ehci_stop completed",
507 ehci_readl(ehci
, &ehci
->regs
->status
));
510 /* one-time init, only for memory state */
511 static int ehci_init(struct usb_hcd
*hcd
)
513 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
517 struct ehci_qh_hw
*hw
;
519 spin_lock_init(&ehci
->lock
);
522 * keep io watchdog by default, those good HCDs could turn off it later
524 ehci
->need_io_watchdog
= 1;
525 init_timer(&ehci
->watchdog
);
526 ehci
->watchdog
.function
= ehci_watchdog
;
527 ehci
->watchdog
.data
= (unsigned long) ehci
;
529 init_timer(&ehci
->iaa_watchdog
);
530 ehci
->iaa_watchdog
.function
= ehci_iaa_watchdog
;
531 ehci
->iaa_watchdog
.data
= (unsigned long) ehci
;
533 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
536 * hw default: 1K periodic list heads, one per frame.
537 * periodic_size can shrink by USBCMD update if hcc_params allows.
539 ehci
->periodic_size
= DEFAULT_I_TDPS
;
540 INIT_LIST_HEAD(&ehci
->cached_itd_list
);
541 INIT_LIST_HEAD(&ehci
->cached_sitd_list
);
543 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
544 /* periodic schedule size can be smaller than default */
545 switch (EHCI_TUNE_FLS
) {
546 case 0: ehci
->periodic_size
= 1024; break;
547 case 1: ehci
->periodic_size
= 512; break;
548 case 2: ehci
->periodic_size
= 256; break;
552 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
555 /* controllers may cache some of the periodic schedule ... */
556 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
557 ehci
->i_thresh
= 2 + 8;
558 else // N microframes cached
559 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
561 ehci
->reclaim
= NULL
;
562 ehci
->next_uframe
= -1;
563 ehci
->clock_frame
= -1;
566 * dedicate a qh for the async ring head, since we couldn't unlink
567 * a 'real' qh without stopping the async schedule [4.8]. use it
568 * as the 'reclamation list head' too.
569 * its dummy is used in hw_alt_next of many tds, to prevent the qh
570 * from automatically advancing to the next td after short reads.
572 ehci
->async
->qh_next
.qh
= NULL
;
573 hw
= ehci
->async
->hw
;
574 hw
->hw_next
= QH_NEXT(ehci
, ehci
->async
->qh_dma
);
575 hw
->hw_info1
= cpu_to_hc32(ehci
, QH_HEAD
);
576 hw
->hw_token
= cpu_to_hc32(ehci
, QTD_STS_HALT
);
577 hw
->hw_qtd_next
= EHCI_LIST_END(ehci
);
578 ehci
->async
->qh_state
= QH_STATE_LINKED
;
579 hw
->hw_alt_next
= QTD_NEXT(ehci
, ehci
->async
->dummy
->qtd_dma
);
581 /* clear interrupt enables, set irq latency */
582 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
584 temp
= 1 << (16 + log2_irq_thresh
);
585 if (HCC_CANPARK(hcc_params
)) {
586 /* HW default park == 3, on hardware that supports it (like
587 * NVidia and ALI silicon), maximizes throughput on the async
588 * schedule by avoiding QH fetches between transfers.
590 * With fast usb storage devices and NForce2, "park" seems to
591 * make problems: throughput reduction (!), data errors...
594 park
= min(park
, (unsigned) 3);
598 ehci_dbg(ehci
, "park %d\n", park
);
600 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
601 /* periodic schedule size can be smaller than default */
603 temp
|= (EHCI_TUNE_FLS
<< 2);
605 ehci
->command
= temp
;
610 /* start HC running; it's halted, ehci_init() has been run (once) */
611 static int ehci_run (struct usb_hcd
*hcd
)
613 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
618 hcd
->uses_new_polling
= 1;
621 /* EHCI spec section 4.1 */
622 if ((retval
= ehci_reset(ehci
)) != 0) {
623 ehci_mem_cleanup(ehci
);
626 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
627 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
630 * hcc_params controls whether ehci->regs->segment must (!!!)
631 * be used; it constrains QH/ITD/SITD and QTD locations.
632 * pci_pool consistent memory always uses segment zero.
633 * streaming mappings for I/O buffers, like pci_map_single(),
634 * can return segments above 4GB, if the device allows.
636 * NOTE: the dma mask is visible through dma_supported(), so
637 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
638 * Scsi_Host.highmem_io, and so forth. It's readonly to all
639 * host side drivers though.
641 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
642 if (HCC_64BIT_ADDR(hcc_params
)) {
643 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
645 // this is deeply broken on almost all architectures
646 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
647 ehci_info(ehci
, "enabled 64bit DMA\n");
652 // Philips, Intel, and maybe others need CMD_RUN before the
653 // root hub will detect new devices (why?); NEC doesn't
654 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
655 ehci
->command
|= CMD_RUN
;
656 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
657 dbg_cmd (ehci
, "init", ehci
->command
);
660 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
661 * are explicitly handed to companion controller(s), so no TT is
662 * involved with the root hub. (Except where one is integrated,
663 * and there's no companion controller unless maybe for USB OTG.)
665 * Turning on the CF flag will transfer ownership of all ports
666 * from the companions to the EHCI controller. If any of the
667 * companions are in the middle of a port reset at the time, it
668 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
669 * guarantees that no resets are in progress. After we set CF,
670 * a short delay lets the hardware catch up; new resets shouldn't
671 * be started before the port switching actions could complete.
673 down_write(&ehci_cf_port_reset_rwsem
);
674 hcd
->state
= HC_STATE_RUNNING
;
675 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
676 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
678 up_write(&ehci_cf_port_reset_rwsem
);
679 ehci
->last_periodic_enable
= ktime_get_real();
681 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
683 "USB %x.%x started, EHCI %x.%02x%s\n",
684 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
685 temp
>> 8, temp
& 0xff,
686 ignore_oc
? ", overcurrent ignored" : "");
688 ehci_writel(ehci
, INTR_MASK
,
689 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
691 /* GRR this is run-once init(), being done every time the HC starts.
692 * So long as they're part of class devices, we can't do it init()
693 * since the class device isn't created that early.
695 create_debug_files(ehci
);
696 create_companion_file(ehci
);
701 /*-------------------------------------------------------------------------*/
703 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
705 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
706 u32 status
, masked_status
, pcd_status
= 0, cmd
;
709 spin_lock (&ehci
->lock
);
711 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
713 /* e.g. cardbus physical eject */
714 if (status
== ~(u32
) 0) {
715 ehci_dbg (ehci
, "device removed\n");
719 masked_status
= status
& INTR_MASK
;
720 if (!masked_status
) { /* irq sharing? */
721 spin_unlock(&ehci
->lock
);
725 /* clear (just) interrupts */
726 ehci_writel(ehci
, masked_status
, &ehci
->regs
->status
);
727 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
);
731 /* unrequested/ignored: Frame List Rollover */
732 dbg_status (ehci
, "irq", status
);
735 /* INT, ERR, and IAA interrupt rates can be throttled */
737 /* normal [4.15.1.2] or error [4.15.1.1] completion */
738 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
739 if (likely ((status
& STS_ERR
) == 0))
740 COUNT (ehci
->stats
.normal
);
742 COUNT (ehci
->stats
.error
);
746 /* complete the unlinking of some qh [4.15.2.3] */
747 if (status
& STS_IAA
) {
748 /* guard against (alleged) silicon errata */
749 if (cmd
& CMD_IAAD
) {
750 ehci_writel(ehci
, cmd
& ~CMD_IAAD
,
751 &ehci
->regs
->command
);
752 ehci_dbg(ehci
, "IAA with IAAD still set?\n");
755 COUNT(ehci
->stats
.reclaim
);
756 end_unlink_async(ehci
);
758 ehci_dbg(ehci
, "IAA with nothing to reclaim?\n");
761 /* remote wakeup [4.3.1] */
762 if (status
& STS_PCD
) {
763 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
765 /* kick root hub later */
768 /* resume root hub? */
769 if (!(cmd
& CMD_RUN
))
770 usb_hcd_resume_root_hub(hcd
);
773 int pstatus
= ehci_readl(ehci
,
774 &ehci
->regs
->port_status
[i
]);
776 if (pstatus
& PORT_OWNER
)
778 if (!(test_bit(i
, &ehci
->suspended_ports
) &&
779 ((pstatus
& PORT_RESUME
) ||
780 !(pstatus
& PORT_SUSPEND
)) &&
781 (pstatus
& PORT_PE
) &&
782 ehci
->reset_done
[i
] == 0))
785 /* start 20 msec resume signaling from this port,
786 * and make khubd collect PORT_STAT_C_SUSPEND to
787 * stop that signaling. Use 5 ms extra for safety,
788 * like usb_port_resume() does.
790 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies(25);
791 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
792 mod_timer(&hcd
->rh_timer
, ehci
->reset_done
[i
]);
796 /* PCI errors [4.15.2.4] */
797 if (unlikely ((status
& STS_FATAL
) != 0)) {
798 ehci_err(ehci
, "fatal error\n");
799 dbg_cmd(ehci
, "fatal", cmd
);
800 dbg_status(ehci
, "fatal", status
);
804 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
805 /* generic layer kills/unlinks all urbs, then
806 * uses ehci_stop to clean up the rest
813 spin_unlock (&ehci
->lock
);
815 usb_hcd_poll_rh_status(hcd
);
819 /*-------------------------------------------------------------------------*/
822 * non-error returns are a promise to giveback() the urb later
823 * we drop ownership so next owner (or urb unlink) can get it
825 * urb + dev is in hcd.self.controller.urb_list
826 * we're queueing TDs onto software and hardware lists
828 * hcd-specific init for hcpriv hasn't been done yet
830 * NOTE: control, bulk, and interrupt share the same code to append TDs
831 * to a (possibly active) QH, and the same QH scanning code.
833 static int ehci_urb_enqueue (
838 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
839 struct list_head qtd_list
;
841 INIT_LIST_HEAD (&qtd_list
);
843 switch (usb_pipetype (urb
->pipe
)) {
845 /* qh_completions() code doesn't handle all the fault cases
846 * in multi-TD control transfers. Even 1KB is rare anyway.
848 if (urb
->transfer_buffer_length
> (16 * 1024))
851 /* case PIPE_BULK: */
853 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
855 return submit_async(ehci
, urb
, &qtd_list
, mem_flags
);
858 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
860 return intr_submit(ehci
, urb
, &qtd_list
, mem_flags
);
862 case PIPE_ISOCHRONOUS
:
863 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
864 return itd_submit (ehci
, urb
, mem_flags
);
866 return sitd_submit (ehci
, urb
, mem_flags
);
870 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
873 if (!HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
874 end_unlink_async(ehci
);
876 /* If the QH isn't linked then there's nothing we can do
877 * unless we were called during a giveback, in which case
878 * qh_completions() has to deal with it.
880 if (qh
->qh_state
!= QH_STATE_LINKED
) {
881 if (qh
->qh_state
== QH_STATE_COMPLETING
)
882 qh
->needs_rescan
= 1;
886 /* defer till later if busy */
888 struct ehci_qh
*last
;
890 for (last
= ehci
->reclaim
;
892 last
= last
->reclaim
)
894 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
897 /* start IAA cycle */
899 start_unlink_async (ehci
, qh
);
902 /* remove from hardware lists
903 * completions normally happen asynchronously
906 static int ehci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
908 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
913 spin_lock_irqsave (&ehci
->lock
, flags
);
914 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
918 switch (usb_pipetype (urb
->pipe
)) {
919 // case PIPE_CONTROL:
922 qh
= (struct ehci_qh
*) urb
->hcpriv
;
925 switch (qh
->qh_state
) {
926 case QH_STATE_LINKED
:
927 case QH_STATE_COMPLETING
:
928 unlink_async(ehci
, qh
);
930 case QH_STATE_UNLINK
:
931 case QH_STATE_UNLINK_WAIT
:
932 /* already started */
941 qh
= (struct ehci_qh
*) urb
->hcpriv
;
944 switch (qh
->qh_state
) {
945 case QH_STATE_LINKED
:
946 case QH_STATE_COMPLETING
:
947 intr_deschedule (ehci
, qh
);
950 qh_completions (ehci
, qh
);
953 ehci_dbg (ehci
, "bogus qh %p state %d\n",
959 case PIPE_ISOCHRONOUS
:
962 // wait till next completion, do it then.
963 // completion irqs can wait up to 1024 msec,
967 spin_unlock_irqrestore (&ehci
->lock
, flags
);
971 /*-------------------------------------------------------------------------*/
973 // bulk qh holds the data toggle
976 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
978 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
980 struct ehci_qh
*qh
, *tmp
;
982 /* ASSERT: any requests/urbs are being unlinked */
983 /* ASSERT: nobody can be submitting urbs for this any more */
986 spin_lock_irqsave (&ehci
->lock
, flags
);
991 /* endpoints can be iso streams. for now, we don't
992 * accelerate iso completions ... so spin a while.
994 if (qh
->hw
== NULL
) {
995 ehci_vdbg (ehci
, "iso delay\n");
999 if (!HC_IS_RUNNING (hcd
->state
))
1000 qh
->qh_state
= QH_STATE_IDLE
;
1001 switch (qh
->qh_state
) {
1002 case QH_STATE_LINKED
:
1003 case QH_STATE_COMPLETING
:
1004 for (tmp
= ehci
->async
->qh_next
.qh
;
1006 tmp
= tmp
->qh_next
.qh
)
1008 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1009 * may already be unlinked.
1012 unlink_async(ehci
, qh
);
1014 case QH_STATE_UNLINK
: /* wait for hw to finish? */
1015 case QH_STATE_UNLINK_WAIT
:
1017 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1018 schedule_timeout_uninterruptible(1);
1020 case QH_STATE_IDLE
: /* fully unlinked */
1021 if (list_empty (&qh
->qtd_list
)) {
1025 /* else FALL THROUGH */
1027 /* caller was supposed to have unlinked any requests;
1028 * that's not our job. just leak this memory.
1030 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
1031 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
1032 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
1037 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1041 static int ehci_get_frame (struct usb_hcd
*hcd
)
1043 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
1044 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
1045 ehci
->periodic_size
;
1048 /*-------------------------------------------------------------------------*/
1050 MODULE_DESCRIPTION(DRIVER_DESC
);
1051 MODULE_AUTHOR (DRIVER_AUTHOR
);
1052 MODULE_LICENSE ("GPL");
1055 #include "ehci-pci.c"
1056 #define PCI_DRIVER ehci_pci_driver
1059 #ifdef CONFIG_USB_EHCI_FSL
1060 #include "ehci-fsl.c"
1061 #define PLATFORM_DRIVER ehci_fsl_driver
1064 #ifdef CONFIG_SOC_AU1200
1065 #include "ehci-au1xxx.c"
1066 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1069 #ifdef CONFIG_PPC_PS3
1070 #include "ehci-ps3.c"
1071 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1074 #ifdef CONFIG_440EPX
1075 #include "ehci-ppc-soc.c"
1076 #define PLATFORM_DRIVER ehci_ppc_soc_driver
1079 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1080 !defined(PS3_SYSTEM_BUS_DRIVER)
1081 #error "missing bus glue for ehci-hcd"
1084 static int __init
ehci_hcd_init(void)
1091 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1092 set_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1093 if (test_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
) ||
1094 test_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
))
1095 printk(KERN_WARNING
"Warning! ehci_hcd should always be loaded"
1096 " before uhci_hcd and ohci_hcd, not after\n");
1098 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1100 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
1101 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
1104 ehci_debug_root
= debugfs_create_dir("ehci", NULL
);
1105 if (!ehci_debug_root
) {
1111 #ifdef PLATFORM_DRIVER
1112 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1118 retval
= pci_register_driver(&PCI_DRIVER
);
1123 #ifdef PS3_SYSTEM_BUS_DRIVER
1124 retval
= ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1131 #ifdef PS3_SYSTEM_BUS_DRIVER
1132 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1136 pci_unregister_driver(&PCI_DRIVER
);
1139 #ifdef PLATFORM_DRIVER
1140 platform_driver_unregister(&PLATFORM_DRIVER
);
1144 debugfs_remove(ehci_debug_root
);
1145 ehci_debug_root
= NULL
;
1148 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1151 module_init(ehci_hcd_init
);
1153 static void __exit
ehci_hcd_cleanup(void)
1155 #ifdef PLATFORM_DRIVER
1156 platform_driver_unregister(&PLATFORM_DRIVER
);
1159 pci_unregister_driver(&PCI_DRIVER
);
1161 #ifdef PS3_SYSTEM_BUS_DRIVER
1162 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1165 debugfs_remove(ehci_debug_root
);
1167 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1169 module_exit(ehci_hcd_cleanup
);