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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / usb / gadget / fsl_usb2_udc.c
blobd57bcfbc08a530b31cdb5e6c75871057c6a794ae
1 /*
2 * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Li Yang <leoli@freescale.com>
5 * Jiang Bo <tanya.jiang@freescale.com>
6 *
7 * Description:
8 * Freescale high-speed USB SOC DR module device controller driver.
9 * This can be found on MPC8349E/MPC8313E cpus.
10 * The driver is previously named as mpc_udc. Based on bare board
11 * code from Dave Liu and Shlomi Gridish.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #undef VERBOSE
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/ioport.h>
24 #include <linux/types.h>
25 #include <linux/errno.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/proc_fs.h>
34 #include <linux/mm.h>
35 #include <linux/moduleparam.h>
36 #include <linux/device.h>
37 #include <linux/usb/ch9.h>
38 #include <linux/usb_gadget.h>
39 #include <linux/usb/otg.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/platform_device.h>
42 #include <linux/fsl_devices.h>
43 #include <linux/dmapool.h>
44
45 #include <asm/byteorder.h>
46 #include <asm/io.h>
47 #include <asm/irq.h>
48 #include <asm/system.h>
49 #include <asm/unaligned.h>
50 #include <asm/dma.h>
51 #include <asm/cacheflush.h>
52
53 #include "fsl_usb2_udc.h"
54
55 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
56 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
57 #define DRIVER_VERSION "Apr 20, 2007"
58
59 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
60
61 static const char driver_name[] = "fsl-usb2-udc";
62 static const char driver_desc[] = DRIVER_DESC;
63
64 volatile static struct usb_dr_device *dr_regs = NULL;
65 volatile static struct usb_sys_interface *usb_sys_regs = NULL;
66
67 /* it is initialized in probe() */
68 static struct fsl_udc *udc_controller = NULL;
69
70 static const struct usb_endpoint_descriptor
71 fsl_ep0_desc = {
72 .bLength = USB_DT_ENDPOINT_SIZE,
73 .bDescriptorType = USB_DT_ENDPOINT,
74 .bEndpointAddress = 0,
75 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
76 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
77 };
78
79 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state);
80 static int fsl_udc_resume(struct platform_device *pdev);
81 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
82
83 #ifdef CONFIG_PPC32
84 #define fsl_readl(addr) in_le32(addr)
85 #define fsl_writel(addr, val32) out_le32(val32, addr)
86 #else
87 #define fsl_readl(addr) readl(addr)
88 #define fsl_writel(addr, val32) writel(addr, val32)
89 #endif
90
91 /********************************************************************
92 * Internal Used Function
93 ********************************************************************/
94 /*-----------------------------------------------------------------
95 * done() - retire a request; caller blocked irqs
96 * @status : request status to be set, only works when
97 * request is still in progress.
98 *--------------------------------------------------------------*/
99 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
100 {
101 struct fsl_udc *udc = NULL;
102 unsigned char stopped = ep->stopped;
103 struct ep_td_struct *curr_td, *next_td;
104 int j;
105
106 udc = (struct fsl_udc *)ep->udc;
107 /* Removed the req from fsl_ep->queue */
108 list_del_init(&req->queue);
109
110 /* req.status should be set as -EINPROGRESS in ep_queue() */
111 if (req->req.status == -EINPROGRESS)
112 req->req.status = status;
113 else
114 status = req->req.status;
115
116 /* Free dtd for the request */
117 next_td = req->head;
118 for (j = 0; j < req->dtd_count; j++) {
119 curr_td = next_td;
120 if (j != req->dtd_count - 1) {
121 next_td = curr_td->next_td_virt;
122 }
123 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
124 }
125
126 if (req->mapped) {
127 dma_unmap_single(ep->udc->gadget.dev.parent,
128 req->req.dma, req->req.length,
129 ep_is_in(ep)
130 ? DMA_TO_DEVICE
131 : DMA_FROM_DEVICE);
132 req->req.dma = DMA_ADDR_INVALID;
133 req->mapped = 0;
134 } else
135 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
136 req->req.dma, req->req.length,
137 ep_is_in(ep)
138 ? DMA_TO_DEVICE
139 : DMA_FROM_DEVICE);
140
141 if (status && (status != -ESHUTDOWN))
142 VDBG("complete %s req %p stat %d len %u/%u",
143 ep->ep.name, &req->req, status,
144 req->req.actual, req->req.length);
145
146 ep->stopped = 1;
147
148 spin_unlock(&ep->udc->lock);
149 /* complete() is from gadget layer,
150 * eg fsg->bulk_in_complete() */
151 if (req->req.complete)
152 req->req.complete(&ep->ep, &req->req);
153
154 spin_lock(&ep->udc->lock);
155 ep->stopped = stopped;
156 }
157
158 /*-----------------------------------------------------------------
159 * nuke(): delete all requests related to this ep
160 * called with spinlock held
161 *--------------------------------------------------------------*/
162 static void nuke(struct fsl_ep *ep, int status)
163 {
164 ep->stopped = 1;
165
166 /* Flush fifo */
167 fsl_ep_fifo_flush(&ep->ep);
168
169 /* Whether this eq has request linked */
170 while (!list_empty(&ep->queue)) {
171 struct fsl_req *req = NULL;
172
173 req = list_entry(ep->queue.next, struct fsl_req, queue);
174 done(ep, req, status);
175 }
176 }
177
178 /*------------------------------------------------------------------
179 Internal Hardware related function
180 ------------------------------------------------------------------*/
181
182 static int dr_controller_setup(struct fsl_udc *udc)
183 {
184 unsigned int tmp = 0, portctrl = 0, ctrl = 0;
185 unsigned long timeout;
186 #define FSL_UDC_RESET_TIMEOUT 1000
187
188 /* before here, make sure dr_regs has been initialized */
189 if (!udc)
190 return -EINVAL;
191
192 /* Stop and reset the usb controller */
193 tmp = fsl_readl(&dr_regs->usbcmd);
194 tmp &= ~USB_CMD_RUN_STOP;
195 fsl_writel(tmp, &dr_regs->usbcmd);
196
197 tmp = fsl_readl(&dr_regs->usbcmd);
198 tmp |= USB_CMD_CTRL_RESET;
199 fsl_writel(tmp, &dr_regs->usbcmd);
200
201 /* Wait for reset to complete */
202 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
203 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
204 if (time_after(jiffies, timeout)) {
205 ERR("udc reset timeout! \n");
206 return -ETIMEDOUT;
207 }
208 cpu_relax();
209 }
210
211 /* Set the controller as device mode */
212 tmp = fsl_readl(&dr_regs->usbmode);
213 tmp |= USB_MODE_CTRL_MODE_DEVICE;
214 /* Disable Setup Lockout */
215 tmp |= USB_MODE_SETUP_LOCK_OFF;
216 fsl_writel(tmp, &dr_regs->usbmode);
217
218 /* Clear the setup status */
219 fsl_writel(0, &dr_regs->usbsts);
220
221 tmp = udc->ep_qh_dma;
222 tmp &= USB_EP_LIST_ADDRESS_MASK;
223 fsl_writel(tmp, &dr_regs->endpointlistaddr);
224
225 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
226 (int)udc->ep_qh, (int)tmp,
227 fsl_readl(&dr_regs->endpointlistaddr));
228
229 /* Config PHY interface */
230 portctrl = fsl_readl(&dr_regs->portsc1);
231 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
232 switch (udc->phy_mode) {
233 case FSL_USB2_PHY_ULPI:
234 portctrl |= PORTSCX_PTS_ULPI;
235 break;
236 case FSL_USB2_PHY_UTMI_WIDE:
237 portctrl |= PORTSCX_PTW_16BIT;
238 /* fall through */
239 case FSL_USB2_PHY_UTMI:
240 portctrl |= PORTSCX_PTS_UTMI;
241 break;
242 case FSL_USB2_PHY_SERIAL:
243 portctrl |= PORTSCX_PTS_FSLS;
244 break;
245 default:
246 return -EINVAL;
247 }
248 fsl_writel(portctrl, &dr_regs->portsc1);
249
250 /* Config control enable i/o output, cpu endian register */
251 ctrl = __raw_readl(&usb_sys_regs->control);
252 ctrl |= USB_CTRL_IOENB;
253 __raw_writel(ctrl, &usb_sys_regs->control);
254
255 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
256 /* Turn on cache snooping hardware, since some PowerPC platforms
257 * wholly rely on hardware to deal with cache coherent. */
258
259 /* Setup Snooping for all the 4GB space */
260 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
261 __raw_writel(tmp, &usb_sys_regs->snoop1);
262 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
263 __raw_writel(tmp, &usb_sys_regs->snoop2);
264 #endif
265
266 return 0;
267 }
268
269 /* Enable DR irq and set controller to run state */
270 static void dr_controller_run(struct fsl_udc *udc)
271 {
272 u32 temp;
273
274 /* Enable DR irq reg */
275 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
276 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
277 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
278
279 fsl_writel(temp, &dr_regs->usbintr);
280
281 /* Clear stopped bit */
282 udc->stopped = 0;
283
284 /* Set the controller as device mode */
285 temp = fsl_readl(&dr_regs->usbmode);
286 temp |= USB_MODE_CTRL_MODE_DEVICE;
287 fsl_writel(temp, &dr_regs->usbmode);
288
289 /* Set controller to Run */
290 temp = fsl_readl(&dr_regs->usbcmd);
291 temp |= USB_CMD_RUN_STOP;
292 fsl_writel(temp, &dr_regs->usbcmd);
293
294 return;
295 }
296
297 static void dr_controller_stop(struct fsl_udc *udc)
298 {
299 unsigned int tmp;
300
301 /* disable all INTR */
302 fsl_writel(0, &dr_regs->usbintr);
303
304 /* Set stopped bit for isr */
305 udc->stopped = 1;
306
307 /* disable IO output */
308 /* usb_sys_regs->control = 0; */
309
310 /* set controller to Stop */
311 tmp = fsl_readl(&dr_regs->usbcmd);
312 tmp &= ~USB_CMD_RUN_STOP;
313 fsl_writel(tmp, &dr_regs->usbcmd);
314
315 return;
316 }
317
318 void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
319 {
320 unsigned int tmp_epctrl = 0;
321
322 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
323 if (dir) {
324 if (ep_num)
325 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
326 tmp_epctrl |= EPCTRL_TX_ENABLE;
327 tmp_epctrl |= ((unsigned int)(ep_type)
328 << EPCTRL_TX_EP_TYPE_SHIFT);
329 } else {
330 if (ep_num)
331 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
332 tmp_epctrl |= EPCTRL_RX_ENABLE;
333 tmp_epctrl |= ((unsigned int)(ep_type)
334 << EPCTRL_RX_EP_TYPE_SHIFT);
335 }
336
337 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
338 }
339
340 static void
341 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
342 {
343 u32 tmp_epctrl = 0;
344
345 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
346
347 if (value) {
348 /* set the stall bit */
349 if (dir)
350 tmp_epctrl |= EPCTRL_TX_EP_STALL;
351 else
352 tmp_epctrl |= EPCTRL_RX_EP_STALL;
353 } else {
354 /* clear the stall bit and reset data toggle */
355 if (dir) {
356 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
357 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
358 } else {
359 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
360 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
361 }
362 }
363 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
364 }
365
366 /* Get stall status of a specific ep
367 Return: 0: not stalled; 1:stalled */
368 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
369 {
370 u32 epctrl;
371
372 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
373 if (dir)
374 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
375 else
376 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
377 }
378
379 /********************************************************************
380 Internal Structure Build up functions
381 ********************************************************************/
382
383 /*------------------------------------------------------------------
384 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
385 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
386 * @mult: Mult field
387 ------------------------------------------------------------------*/
388 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
389 unsigned char dir, unsigned char ep_type,
390 unsigned int max_pkt_len,
391 unsigned int zlt, unsigned char mult)
392 {
393 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
394 unsigned int tmp = 0;
395
396 /* set the Endpoint Capabilites in QH */
397 switch (ep_type) {
398 case USB_ENDPOINT_XFER_CONTROL:
399 /* Interrupt On Setup (IOS). for control ep */
400 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
401 | EP_QUEUE_HEAD_IOS;
402 break;
403 case USB_ENDPOINT_XFER_ISOC:
404 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
405 | (mult << EP_QUEUE_HEAD_MULT_POS);
406 break;
407 case USB_ENDPOINT_XFER_BULK:
408 case USB_ENDPOINT_XFER_INT:
409 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
410 break;
411 default:
412 VDBG("error ep type is %d", ep_type);
413 return;
414 }
415 if (zlt)
416 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
417 p_QH->max_pkt_length = cpu_to_le32(tmp);
418
419 return;
420 }
421
422 /* Setup qh structure and ep register for ep0. */
423 static void ep0_setup(struct fsl_udc *udc)
424 {
425 /* the intialization of an ep includes: fields in QH, Regs,
426 * fsl_ep struct */
427 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
428 USB_MAX_CTRL_PAYLOAD, 0, 0);
429 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
430 USB_MAX_CTRL_PAYLOAD, 0, 0);
431 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
432 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
433
434 return;
435
436 }
437
438 /***********************************************************************
439 Endpoint Management Functions
440 ***********************************************************************/
441
442 /*-------------------------------------------------------------------------
443 * when configurations are set, or when interface settings change
444 * for example the do_set_interface() in gadget layer,
445 * the driver will enable or disable the relevant endpoints
446 * ep0 doesn't use this routine. It is always enabled.
447 -------------------------------------------------------------------------*/
448 static int fsl_ep_enable(struct usb_ep *_ep,
449 const struct usb_endpoint_descriptor *desc)
450 {
451 struct fsl_udc *udc = NULL;
452 struct fsl_ep *ep = NULL;
453 unsigned short max = 0;
454 unsigned char mult = 0, zlt;
455 int retval = -EINVAL;
456 unsigned long flags = 0;
457
458 ep = container_of(_ep, struct fsl_ep, ep);
459
460 /* catch various bogus parameters */
461 if (!_ep || !desc || ep->desc
462 || (desc->bDescriptorType != USB_DT_ENDPOINT))
463 return -EINVAL;
464
465 udc = ep->udc;
466
467 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
468 return -ESHUTDOWN;
469
470 max = le16_to_cpu(desc->wMaxPacketSize);
471
472 /* Disable automatic zlp generation. Driver is reponsible to indicate
473 * explicitly through req->req.zero. This is needed to enable multi-td
474 * request. */
475 zlt = 1;
476
477 /* Assume the max packet size from gadget is always correct */
478 switch (desc->bmAttributes & 0x03) {
479 case USB_ENDPOINT_XFER_CONTROL:
480 case USB_ENDPOINT_XFER_BULK:
481 case USB_ENDPOINT_XFER_INT:
482 /* mult = 0. Execute N Transactions as demonstrated by
483 * the USB variable length packet protocol where N is
484 * computed using the Maximum Packet Length (dQH) and
485 * the Total Bytes field (dTD) */
486 mult = 0;
487 break;
488 case USB_ENDPOINT_XFER_ISOC:
489 /* Calculate transactions needed for high bandwidth iso */
490 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
491 max = max & 0x8ff; /* bit 0~10 */
492 /* 3 transactions at most */
493 if (mult > 3)
494 goto en_done;
495 break;
496 default:
497 goto en_done;
498 }
499
500 spin_lock_irqsave(&udc->lock, flags);
501 ep->ep.maxpacket = max;
502 ep->desc = desc;
503 ep->stopped = 0;
504
505 /* Controller related setup */
506 /* Init EPx Queue Head (Ep Capabilites field in QH
507 * according to max, zlt, mult) */
508 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
509 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
510 ? USB_SEND : USB_RECV),
511 (unsigned char) (desc->bmAttributes
512 & USB_ENDPOINT_XFERTYPE_MASK),
513 max, zlt, mult);
514
515 /* Init endpoint ctrl register */
516 dr_ep_setup((unsigned char) ep_index(ep),
517 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
518 ? USB_SEND : USB_RECV),
519 (unsigned char) (desc->bmAttributes
520 & USB_ENDPOINT_XFERTYPE_MASK));
521
522 spin_unlock_irqrestore(&udc->lock, flags);
523 retval = 0;
524
525 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
526 ep->desc->bEndpointAddress & 0x0f,
527 (desc->bEndpointAddress & USB_DIR_IN)
528 ? "in" : "out", max);
529 en_done:
530 return retval;
531 }
532
533 /*---------------------------------------------------------------------
534 * @ep : the ep being unconfigured. May not be ep0
535 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
536 *---------------------------------------------------------------------*/
537 static int fsl_ep_disable(struct usb_ep *_ep)
538 {
539 struct fsl_udc *udc = NULL;
540 struct fsl_ep *ep = NULL;
541 unsigned long flags = 0;
542 u32 epctrl;
543 int ep_num;
544
545 ep = container_of(_ep, struct fsl_ep, ep);
546 if (!_ep || !ep->desc) {
547 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
548 return -EINVAL;
549 }
550
551 /* disable ep on controller */
552 ep_num = ep_index(ep);
553 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
554 if (ep_is_in(ep))
555 epctrl &= ~EPCTRL_TX_ENABLE;
556 else
557 epctrl &= ~EPCTRL_RX_ENABLE;
558 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
559
560 udc = (struct fsl_udc *)ep->udc;
561 spin_lock_irqsave(&udc->lock, flags);
562
563 /* nuke all pending requests (does flush) */
564 nuke(ep, -ESHUTDOWN);
565
566 ep->desc = 0;
567 ep->stopped = 1;
568 spin_unlock_irqrestore(&udc->lock, flags);
569
570 VDBG("disabled %s OK", _ep->name);
571 return 0;
572 }
573
574 /*---------------------------------------------------------------------
575 * allocate a request object used by this endpoint
576 * the main operation is to insert the req->queue to the eq->queue
577 * Returns the request, or null if one could not be allocated
578 *---------------------------------------------------------------------*/
579 static struct usb_request *
580 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
581 {
582 struct fsl_req *req = NULL;
583
584 req = kzalloc(sizeof *req, gfp_flags);
585 if (!req)
586 return NULL;
587
588 req->req.dma = DMA_ADDR_INVALID;
589 INIT_LIST_HEAD(&req->queue);
590
591 return &req->req;
592 }
593
594 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
595 {
596 struct fsl_req *req = NULL;
597
598 req = container_of(_req, struct fsl_req, req);
599
600 if (_req)
601 kfree(req);
602 }
603
604 /*-------------------------------------------------------------------------*/
605 static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
606 {
607 int i = ep_index(ep) * 2 + ep_is_in(ep);
608 u32 temp, bitmask, tmp_stat;
609 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
610
611 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
612 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
613
614 bitmask = ep_is_in(ep)
615 ? (1 << (ep_index(ep) + 16))
616 : (1 << (ep_index(ep)));
617
618 /* check if the pipe is empty */
619 if (!(list_empty(&ep->queue))) {
620 /* Add td to the end */
621 struct fsl_req *lastreq;
622 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
623 lastreq->tail->next_td_ptr =
624 cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
625 /* Read prime bit, if 1 goto done */
626 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
627 goto out;
628
629 do {
630 /* Set ATDTW bit in USBCMD */
631 temp = fsl_readl(&dr_regs->usbcmd);
632 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
633
634 /* Read correct status bit */
635 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
636
637 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
638
639 /* Write ATDTW bit to 0 */
640 temp = fsl_readl(&dr_regs->usbcmd);
641 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
642
643 if (tmp_stat)
644 goto out;
645 }
646
647 /* Write dQH next pointer and terminate bit to 0 */
648 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
649 dQH->next_dtd_ptr = cpu_to_le32(temp);
650
651 /* Clear active and halt bit */
652 temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
653 | EP_QUEUE_HEAD_STATUS_HALT));
654 dQH->size_ioc_int_sts &= temp;
655
656 /* Prime endpoint by writing 1 to ENDPTPRIME */
657 temp = ep_is_in(ep)
658 ? (1 << (ep_index(ep) + 16))
659 : (1 << (ep_index(ep)));
660 fsl_writel(temp, &dr_regs->endpointprime);
661 out:
662 return 0;
663 }
664
665 /* Fill in the dTD structure
666 * @req: request that the transfer belongs to
667 * @length: return actually data length of the dTD
668 * @dma: return dma address of the dTD
669 * @is_last: return flag if it is the last dTD of the request
670 * return: pointer to the built dTD */
671 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
672 dma_addr_t *dma, int *is_last)
673 {
674 u32 swap_temp;
675 struct ep_td_struct *dtd;
676
677 /* how big will this transfer be? */
678 *length = min(req->req.length - req->req.actual,
679 (unsigned)EP_MAX_LENGTH_TRANSFER);
680
681 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
682 if (dtd == NULL)
683 return dtd;
684
685 dtd->td_dma = *dma;
686 /* Clear reserved field */
687 swap_temp = cpu_to_le32(dtd->size_ioc_sts);
688 swap_temp &= ~DTD_RESERVED_FIELDS;
689 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
690
691 /* Init all of buffer page pointers */
692 swap_temp = (u32) (req->req.dma + req->req.actual);
693 dtd->buff_ptr0 = cpu_to_le32(swap_temp);
694 dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
695 dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
696 dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
697 dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
698
699 req->req.actual += *length;
700
701 /* zlp is needed if req->req.zero is set */
702 if (req->req.zero) {
703 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
704 *is_last = 1;
705 else
706 *is_last = 0;
707 } else if (req->req.length == req->req.actual)
708 *is_last = 1;
709 else
710 *is_last = 0;
711
712 if ((*is_last) == 0)
713 VDBG("multi-dtd request!\n");
714 /* Fill in the transfer size; set active bit */
715 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
716
717 /* Enable interrupt for the last dtd of a request */
718 if (*is_last && !req->req.no_interrupt)
719 swap_temp |= DTD_IOC;
720
721 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
722
723 mb();
724
725 VDBG("length = %d address= 0x%x", *length, (int)*dma);
726
727 return dtd;
728 }
729
730 /* Generate dtd chain for a request */
731 static int fsl_req_to_dtd(struct fsl_req *req)
732 {
733 unsigned count;
734 int is_last;
735 int is_first =1;
736 struct ep_td_struct *last_dtd = NULL, *dtd;
737 dma_addr_t dma;
738
739 do {
740 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
741 if (dtd == NULL)
742 return -ENOMEM;
743
744 if (is_first) {
745 is_first = 0;
746 req->head = dtd;
747 } else {
748 last_dtd->next_td_ptr = cpu_to_le32(dma);
749 last_dtd->next_td_virt = dtd;
750 }
751 last_dtd = dtd;
752
753 req->dtd_count++;
754 } while (!is_last);
755
756 dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
757
758 req->tail = dtd;
759
760 return 0;
761 }
762
763 /* queues (submits) an I/O request to an endpoint */
764 static int
765 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
766 {
767 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
768 struct fsl_req *req = container_of(_req, struct fsl_req, req);
769 struct fsl_udc *udc;
770 unsigned long flags;
771 int is_iso = 0;
772
773 /* catch various bogus parameters */
774 if (!_req || !req->req.complete || !req->req.buf
775 || !list_empty(&req->queue)) {
776 VDBG("%s, bad params\n", __FUNCTION__);
777 return -EINVAL;
778 }
779 if (!_ep || (!ep->desc && ep_index(ep))) {
780 VDBG("%s, bad ep\n", __FUNCTION__);
781 return -EINVAL;
782 }
783 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
784 if (req->req.length > ep->ep.maxpacket)
785 return -EMSGSIZE;
786 is_iso = 1;
787 }
788
789 udc = ep->udc;
790 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
791 return -ESHUTDOWN;
792
793 req->ep = ep;
794
795 /* map virtual address to hardware */
796 if (req->req.dma == DMA_ADDR_INVALID) {
797 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
798 req->req.buf,
799 req->req.length, ep_is_in(ep)
800 ? DMA_TO_DEVICE
801 : DMA_FROM_DEVICE);
802 req->mapped = 1;
803 } else {
804 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
805 req->req.dma, req->req.length,
806 ep_is_in(ep)
807 ? DMA_TO_DEVICE
808 : DMA_FROM_DEVICE);
809 req->mapped = 0;
810 }
811
812 req->req.status = -EINPROGRESS;
813 req->req.actual = 0;
814 req->dtd_count = 0;
815
816 spin_lock_irqsave(&udc->lock, flags);
817
818 /* build dtds and push them to device queue */
819 if (!fsl_req_to_dtd(req)) {
820 fsl_queue_td(ep, req);
821 } else {
822 spin_unlock_irqrestore(&udc->lock, flags);
823 return -ENOMEM;
824 }
825
826 /* Update ep0 state */
827 if ((ep_index(ep) == 0))
828 udc->ep0_state = DATA_STATE_XMIT;
829
830 /* irq handler advances the queue */
831 if (req != NULL)
832 list_add_tail(&req->queue, &ep->queue);
833 spin_unlock_irqrestore(&udc->lock, flags);
834
835 return 0;
836 }
837
838 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
839 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
840 {
841 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
842 struct fsl_req *req;
843 unsigned long flags;
844 int ep_num, stopped, ret = 0;
845 u32 epctrl;
846
847 if (!_ep || !_req)
848 return -EINVAL;
849
850 spin_lock_irqsave(&ep->udc->lock, flags);
851 stopped = ep->stopped;
852
853 /* Stop the ep before we deal with the queue */
854 ep->stopped = 1;
855 ep_num = ep_index(ep);
856 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
857 if (ep_is_in(ep))
858 epctrl &= ~EPCTRL_TX_ENABLE;
859 else
860 epctrl &= ~EPCTRL_RX_ENABLE;
861 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
862
863 /* make sure it's actually queued on this endpoint */
864 list_for_each_entry(req, &ep->queue, queue) {
865 if (&req->req == _req)
866 break;
867 }
868 if (&req->req != _req) {
869 ret = -EINVAL;
870 goto out;
871 }
872
873 /* The request is in progress, or completed but not dequeued */
874 if (ep->queue.next == &req->queue) {
875 _req->status = -ECONNRESET;
876 fsl_ep_fifo_flush(_ep); /* flush current transfer */
877
878 /* The request isn't the last request in this ep queue */
879 if (req->queue.next != &ep->queue) {
880 struct ep_queue_head *qh;
881 struct fsl_req *next_req;
882
883 qh = ep->qh;
884 next_req = list_entry(req->queue.next, struct fsl_req,
885 queue);
886
887 /* Point the QH to the first TD of next request */
888 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
889 }
890
891 /* The request hasn't been processed, patch up the TD chain */
892 } else {
893 struct fsl_req *prev_req;
894
895 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
896 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
897 &prev_req->tail->next_td_ptr);
898
899 }
900
901 done(ep, req, -ECONNRESET);
902
903 /* Enable EP */
904 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
905 if (ep_is_in(ep))
906 epctrl |= EPCTRL_TX_ENABLE;
907 else
908 epctrl |= EPCTRL_RX_ENABLE;
909 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
910 ep->stopped = stopped;
911
912 spin_unlock_irqrestore(&ep->udc->lock, flags);
913 return ret;
914 }
915
916 /*-------------------------------------------------------------------------*/
917
918 /*-----------------------------------------------------------------
919 * modify the endpoint halt feature
920 * @ep: the non-isochronous endpoint being stalled
921 * @value: 1--set halt 0--clear halt
922 * Returns zero, or a negative error code.
923 *----------------------------------------------------------------*/
924 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
925 {
926 struct fsl_ep *ep = NULL;
927 unsigned long flags = 0;
928 int status = -EOPNOTSUPP; /* operation not supported */
929 unsigned char ep_dir = 0, ep_num = 0;
930 struct fsl_udc *udc = NULL;
931
932 ep = container_of(_ep, struct fsl_ep, ep);
933 udc = ep->udc;
934 if (!_ep || !ep->desc) {
935 status = -EINVAL;
936 goto out;
937 }
938
939 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
940 status = -EOPNOTSUPP;
941 goto out;
942 }
943
944 /* Attempt to halt IN ep will fail if any transfer requests
945 * are still queue */
946 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
947 status = -EAGAIN;
948 goto out;
949 }
950
951 status = 0;
952 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
953 ep_num = (unsigned char)(ep_index(ep));
954 spin_lock_irqsave(&ep->udc->lock, flags);
955 dr_ep_change_stall(ep_num, ep_dir, value);
956 spin_unlock_irqrestore(&ep->udc->lock, flags);
957
958 if (ep_index(ep) == 0) {
959 udc->ep0_state = WAIT_FOR_SETUP;
960 udc->ep0_dir = 0;
961 }
962 out:
963 VDBG(" %s %s halt stat %d", ep->ep.name,
964 value ? "set" : "clear", status);
965
966 return status;
967 }
968
969 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
970 {
971 struct fsl_ep *ep;
972 int ep_num, ep_dir;
973 u32 bits;
974 unsigned long timeout;
975 #define FSL_UDC_FLUSH_TIMEOUT 1000
976
977 if (!_ep) {
978 return;
979 } else {
980 ep = container_of(_ep, struct fsl_ep, ep);
981 if (!ep->desc)
982 return;
983 }
984 ep_num = ep_index(ep);
985 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
986
987 if (ep_num == 0)
988 bits = (1 << 16) | 1;
989 else if (ep_dir == USB_SEND)
990 bits = 1 << (16 + ep_num);
991 else
992 bits = 1 << ep_num;
993
994 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
995 do {
996 fsl_writel(bits, &dr_regs->endptflush);
997
998 /* Wait until flush complete */
999 while (fsl_readl(&dr_regs->endptflush)) {
1000 if (time_after(jiffies, timeout)) {
1001 ERR("ep flush timeout\n");
1002 return;
1003 }
1004 cpu_relax();
1005 }
1006 /* See if we need to flush again */
1007 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1008 }
1009
1010 static struct usb_ep_ops fsl_ep_ops = {
1011 .enable = fsl_ep_enable,
1012 .disable = fsl_ep_disable,
1013
1014 .alloc_request = fsl_alloc_request,
1015 .free_request = fsl_free_request,
1016
1017 .queue = fsl_ep_queue,
1018 .dequeue = fsl_ep_dequeue,
1019
1020 .set_halt = fsl_ep_set_halt,
1021 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1022 };
1023
1024 /*-------------------------------------------------------------------------
1025 Gadget Driver Layer Operations
1026 -------------------------------------------------------------------------*/
1027
1028 /*----------------------------------------------------------------------
1029 * Get the current frame number (from DR frame_index Reg )
1030 *----------------------------------------------------------------------*/
1031 static int fsl_get_frame(struct usb_gadget *gadget)
1032 {
1033 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1034 }
1035
1036 /*-----------------------------------------------------------------------
1037 * Tries to wake up the host connected to this gadget
1038 -----------------------------------------------------------------------*/
1039 static int fsl_wakeup(struct usb_gadget *gadget)
1040 {
1041 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1042 u32 portsc;
1043
1044 /* Remote wakeup feature not enabled by host */
1045 if (!udc->remote_wakeup)
1046 return -ENOTSUPP;
1047
1048 portsc = fsl_readl(&dr_regs->portsc1);
1049 /* not suspended? */
1050 if (!(portsc & PORTSCX_PORT_SUSPEND))
1051 return 0;
1052 /* trigger force resume */
1053 portsc |= PORTSCX_PORT_FORCE_RESUME;
1054 fsl_writel(portsc, &dr_regs->portsc1);
1055 return 0;
1056 }
1057
1058 static int can_pullup(struct fsl_udc *udc)
1059 {
1060 return udc->driver && udc->softconnect && udc->vbus_active;
1061 }
1062
1063 /* Notify controller that VBUS is powered, Called by whatever
1064 detects VBUS sessions */
1065 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1066 {
1067 struct fsl_udc *udc;
1068 unsigned long flags;
1069
1070 udc = container_of(gadget, struct fsl_udc, gadget);
1071 spin_lock_irqsave(&udc->lock, flags);
1072 VDBG("VBUS %s\n", is_active ? "on" : "off");
1073 udc->vbus_active = (is_active != 0);
1074 if (can_pullup(udc))
1075 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1076 &dr_regs->usbcmd);
1077 else
1078 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1079 &dr_regs->usbcmd);
1080 spin_unlock_irqrestore(&udc->lock, flags);
1081 return 0;
1082 }
1083
1084 /* constrain controller's VBUS power usage
1085 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1086 * reporting how much power the device may consume. For example, this
1087 * could affect how quickly batteries are recharged.
1088 *
1089 * Returns zero on success, else negative errno.
1090 */
1091 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1092 {
1093 #ifdef CONFIG_USB_OTG
1094 struct fsl_udc *udc;
1095
1096 udc = container_of(gadget, struct fsl_udc, gadget);
1097
1098 if (udc->transceiver)
1099 return otg_set_power(udc->transceiver, mA);
1100 #endif
1101 return -ENOTSUPP;
1102 }
1103
1104 /* Change Data+ pullup status
1105 * this func is used by usb_gadget_connect/disconnet
1106 */
1107 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1108 {
1109 struct fsl_udc *udc;
1110
1111 udc = container_of(gadget, struct fsl_udc, gadget);
1112 udc->softconnect = (is_on != 0);
1113 if (can_pullup(udc))
1114 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1115 &dr_regs->usbcmd);
1116 else
1117 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1118 &dr_regs->usbcmd);
1119
1120 return 0;
1121 }
1122
1123 /* defined in usb_gadget.h */
1124 static struct usb_gadget_ops fsl_gadget_ops = {
1125 .get_frame = fsl_get_frame,
1126 .wakeup = fsl_wakeup,
1127 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1128 .vbus_session = fsl_vbus_session,
1129 .vbus_draw = fsl_vbus_draw,
1130 .pullup = fsl_pullup,
1131 };
1132
1133 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1134 on new transaction */
1135 static void ep0stall(struct fsl_udc *udc)
1136 {
1137 u32 tmp;
1138
1139 /* must set tx and rx to stall at the same time */
1140 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1141 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1142 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1143 udc->ep0_state = WAIT_FOR_SETUP;
1144 udc->ep0_dir = 0;
1145 }
1146
1147 /* Prime a status phase for ep0 */
1148 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1149 {
1150 struct fsl_req *req = udc->status_req;
1151 struct fsl_ep *ep;
1152 int status = 0;
1153
1154 if (direction == EP_DIR_IN)
1155 udc->ep0_dir = USB_DIR_IN;
1156 else
1157 udc->ep0_dir = USB_DIR_OUT;
1158
1159 ep = &udc->eps[0];
1160 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1161
1162 req->ep = ep;
1163 req->req.length = 0;
1164 req->req.status = -EINPROGRESS;
1165 req->req.actual = 0;
1166 req->req.complete = NULL;
1167 req->dtd_count = 0;
1168
1169 if (fsl_req_to_dtd(req) == 0)
1170 status = fsl_queue_td(ep, req);
1171 else
1172 return -ENOMEM;
1173
1174 if (status)
1175 ERR("Can't queue ep0 status request \n");
1176 list_add_tail(&req->queue, &ep->queue);
1177
1178 return status;
1179 }
1180
1181 static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1182 {
1183 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1184
1185 if (!ep->name)
1186 return 0;
1187
1188 nuke(ep, -ESHUTDOWN);
1189
1190 return 0;
1191 }
1192
1193 /*
1194 * ch9 Set address
1195 */
1196 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1197 {
1198 /* Save the new address to device struct */
1199 udc->device_address = (u8) value;
1200 /* Update usb state */
1201 udc->usb_state = USB_STATE_ADDRESS;
1202 /* Status phase */
1203 if (ep0_prime_status(udc, EP_DIR_IN))
1204 ep0stall(udc);
1205 }
1206
1207 /*
1208 * ch9 Get status
1209 */
1210 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1211 u16 index, u16 length)
1212 {
1213 u16 tmp = 0; /* Status, cpu endian */
1214
1215 struct fsl_req *req;
1216 struct fsl_ep *ep;
1217 int status = 0;
1218
1219 ep = &udc->eps[0];
1220
1221 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1222 /* Get device status */
1223 tmp = 1 << USB_DEVICE_SELF_POWERED;
1224 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1225 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1226 /* Get interface status */
1227 /* We don't have interface information in udc driver */
1228 tmp = 0;
1229 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1230 /* Get endpoint status */
1231 struct fsl_ep *target_ep;
1232
1233 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1234
1235 /* stall if endpoint doesn't exist */
1236 if (!target_ep->desc)
1237 goto stall;
1238 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1239 << USB_ENDPOINT_HALT;
1240 }
1241
1242 udc->ep0_dir = USB_DIR_IN;
1243 /* Borrow the per device status_req */
1244 req = udc->status_req;
1245 /* Fill in the reqest structure */
1246 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1247 req->ep = ep;
1248 req->req.length = 2;
1249 req->req.status = -EINPROGRESS;
1250 req->req.actual = 0;
1251 req->req.complete = NULL;
1252 req->dtd_count = 0;
1253
1254 /* prime the data phase */
1255 if ((fsl_req_to_dtd(req) == 0))
1256 status = fsl_queue_td(ep, req);
1257 else /* no mem */
1258 goto stall;
1259
1260 if (status) {
1261 ERR("Can't respond to getstatus request \n");
1262 goto stall;
1263 }
1264 list_add_tail(&req->queue, &ep->queue);
1265 udc->ep0_state = DATA_STATE_XMIT;
1266 return;
1267 stall:
1268 ep0stall(udc);
1269 }
1270
1271 static void setup_received_irq(struct fsl_udc *udc,
1272 struct usb_ctrlrequest *setup)
1273 {
1274 u16 wValue = le16_to_cpu(setup->wValue);
1275 u16 wIndex = le16_to_cpu(setup->wIndex);
1276 u16 wLength = le16_to_cpu(setup->wLength);
1277
1278 udc_reset_ep_queue(udc, 0);
1279
1280 /* We process some stardard setup requests here */
1281 switch (setup->bRequest) {
1282 case USB_REQ_GET_STATUS:
1283 /* Data+Status phase from udc */
1284 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1285 != (USB_DIR_IN | USB_TYPE_STANDARD))
1286 break;
1287 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1288 return;
1289
1290 case USB_REQ_SET_ADDRESS:
1291 /* Status phase from udc */
1292 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1293 | USB_RECIP_DEVICE))
1294 break;
1295 ch9setaddress(udc, wValue, wIndex, wLength);
1296 return;
1297
1298 case USB_REQ_CLEAR_FEATURE:
1299 case USB_REQ_SET_FEATURE:
1300 /* Status phase from udc */
1301 {
1302 int rc = -EOPNOTSUPP;
1303
1304 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1305 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1306 int pipe = get_pipe_by_windex(wIndex);
1307 struct fsl_ep *ep;
1308
1309 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1310 break;
1311 ep = get_ep_by_pipe(udc, pipe);
1312
1313 spin_unlock(&udc->lock);
1314 rc = fsl_ep_set_halt(&ep->ep,
1315 (setup->bRequest == USB_REQ_SET_FEATURE)
1316 ? 1 : 0);
1317 spin_lock(&udc->lock);
1318
1319 } else if ((setup->bRequestType & (USB_RECIP_MASK
1320 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1321 | USB_TYPE_STANDARD)) {
1322 /* Note: The driver has not include OTG support yet.
1323 * This will be set when OTG support is added */
1324 if (!udc->gadget.is_otg)
1325 break;
1326 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
1327 udc->gadget.b_hnp_enable = 1;
1328 else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
1329 udc->gadget.a_hnp_support = 1;
1330 else if (setup->bRequest ==
1331 USB_DEVICE_A_ALT_HNP_SUPPORT)
1332 udc->gadget.a_alt_hnp_support = 1;
1333 rc = 0;
1334 } else
1335 break;
1336
1337 if (rc == 0) {
1338 if (ep0_prime_status(udc, EP_DIR_IN))
1339 ep0stall(udc);
1340 }
1341 return;
1342 }
1343
1344 default:
1345 break;
1346 }
1347
1348 /* Requests handled by gadget */
1349 if (wLength) {
1350 /* Data phase from gadget, status phase from udc */
1351 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1352 ? USB_DIR_IN : USB_DIR_OUT;
1353 spin_unlock(&udc->lock);
1354 if (udc->driver->setup(&udc->gadget,
1355 &udc->local_setup_buff) < 0)
1356 ep0stall(udc);
1357 spin_lock(&udc->lock);
1358 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1359 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1360 } else {
1361 /* No data phase, IN status from gadget */
1362 udc->ep0_dir = USB_DIR_IN;
1363 spin_unlock(&udc->lock);
1364 if (udc->driver->setup(&udc->gadget,
1365 &udc->local_setup_buff) < 0)
1366 ep0stall(udc);
1367 spin_lock(&udc->lock);
1368 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1369 }
1370 }
1371
1372 /* Process request for Data or Status phase of ep0
1373 * prime status phase if needed */
1374 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1375 struct fsl_req *req)
1376 {
1377 if (udc->usb_state == USB_STATE_ADDRESS) {
1378 /* Set the new address */
1379 u32 new_address = (u32) udc->device_address;
1380 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1381 &dr_regs->deviceaddr);
1382 }
1383
1384 done(ep0, req, 0);
1385
1386 switch (udc->ep0_state) {
1387 case DATA_STATE_XMIT:
1388 /* receive status phase */
1389 if (ep0_prime_status(udc, EP_DIR_OUT))
1390 ep0stall(udc);
1391 break;
1392 case DATA_STATE_RECV:
1393 /* send status phase */
1394 if (ep0_prime_status(udc, EP_DIR_IN))
1395 ep0stall(udc);
1396 break;
1397 case WAIT_FOR_OUT_STATUS:
1398 udc->ep0_state = WAIT_FOR_SETUP;
1399 break;
1400 case WAIT_FOR_SETUP:
1401 ERR("Unexpect ep0 packets \n");
1402 break;
1403 default:
1404 ep0stall(udc);
1405 break;
1406 }
1407 }
1408
1409 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1410 * being corrupted by another incoming setup packet */
1411 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1412 {
1413 u32 temp;
1414 struct ep_queue_head *qh;
1415
1416 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1417
1418 /* Clear bit in ENDPTSETUPSTAT */
1419 temp = fsl_readl(&dr_regs->endptsetupstat);
1420 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1421
1422 /* while a hazard exists when setup package arrives */
1423 do {
1424 /* Set Setup Tripwire */
1425 temp = fsl_readl(&dr_regs->usbcmd);
1426 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1427
1428 /* Copy the setup packet to local buffer */
1429 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1430 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1431
1432 /* Clear Setup Tripwire */
1433 temp = fsl_readl(&dr_regs->usbcmd);
1434 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1435 }
1436
1437 /* process-ep_req(): free the completed Tds for this req */
1438 static int process_ep_req(struct fsl_udc *udc, int pipe,
1439 struct fsl_req *curr_req)
1440 {
1441 struct ep_td_struct *curr_td;
1442 int td_complete, actual, remaining_length, j, tmp;
1443 int status = 0;
1444 int errors = 0;
1445 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1446 int direction = pipe % 2;
1447
1448 curr_td = curr_req->head;
1449 td_complete = 0;
1450 actual = curr_req->req.length;
1451
1452 for (j = 0; j < curr_req->dtd_count; j++) {
1453 remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
1454 & DTD_PACKET_SIZE)
1455 >> DTD_LENGTH_BIT_POS;
1456 actual -= remaining_length;
1457
1458 if ((errors = le32_to_cpu(curr_td->size_ioc_sts) &
1459 DTD_ERROR_MASK)) {
1460 if (errors & DTD_STATUS_HALTED) {
1461 ERR("dTD error %08x QH=%d\n", errors, pipe);
1462 /* Clear the errors and Halt condition */
1463 tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
1464 tmp &= ~errors;
1465 curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
1466 status = -EPIPE;
1467 /* FIXME: continue with next queued TD? */
1468
1469 break;
1470 }
1471 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1472 VDBG("Transfer overflow");
1473 status = -EPROTO;
1474 break;
1475 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1476 VDBG("ISO error");
1477 status = -EILSEQ;
1478 break;
1479 } else
1480 ERR("Unknown error has occured (0x%x)!\r\n",
1481 errors);
1482
1483 } else if (le32_to_cpu(curr_td->size_ioc_sts)
1484 & DTD_STATUS_ACTIVE) {
1485 VDBG("Request not complete");
1486 status = REQ_UNCOMPLETE;
1487 return status;
1488 } else if (remaining_length) {
1489 if (direction) {
1490 VDBG("Transmit dTD remaining length not zero");
1491 status = -EPROTO;
1492 break;
1493 } else {
1494 td_complete++;
1495 break;
1496 }
1497 } else {
1498 td_complete++;
1499 VDBG("dTD transmitted successful ");
1500 }
1501
1502 if (j != curr_req->dtd_count - 1)
1503 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1504 }
1505
1506 if (status)
1507 return status;
1508
1509 curr_req->req.actual = actual;
1510
1511 return 0;
1512 }
1513
1514 /* Process a DTD completion interrupt */
1515 static void dtd_complete_irq(struct fsl_udc *udc)
1516 {
1517 u32 bit_pos;
1518 int i, ep_num, direction, bit_mask, status;
1519 struct fsl_ep *curr_ep;
1520 struct fsl_req *curr_req, *temp_req;
1521
1522 /* Clear the bits in the register */
1523 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1524 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1525
1526 if (!bit_pos)
1527 return;
1528
1529 for (i = 0; i < udc->max_ep * 2; i++) {
1530 ep_num = i >> 1;
1531 direction = i % 2;
1532
1533 bit_mask = 1 << (ep_num + 16 * direction);
1534
1535 if (!(bit_pos & bit_mask))
1536 continue;
1537
1538 curr_ep = get_ep_by_pipe(udc, i);
1539
1540 /* If the ep is configured */
1541 if (curr_ep->name == NULL) {
1542 WARN("Invalid EP?");
1543 continue;
1544 }
1545
1546 /* process the req queue until an uncomplete request */
1547 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1548 queue) {
1549 status = process_ep_req(udc, i, curr_req);
1550
1551 VDBG("status of process_ep_req= %d, ep = %d",
1552 status, ep_num);
1553 if (status == REQ_UNCOMPLETE)
1554 break;
1555 /* write back status to req */
1556 curr_req->req.status = status;
1557
1558 if (ep_num == 0) {
1559 ep0_req_complete(udc, curr_ep, curr_req);
1560 break;
1561 } else
1562 done(curr_ep, curr_req, status);
1563 }
1564 }
1565 }
1566
1567 /* Process a port change interrupt */
1568 static void port_change_irq(struct fsl_udc *udc)
1569 {
1570 u32 speed;
1571
1572 if (udc->bus_reset)
1573 udc->bus_reset = 0;
1574
1575 /* Bus resetting is finished */
1576 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1577 /* Get the speed */
1578 speed = (fsl_readl(&dr_regs->portsc1)
1579 & PORTSCX_PORT_SPEED_MASK);
1580 switch (speed) {
1581 case PORTSCX_PORT_SPEED_HIGH:
1582 udc->gadget.speed = USB_SPEED_HIGH;
1583 break;
1584 case PORTSCX_PORT_SPEED_FULL:
1585 udc->gadget.speed = USB_SPEED_FULL;
1586 break;
1587 case PORTSCX_PORT_SPEED_LOW:
1588 udc->gadget.speed = USB_SPEED_LOW;
1589 break;
1590 default:
1591 udc->gadget.speed = USB_SPEED_UNKNOWN;
1592 break;
1593 }
1594 }
1595
1596 /* Update USB state */
1597 if (!udc->resume_state)
1598 udc->usb_state = USB_STATE_DEFAULT;
1599 }
1600
1601 /* Process suspend interrupt */
1602 static void suspend_irq(struct fsl_udc *udc)
1603 {
1604 udc->resume_state = udc->usb_state;
1605 udc->usb_state = USB_STATE_SUSPENDED;
1606
1607 /* report suspend to the driver, serial.c does not support this */
1608 if (udc->driver->suspend)
1609 udc->driver->suspend(&udc->gadget);
1610 }
1611
1612 static void bus_resume(struct fsl_udc *udc)
1613 {
1614 udc->usb_state = udc->resume_state;
1615 udc->resume_state = 0;
1616
1617 /* report resume to the driver, serial.c does not support this */
1618 if (udc->driver->resume)
1619 udc->driver->resume(&udc->gadget);
1620 }
1621
1622 /* Clear up all ep queues */
1623 static int reset_queues(struct fsl_udc *udc)
1624 {
1625 u8 pipe;
1626
1627 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1628 udc_reset_ep_queue(udc, pipe);
1629
1630 /* report disconnect; the driver is already quiesced */
1631 udc->driver->disconnect(&udc->gadget);
1632
1633 return 0;
1634 }
1635
1636 /* Process reset interrupt */
1637 static void reset_irq(struct fsl_udc *udc)
1638 {
1639 u32 temp;
1640 unsigned long timeout;
1641
1642 /* Clear the device address */
1643 temp = fsl_readl(&dr_regs->deviceaddr);
1644 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1645
1646 udc->device_address = 0;
1647
1648 /* Clear usb state */
1649 udc->resume_state = 0;
1650 udc->ep0_dir = 0;
1651 udc->ep0_state = WAIT_FOR_SETUP;
1652 udc->remote_wakeup = 0; /* default to 0 on reset */
1653 udc->gadget.b_hnp_enable = 0;
1654 udc->gadget.a_hnp_support = 0;
1655 udc->gadget.a_alt_hnp_support = 0;
1656
1657 /* Clear all the setup token semaphores */
1658 temp = fsl_readl(&dr_regs->endptsetupstat);
1659 fsl_writel(temp, &dr_regs->endptsetupstat);
1660
1661 /* Clear all the endpoint complete status bits */
1662 temp = fsl_readl(&dr_regs->endptcomplete);
1663 fsl_writel(temp, &dr_regs->endptcomplete);
1664
1665 timeout = jiffies + 100;
1666 while (fsl_readl(&dr_regs->endpointprime)) {
1667 /* Wait until all endptprime bits cleared */
1668 if (time_after(jiffies, timeout)) {
1669 ERR("Timeout for reset\n");
1670 break;
1671 }
1672 cpu_relax();
1673 }
1674
1675 /* Write 1s to the flush register */
1676 fsl_writel(0xffffffff, &dr_regs->endptflush);
1677
1678 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1679 VDBG("Bus reset");
1680 /* Bus is reseting */
1681 udc->bus_reset = 1;
1682 /* Reset all the queues, include XD, dTD, EP queue
1683 * head and TR Queue */
1684 reset_queues(udc);
1685 udc->usb_state = USB_STATE_DEFAULT;
1686 } else {
1687 VDBG("Controller reset");
1688 /* initialize usb hw reg except for regs for EP, not
1689 * touch usbintr reg */
1690 dr_controller_setup(udc);
1691
1692 /* Reset all internal used Queues */
1693 reset_queues(udc);
1694
1695 ep0_setup(udc);
1696
1697 /* Enable DR IRQ reg, Set Run bit, change udc state */
1698 dr_controller_run(udc);
1699 udc->usb_state = USB_STATE_ATTACHED;
1700 }
1701 }
1702
1703 /*
1704 * USB device controller interrupt handler
1705 */
1706 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1707 {
1708 struct fsl_udc *udc = _udc;
1709 u32 irq_src;
1710 irqreturn_t status = IRQ_NONE;
1711 unsigned long flags;
1712
1713 /* Disable ISR for OTG host mode */
1714 if (udc->stopped)
1715 return IRQ_NONE;
1716 spin_lock_irqsave(&udc->lock, flags);
1717 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1718 /* Clear notification bits */
1719 fsl_writel(irq_src, &dr_regs->usbsts);
1720
1721 /* VDBG("irq_src [0x%8x]", irq_src); */
1722
1723 /* Need to resume? */
1724 if (udc->usb_state == USB_STATE_SUSPENDED)
1725 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1726 bus_resume(udc);
1727
1728 /* USB Interrupt */
1729 if (irq_src & USB_STS_INT) {
1730 VDBG("Packet int");
1731 /* Setup package, we only support ep0 as control ep */
1732 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1733 tripwire_handler(udc, 0,
1734 (u8 *) (&udc->local_setup_buff));
1735 setup_received_irq(udc, &udc->local_setup_buff);
1736 status = IRQ_HANDLED;
1737 }
1738
1739 /* completion of dtd */
1740 if (fsl_readl(&dr_regs->endptcomplete)) {
1741 dtd_complete_irq(udc);
1742 status = IRQ_HANDLED;
1743 }
1744 }
1745
1746 /* SOF (for ISO transfer) */
1747 if (irq_src & USB_STS_SOF) {
1748 status = IRQ_HANDLED;
1749 }
1750
1751 /* Port Change */
1752 if (irq_src & USB_STS_PORT_CHANGE) {
1753 port_change_irq(udc);
1754 status = IRQ_HANDLED;
1755 }
1756
1757 /* Reset Received */
1758 if (irq_src & USB_STS_RESET) {
1759 reset_irq(udc);
1760 status = IRQ_HANDLED;
1761 }
1762
1763 /* Sleep Enable (Suspend) */
1764 if (irq_src & USB_STS_SUSPEND) {
1765 suspend_irq(udc);
1766 status = IRQ_HANDLED;
1767 }
1768
1769 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1770 VDBG("Error IRQ %x ", irq_src);
1771 }
1772
1773 spin_unlock_irqrestore(&udc->lock, flags);
1774 return status;
1775 }
1776
1777 /*----------------------------------------------------------------*
1778 * Hook to gadget drivers
1779 * Called by initialization code of gadget drivers
1780 *----------------------------------------------------------------*/
1781 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1782 {
1783 int retval = -ENODEV;
1784 unsigned long flags = 0;
1785
1786 if (!udc_controller)
1787 return -ENODEV;
1788
1789 if (!driver || (driver->speed != USB_SPEED_FULL
1790 && driver->speed != USB_SPEED_HIGH)
1791 || !driver->bind || !driver->disconnect
1792 || !driver->setup)
1793 return -EINVAL;
1794
1795 if (udc_controller->driver)
1796 return -EBUSY;
1797
1798 /* lock is needed but whether should use this lock or another */
1799 spin_lock_irqsave(&udc_controller->lock, flags);
1800
1801 driver->driver.bus = 0;
1802 /* hook up the driver */
1803 udc_controller->driver = driver;
1804 udc_controller->gadget.dev.driver = &driver->driver;
1805 spin_unlock_irqrestore(&udc_controller->lock, flags);
1806
1807 /* bind udc driver to gadget driver */
1808 retval = driver->bind(&udc_controller->gadget);
1809 if (retval) {
1810 VDBG("bind to %s --> %d", driver->driver.name, retval);
1811 udc_controller->gadget.dev.driver = 0;
1812 udc_controller->driver = 0;
1813 goto out;
1814 }
1815
1816 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
1817 dr_controller_run(udc_controller);
1818 udc_controller->usb_state = USB_STATE_ATTACHED;
1819 udc_controller->ep0_state = WAIT_FOR_SETUP;
1820 udc_controller->ep0_dir = 0;
1821 printk(KERN_INFO "%s: bind to driver %s \n",
1822 udc_controller->gadget.name, driver->driver.name);
1823
1824 out:
1825 if (retval)
1826 printk("retval %d \n", retval);
1827 return retval;
1828 }
1829 EXPORT_SYMBOL(usb_gadget_register_driver);
1830
1831 /* Disconnect from gadget driver */
1832 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1833 {
1834 struct fsl_ep *loop_ep;
1835 unsigned long flags;
1836
1837 if (!udc_controller)
1838 return -ENODEV;
1839
1840 if (!driver || driver != udc_controller->driver || !driver->unbind)
1841 return -EINVAL;
1842
1843 #ifdef CONFIG_USB_OTG
1844 if (udc_controller->transceiver)
1845 (void)otg_set_peripheral(udc_controller->transceiver, 0);
1846 #endif
1847
1848 /* stop DR, disable intr */
1849 dr_controller_stop(udc_controller);
1850
1851 /* in fact, no needed */
1852 udc_controller->usb_state = USB_STATE_ATTACHED;
1853 udc_controller->ep0_state = WAIT_FOR_SETUP;
1854 udc_controller->ep0_dir = 0;
1855
1856 /* stand operation */
1857 spin_lock_irqsave(&udc_controller->lock, flags);
1858 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1859 nuke(&udc_controller->eps[0], -ESHUTDOWN);
1860 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1861 ep.ep_list)
1862 nuke(loop_ep, -ESHUTDOWN);
1863 spin_unlock_irqrestore(&udc_controller->lock, flags);
1864
1865 /* unbind gadget and unhook driver. */
1866 driver->unbind(&udc_controller->gadget);
1867 udc_controller->gadget.dev.driver = 0;
1868 udc_controller->driver = 0;
1869
1870 printk("unregistered gadget driver '%s'\r\n", driver->driver.name);
1871 return 0;
1872 }
1873 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1874
1875 /*-------------------------------------------------------------------------
1876 PROC File System Support
1877 -------------------------------------------------------------------------*/
1878 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1879
1880 #include <linux/seq_file.h>
1881
1882 static const char proc_filename[] = "driver/fsl_usb2_udc";
1883
1884 static int fsl_proc_read(char *page, char **start, off_t off, int count,
1885 int *eof, void *_dev)
1886 {
1887 char *buf = page;
1888 char *next = buf;
1889 unsigned size = count;
1890 unsigned long flags;
1891 int t, i;
1892 u32 tmp_reg;
1893 struct fsl_ep *ep = NULL;
1894 struct fsl_req *req;
1895
1896 struct fsl_udc *udc = udc_controller;
1897 if (off != 0)
1898 return 0;
1899
1900 spin_lock_irqsave(&udc->lock, flags);
1901
1902 /* ------basic driver infomation ---- */
1903 t = scnprintf(next, size,
1904 DRIVER_DESC "\n"
1905 "%s version: %s\n"
1906 "Gadget driver: %s\n\n",
1907 driver_name, DRIVER_VERSION,
1908 udc->driver ? udc->driver->driver.name : "(none)");
1909 size -= t;
1910 next += t;
1911
1912 /* ------ DR Registers ----- */
1913 tmp_reg = fsl_readl(&dr_regs->usbcmd);
1914 t = scnprintf(next, size,
1915 "USBCMD reg:\n"
1916 "SetupTW: %d\n"
1917 "Run/Stop: %s\n\n",
1918 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
1919 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
1920 size -= t;
1921 next += t;
1922
1923 tmp_reg = fsl_readl(&dr_regs->usbsts);
1924 t = scnprintf(next, size,
1925 "USB Status Reg:\n"
1926 "Dr Suspend: %d" "Reset Received: %d" "System Error: %s"
1927 "USB Error Interrupt: %s\n\n",
1928 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
1929 (tmp_reg & USB_STS_RESET) ? 1 : 0,
1930 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
1931 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
1932 size -= t;
1933 next += t;
1934
1935 tmp_reg = fsl_readl(&dr_regs->usbintr);
1936 t = scnprintf(next, size,
1937 "USB Intrrupt Enable Reg:\n"
1938 "Sleep Enable: %d" "SOF Received Enable: %d"
1939 "Reset Enable: %d\n"
1940 "System Error Enable: %d"
1941 "Port Change Dectected Enable: %d\n"
1942 "USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n",
1943 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
1944 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
1945 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
1946 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
1947 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
1948 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
1949 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
1950 size -= t;
1951 next += t;
1952
1953 tmp_reg = fsl_readl(&dr_regs->frindex);
1954 t = scnprintf(next, size,
1955 "USB Frame Index Reg:" "Frame Number is 0x%x\n\n",
1956 (tmp_reg & USB_FRINDEX_MASKS));
1957 size -= t;
1958 next += t;
1959
1960 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
1961 t = scnprintf(next, size,
1962 "USB Device Address Reg:" "Device Addr is 0x%x\n\n",
1963 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
1964 size -= t;
1965 next += t;
1966
1967 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
1968 t = scnprintf(next, size,
1969 "USB Endpoint List Address Reg:"
1970 "Device Addr is 0x%x\n\n",
1971 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
1972 size -= t;
1973 next += t;
1974
1975 tmp_reg = fsl_readl(&dr_regs->portsc1);
1976 t = scnprintf(next, size,
1977 "USB Port Status&Control Reg:\n"
1978 "Port Transceiver Type : %s" "Port Speed: %s \n"
1979 "PHY Low Power Suspend: %s" "Port Reset: %s"
1980 "Port Suspend Mode: %s \n" "Over-current Change: %s"
1981 "Port Enable/Disable Change: %s\n"
1982 "Port Enabled/Disabled: %s"
1983 "Current Connect Status: %s\n\n", ( {
1984 char *s;
1985 switch (tmp_reg & PORTSCX_PTS_FSLS) {
1986 case PORTSCX_PTS_UTMI:
1987 s = "UTMI"; break;
1988 case PORTSCX_PTS_ULPI:
1989 s = "ULPI "; break;
1990 case PORTSCX_PTS_FSLS:
1991 s = "FS/LS Serial"; break;
1992 default:
1993 s = "None"; break;
1994 }
1995 s;} ), ( {
1996 char *s;
1997 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
1998 case PORTSCX_PORT_SPEED_FULL:
1999 s = "Full Speed"; break;
2000 case PORTSCX_PORT_SPEED_LOW:
2001 s = "Low Speed"; break;
2002 case PORTSCX_PORT_SPEED_HIGH:
2003 s = "High Speed"; break;
2004 default:
2005 s = "Undefined"; break;
2006 }
2007 s;
2008 } ),
2009 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2010 "Normal PHY mode" : "Low power mode",
2011 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2012 "Not in Reset",
2013 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2014 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2015 "No",
2016 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2017 "Not change",
2018 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2019 "Not correct",
2020 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2021 "Attached" : "Not-Att");
2022 size -= t;
2023 next += t;
2024
2025 tmp_reg = fsl_readl(&dr_regs->usbmode);
2026 t = scnprintf(next, size,
2027 "USB Mode Reg:" "Controller Mode is : %s\n\n", ( {
2028 char *s;
2029 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2030 case USB_MODE_CTRL_MODE_IDLE:
2031 s = "Idle"; break;
2032 case USB_MODE_CTRL_MODE_DEVICE:
2033 s = "Device Controller"; break;
2034 case USB_MODE_CTRL_MODE_HOST:
2035 s = "Host Controller"; break;
2036 default:
2037 s = "None"; break;
2038 }
2039 s;
2040 } ));
2041 size -= t;
2042 next += t;
2043
2044 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2045 t = scnprintf(next, size,
2046 "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
2047 (tmp_reg & EP_SETUP_STATUS_MASK));
2048 size -= t;
2049 next += t;
2050
2051 for (i = 0; i < udc->max_ep / 2; i++) {
2052 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2053 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2054 i, tmp_reg);
2055 size -= t;
2056 next += t;
2057 }
2058 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2059 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
2060 size -= t;
2061 next += t;
2062
2063 tmp_reg = usb_sys_regs->snoop1;
2064 t = scnprintf(next, size, "\nSnoop1 Reg : = [0x%x]\n\n", tmp_reg);
2065 size -= t;
2066 next += t;
2067
2068 tmp_reg = usb_sys_regs->control;
2069 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2070 tmp_reg);
2071 size -= t;
2072 next += t;
2073
2074 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2075 ep = &udc->eps[0];
2076 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2077 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2078 size -= t;
2079 next += t;
2080
2081 if (list_empty(&ep->queue)) {
2082 t = scnprintf(next, size, "its req queue is empty\n\n");
2083 size -= t;
2084 next += t;
2085 } else {
2086 list_for_each_entry(req, &ep->queue, queue) {
2087 t = scnprintf(next, size,
2088 "req %p actual 0x%x length 0x%x buf %p\n",
2089 &req->req, req->req.actual,
2090 req->req.length, req->req.buf);
2091 size -= t;
2092 next += t;
2093 }
2094 }
2095 /* other gadget->eplist ep */
2096 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2097 if (ep->desc) {
2098 t = scnprintf(next, size,
2099 "\nFor %s Maxpkt is 0x%x "
2100 "index is 0x%x\n",
2101 ep->ep.name, ep_maxpacket(ep),
2102 ep_index(ep));
2103 size -= t;
2104 next += t;
2105
2106 if (list_empty(&ep->queue)) {
2107 t = scnprintf(next, size,
2108 "its req queue is empty\n\n");
2109 size -= t;
2110 next += t;
2111 } else {
2112 list_for_each_entry(req, &ep->queue, queue) {
2113 t = scnprintf(next, size,
2114 "req %p actual 0x%x length"
2115 "0x%x buf %p\n",
2116 &req->req, req->req.actual,
2117 req->req.length, req->req.buf);
2118 size -= t;
2119 next += t;
2120 } /* end for each_entry of ep req */
2121 } /* end for else */
2122 } /* end for if(ep->queue) */
2123 } /* end (ep->desc) */
2124
2125 spin_unlock_irqrestore(&udc->lock, flags);
2126
2127 *eof = 1;
2128 return count - size;
2129 }
2130
2131 #define create_proc_file() create_proc_read_entry(proc_filename, \
2132 0, NULL, fsl_proc_read, NULL)
2133
2134 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2135
2136 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2137
2138 #define create_proc_file() do {} while (0)
2139 #define remove_proc_file() do {} while (0)
2140
2141 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2142
2143 /*-------------------------------------------------------------------------*/
2144
2145 /* Release udc structures */
2146 static void fsl_udc_release(struct device *dev)
2147 {
2148 complete(udc_controller->done);
2149 dma_free_coherent(dev, udc_controller->ep_qh_size,
2150 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2151 kfree(udc_controller);
2152 }
2153
2154 /******************************************************************
2155 Internal structure setup functions
2156 *******************************************************************/
2157 /*------------------------------------------------------------------
2158 * init resource for globle controller
2159 * Return the udc handle on success or NULL on failure
2160 ------------------------------------------------------------------*/
2161 static int __init struct_udc_setup(struct fsl_udc *udc,
2162 struct platform_device *pdev)
2163 {
2164 struct fsl_usb2_platform_data *pdata;
2165 size_t size;
2166
2167 pdata = pdev->dev.platform_data;
2168 udc->phy_mode = pdata->phy_mode;
2169
2170 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2171 if (!udc->eps) {
2172 ERR("malloc fsl_ep failed\n");
2173 return -1;
2174 }
2175
2176 /* initialized QHs, take care of alignment */
2177 size = udc->max_ep * sizeof(struct ep_queue_head);
2178 if (size < QH_ALIGNMENT)
2179 size = QH_ALIGNMENT;
2180 else if ((size % QH_ALIGNMENT) != 0) {
2181 size += QH_ALIGNMENT + 1;
2182 size &= ~(QH_ALIGNMENT - 1);
2183 }
2184 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2185 &udc->ep_qh_dma, GFP_KERNEL);
2186 if (!udc->ep_qh) {
2187 ERR("malloc QHs for udc failed\n");
2188 kfree(udc->eps);
2189 return -1;
2190 }
2191
2192 udc->ep_qh_size = size;
2193
2194 /* Initialize ep0 status request structure */
2195 /* FIXME: fsl_alloc_request() ignores ep argument */
2196 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2197 struct fsl_req, req);
2198 /* allocate a small amount of memory to get valid address */
2199 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2200 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2201
2202 udc->resume_state = USB_STATE_NOTATTACHED;
2203 udc->usb_state = USB_STATE_POWERED;
2204 udc->ep0_dir = 0;
2205 udc->remote_wakeup = 0; /* default to 0 on reset */
2206 spin_lock_init(&udc->lock);
2207
2208 return 0;
2209 }
2210
2211 /*----------------------------------------------------------------
2212 * Setup the fsl_ep struct for eps
2213 * Link fsl_ep->ep to gadget->ep_list
2214 * ep0out is not used so do nothing here
2215 * ep0in should be taken care
2216 *--------------------------------------------------------------*/
2217 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2218 char *name, int link)
2219 {
2220 struct fsl_ep *ep = &udc->eps[index];
2221
2222 ep->udc = udc;
2223 strcpy(ep->name, name);
2224 ep->ep.name = ep->name;
2225
2226 ep->ep.ops = &fsl_ep_ops;
2227 ep->stopped = 0;
2228
2229 /* for ep0: maxP defined in desc
2230 * for other eps, maxP is set by epautoconfig() called by gadget layer
2231 */
2232 ep->ep.maxpacket = (unsigned short) ~0;
2233
2234 /* the queue lists any req for this ep */
2235 INIT_LIST_HEAD(&ep->queue);
2236
2237 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2238 if (link)
2239 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2240 ep->gadget = &udc->gadget;
2241 ep->qh = &udc->ep_qh[index];
2242
2243 return 0;
2244 }
2245
2246 /* Driver probe function
2247 * all intialization operations implemented here except enabling usb_intr reg
2248 * board setup should have been done in the platform code
2249 */
2250 static int __init fsl_udc_probe(struct platform_device *pdev)
2251 {
2252 struct resource *res;
2253 int ret = -ENODEV;
2254 unsigned int i;
2255 u32 dccparams;
2256
2257 if (strcmp(pdev->name, driver_name)) {
2258 VDBG("Wrong device\n");
2259 return -ENODEV;
2260 }
2261
2262 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2263 if (udc_controller == NULL) {
2264 ERR("malloc udc failed\n");
2265 return -ENOMEM;
2266 }
2267
2268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2269 if (!res) {
2270 kfree(udc_controller);
2271 return -ENXIO;
2272 }
2273
2274 if (!request_mem_region(res->start, res->end - res->start + 1,
2275 driver_name)) {
2276 ERR("request mem region for %s failed \n", pdev->name);
2277 kfree(udc_controller);
2278 return -EBUSY;
2279 }
2280
2281 dr_regs = ioremap(res->start, res->end - res->start + 1);
2282 if (!dr_regs) {
2283 ret = -ENOMEM;
2284 goto err1;
2285 }
2286
2287 usb_sys_regs = (struct usb_sys_interface *)
2288 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2289
2290 /* Read Device Controller Capability Parameters register */
2291 dccparams = fsl_readl(&dr_regs->dccparams);
2292 if (!(dccparams & DCCPARAMS_DC)) {
2293 ERR("This SOC doesn't support device role\n");
2294 ret = -ENODEV;
2295 goto err2;
2296 }
2297 /* Get max device endpoints */
2298 /* DEN is bidirectional ep number, max_ep doubles the number */
2299 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2300
2301 udc_controller->irq = platform_get_irq(pdev, 0);
2302 if (!udc_controller->irq) {
2303 ret = -ENODEV;
2304 goto err2;
2305 }
2306
2307 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2308 driver_name, udc_controller);
2309 if (ret != 0) {
2310 ERR("cannot request irq %d err %d \n",
2311 udc_controller->irq, ret);
2312 goto err2;
2313 }
2314
2315 /* Initialize the udc structure including QH member and other member */
2316 if (struct_udc_setup(udc_controller, pdev)) {
2317 ERR("Can't initialize udc data structure\n");
2318 ret = -ENOMEM;
2319 goto err3;
2320 }
2321
2322 /* initialize usb hw reg except for regs for EP,
2323 * leave usbintr reg untouched */
2324 dr_controller_setup(udc_controller);
2325
2326 /* Setup gadget structure */
2327 udc_controller->gadget.ops = &fsl_gadget_ops;
2328 udc_controller->gadget.is_dualspeed = 1;
2329 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2330 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2331 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2332 udc_controller->gadget.name = driver_name;
2333
2334 /* Setup gadget.dev and register with kernel */
2335 strcpy(udc_controller->gadget.dev.bus_id, "gadget");
2336 udc_controller->gadget.dev.release = fsl_udc_release;
2337 udc_controller->gadget.dev.parent = &pdev->dev;
2338 ret = device_register(&udc_controller->gadget.dev);
2339 if (ret < 0)
2340 goto err3;
2341
2342 /* setup QH and epctrl for ep0 */
2343 ep0_setup(udc_controller);
2344
2345 /* setup udc->eps[] for ep0 */
2346 struct_ep_setup(udc_controller, 0, "ep0", 0);
2347 /* for ep0: the desc defined here;
2348 * for other eps, gadget layer called ep_enable with defined desc
2349 */
2350 udc_controller->eps[0].desc = &fsl_ep0_desc;
2351 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2352
2353 /* setup the udc->eps[] for non-control endpoints and link
2354 * to gadget.ep_list */
2355 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2356 char name[14];
2357
2358 sprintf(name, "ep%dout", i);
2359 struct_ep_setup(udc_controller, i * 2, name, 1);
2360 sprintf(name, "ep%din", i);
2361 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2362 }
2363
2364 /* use dma_pool for TD management */
2365 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2366 sizeof(struct ep_td_struct),
2367 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2368 if (udc_controller->td_pool == NULL) {
2369 ret = -ENOMEM;
2370 goto err4;
2371 }
2372 create_proc_file();
2373 return 0;
2374
2375 err4:
2376 device_unregister(&udc_controller->gadget.dev);
2377 err3:
2378 free_irq(udc_controller->irq, udc_controller);
2379 err2:
2380 iounmap(dr_regs);
2381 err1:
2382 release_mem_region(res->start, res->end - res->start + 1);
2383 kfree(udc_controller);
2384 return ret;
2385 }
2386
2387 /* Driver removal function
2388 * Free resources and finish pending transactions
2389 */
2390 static int __exit fsl_udc_remove(struct platform_device *pdev)
2391 {
2392 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2393
2394 DECLARE_COMPLETION(done);
2395
2396 if (!udc_controller)
2397 return -ENODEV;
2398 udc_controller->done = &done;
2399
2400 /* DR has been stopped in usb_gadget_unregister_driver() */
2401 remove_proc_file();
2402
2403 /* Free allocated memory */
2404 kfree(udc_controller->status_req->req.buf);
2405 kfree(udc_controller->status_req);
2406 kfree(udc_controller->eps);
2407
2408 dma_pool_destroy(udc_controller->td_pool);
2409 free_irq(udc_controller->irq, udc_controller);
2410 iounmap(dr_regs);
2411 release_mem_region(res->start, res->end - res->start + 1);
2412
2413 device_unregister(&udc_controller->gadget.dev);
2414 /* free udc --wait for the release() finished */
2415 wait_for_completion(&done);
2416
2417 return 0;
2418 }
2419
2420 /*-----------------------------------------------------------------
2421 * Modify Power management attributes
2422 * Used by OTG statemachine to disable gadget temporarily
2423 -----------------------------------------------------------------*/
2424 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2425 {
2426 dr_controller_stop(udc_controller);
2427 return 0;
2428 }
2429
2430 /*-----------------------------------------------------------------
2431 * Invoked on USB resume. May be called in_interrupt.
2432 * Here we start the DR controller and enable the irq
2433 *-----------------------------------------------------------------*/
2434 static int fsl_udc_resume(struct platform_device *pdev)
2435 {
2436 /* Enable DR irq reg and set controller Run */
2437 if (udc_controller->stopped) {
2438 dr_controller_setup(udc_controller);
2439 dr_controller_run(udc_controller);
2440 }
2441 udc_controller->usb_state = USB_STATE_ATTACHED;
2442 udc_controller->ep0_state = WAIT_FOR_SETUP;
2443 udc_controller->ep0_dir = 0;
2444 return 0;
2445 }
2446
2447 /*-------------------------------------------------------------------------
2448 Register entry point for the peripheral controller driver
2449 --------------------------------------------------------------------------*/
2450
2451 static struct platform_driver udc_driver = {
2452 .remove = __exit_p(fsl_udc_remove),
2453 /* these suspend and resume are not usb suspend and resume */
2454 .suspend = fsl_udc_suspend,
2455 .resume = fsl_udc_resume,
2456 .driver = {
2457 .name = (char *)driver_name,
2458 .owner = THIS_MODULE,
2459 },
2460 };
2461
2462 static int __init udc_init(void)
2463 {
2464 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2465 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2466 }
2467
2468 module_init(udc_init);
2469
2470 static void __exit udc_exit(void)
2471 {
2472 platform_driver_unregister(&udc_driver);
2473 printk("%s unregistered \n", driver_desc);
2474 }
2475
2476 module_exit(udc_exit);
2477
2478 MODULE_DESCRIPTION(DRIVER_DESC);
2479 MODULE_AUTHOR(DRIVER_AUTHOR);
2480 MODULE_LICENSE("GPL");
Tomato firmware and modifications.