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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / scsi / 53c700.h
blob841e1bb27d57eb54ae0142c2c64e4009fdb1cc51
1 /* -*- mode: c; c-basic-offset: 8 -*- */
2
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
4 *
5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
6 */
7
8 #ifndef _53C700_H
9 #define _53C700_H
10
11 #include <linux/interrupt.h>
12 #include <asm/io.h>
13
14 #include <scsi/scsi_device.h>
15 #include <scsi/scsi_cmnd.h>
16
17 /* Turn on for general debugging---too verbose for normal use */
18 #undef NCR_700_DEBUG
19 /* Debug the tag queues, checking hash queue allocation and deallocation
20 * and search for duplicate tags */
21 #undef NCR_700_TAG_DEBUG
22
23 #ifdef NCR_700_DEBUG
24 #define DEBUG(x) printk x
25 #define DDEBUG(prefix, sdev, fmt, a...) \
26 sdev_printk(prefix, sdev, fmt, ##a)
27 #define CDEBUG(prefix, scmd, fmt, a...) \
28 scmd_printk(prefix, scmd, fmt, ##a)
29 #else
30 #define DEBUG(x) do {} while (0)
31 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
32 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
33 #endif
34
35 /* The number of available command slots */
36 #define NCR_700_COMMAND_SLOTS_PER_HOST 64
37 /* The maximum number of Scatter Gathers we allow */
38 #define NCR_700_SG_SEGMENTS 32
39 /* The maximum number of luns (make this of the form 2^n) */
40 #define NCR_700_MAX_LUNS 32
41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
42 /* Maximum number of tags the driver ever allows per device */
43 #define NCR_700_MAX_TAGS 16
44 /* Tag depth the driver starts out with (can be altered in sysfs) */
45 #define NCR_700_DEFAULT_TAGS 4
46 /* This is the default number of commands per LUN in the untagged case.
47 * two is a good value because it means we can have one command active and
48 * one command fully prepared and waiting
49 */
50 #define NCR_700_CMD_PER_LUN 2
51 /* magic byte identifying an internally generated REQUEST_SENSE command */
52 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42
53
54 struct NCR_700_Host_Parameters;
55
56 /* These are the externally used routines */
57 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
58 struct NCR_700_Host_Parameters *, struct device *);
59 int NCR_700_release(struct Scsi_Host *host);
60 irqreturn_t NCR_700_intr(int, void *);
61
62
63 enum NCR_700_Host_State {
64 NCR_700_HOST_BUSY,
65 NCR_700_HOST_FREE,
66 };
67
68 struct NCR_700_SG_List {
69 /* The following is a script fragment to move the buffer onto the
70 * bus and then link the next fragment or return */
71 #define SCRIPT_MOVE_DATA_IN 0x09000000
72 #define SCRIPT_MOVE_DATA_OUT 0x08000000
73 __u32 ins;
74 __u32 pAddr;
75 #define SCRIPT_NOP 0x80000000
76 #define SCRIPT_RETURN 0x90080000
77 };
78
79 struct NCR_700_Device_Parameters {
80 /* space for creating a request sense command. Really, except
81 * for the annoying SCSI-2 requirement for LUN information in
82 * cmnd[1], this could be in static storage */
83 unsigned char cmnd[MAX_COMMAND_SIZE];
84 __u8 depth;
85 };
86
87
88 /* The SYNC negotiation sequence looks like:
89 *
90 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
91 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
92 * If we get an SDTR reply, work out the SXFER parameters, squirrel
93 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
94 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
95 *
96 *
97 * 0:7 SXFER_REG negotiated value for this device
98 * 8:15 Current queue depth
99 * 16 negotiated SYNC flag
100 * 17 begin SYNC negotiation flag
101 * 18 device supports tag queueing */
102 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
103 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
104 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
105
106 static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
107 {
108 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
109
110 return hostdata->cmnd;
111 }
112
113 static inline void
114 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
115 {
116 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
117
118 hostdata->depth = depth;
119 }
120 static inline __u8
121 NCR_700_get_depth(struct scsi_device *SDp)
122 {
123 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
124
125 return hostdata->depth;
126 }
127 static inline int
128 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
129 {
130 return (spi_flags(SDp->sdev_target) & flag) == flag;
131 }
132 static inline int
133 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
134 {
135 return (spi_flags(SDp->sdev_target) & flag) == 0;
136 }
137 static inline void
138 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
139 {
140 spi_flags(SDp->sdev_target) |= flag;
141 }
142 static inline void
143 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
144 {
145 spi_flags(SDp->sdev_target) &= ~flag;
146 }
147
148 enum NCR_700_tag_neg_state {
149 NCR_700_START_TAG_NEGOTIATION = 0,
150 NCR_700_DURING_TAG_NEGOTIATION = 1,
151 NCR_700_FINISHED_TAG_NEGOTIATION = 2,
152 };
153
154 static inline enum NCR_700_tag_neg_state
155 NCR_700_get_tag_neg_state(struct scsi_device *SDp)
156 {
157 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
158 }
159
160 static inline void
161 NCR_700_set_tag_neg_state(struct scsi_device *SDp,
162 enum NCR_700_tag_neg_state state)
163 {
164 /* clear the slot */
165 spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
166 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
167 }
168
169 struct NCR_700_command_slot {
170 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
171 struct NCR_700_SG_List *pSG;
172 #define NCR_700_SLOT_MASK 0xFC
173 #define NCR_700_SLOT_MAGIC 0xb8
174 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
175 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
176 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
177 __u8 state;
178 #define NCR_700_FLAG_AUTOSENSE 0x01
179 __u8 flags;
180 int tag;
181 __u32 resume_offset;
182 struct scsi_cmnd *cmnd;
183 /* The pci_mapped address of the actual command in cmnd */
184 dma_addr_t pCmd;
185 __u32 temp;
186 /* if this command is a pci_single mapping, holds the dma address
187 * for later unmapping in the done routine */
188 dma_addr_t dma_handle;
189 /* historical remnant, now used to link free commands */
190 struct NCR_700_command_slot *ITL_forw;
191 };
192
193 struct NCR_700_Host_Parameters {
194 /* These must be filled in by the calling driver */
195 int clock; /* board clock speed in MHz */
196 void __iomem *base; /* the base for the port (copied to host) */
197 struct device *dev;
198 __u32 dmode_extra; /* adjustable bus settings */
199 __u32 differential:1; /* if we are differential */
200 #ifdef CONFIG_53C700_LE_ON_BE
201 /* This option is for HP only. Set it if your chip is wired for
202 * little endian on this platform (which is big endian) */
203 __u32 force_le_on_be:1;
204 #endif
205 __u32 chip710:1; /* set if really a 710 not 700 */
206 __u32 burst_length:4; /* set to 0 to disable 710 bursting */
207
208 /* NOTHING BELOW HERE NEEDS ALTERING */
209 __u32 fast:1; /* if we can alter the SCSI bus clock
210 speed (so can negiotiate sync) */
211 int sync_clock; /* The speed of the SYNC core */
212
213 __u32 *script; /* pointer to script location */
214 __u32 pScript; /* physical mem addr of script */
215
216 enum NCR_700_Host_State state; /* protected by state lock */
217 struct scsi_cmnd *cmd;
218 /* Note: pScript contains the single consistent block of
219 * memory. All the msgin, msgout and status are allocated in
220 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
221 * represents the total size of this area */
222 #define MSG_ARRAY_SIZE 8
223 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
224 __u8 *msgout;
225 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
226 __u8 *msgin;
227 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
228 __u8 *status;
229 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
230 struct NCR_700_command_slot *slots;
231 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
232 int saved_slot_position;
233 int command_slot_count; /* protected by state lock */
234 __u8 tag_negotiated;
235 __u8 rev;
236 __u8 reselection_id;
237 __u8 min_period;
238
239 /* Free list, singly linked by ITL_forw elements */
240 struct NCR_700_command_slot *free_list;
241 /* Completion for waited for ops, like reset, abort or
242 * device reset.
243 *
244 * NOTE: relies on single threading in the error handler to
245 * have only one outstanding at once */
246 struct completion *eh_complete;
247 };
248
249 /*
250 * 53C700 Register Interface - the offset from the Selected base
251 * I/O address */
252 #ifdef CONFIG_53C700_LE_ON_BE
253 #define bE (hostdata->force_le_on_be ? 0 : 3)
254 #define bSWAP (hostdata->force_le_on_be)
255 #define bEBus (!hostdata->force_le_on_be)
256 #elif defined(__BIG_ENDIAN)
257 #define bE 3
258 #define bSWAP 0
259 #elif defined(__LITTLE_ENDIAN)
260 #define bE 0
261 #define bSWAP 0
262 #else
263 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
264 #endif
265 #ifndef bEBus
266 #ifdef CONFIG_53C700_BE_BUS
267 #define bEBus 1
268 #else
269 #define bEBus 0
270 #endif
271 #endif
272 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
273 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
274
275 /* NOTE: These registers are in the LE register space only, the required byte
276 * swapping is done by the NCR_700_{read|write}[b] functions */
277 #define SCNTL0_REG 0x00
278 #define FULL_ARBITRATION 0xc0
279 #define PARITY 0x08
280 #define ENABLE_PARITY 0x04
281 #define AUTO_ATN 0x02
282 #define SCNTL1_REG 0x01
283 #define SLOW_BUS 0x80
284 #define ENABLE_SELECT 0x20
285 #define ASSERT_RST 0x08
286 #define ASSERT_EVEN_PARITY 0x04
287 #define SDID_REG 0x02
288 #define SIEN_REG 0x03
289 #define PHASE_MM_INT 0x80
290 #define FUNC_COMP_INT 0x40
291 #define SEL_TIMEOUT_INT 0x20
292 #define SELECT_INT 0x10
293 #define GROSS_ERR_INT 0x08
294 #define UX_DISC_INT 0x04
295 #define RST_INT 0x02
296 #define PAR_ERR_INT 0x01
297 #define SCID_REG 0x04
298 #define SXFER_REG 0x05
299 #define ASYNC_OPERATION 0x00
300 #define SODL_REG 0x06
301 #define SOCL_REG 0x07
302 #define SFBR_REG 0x08
303 #define SIDL_REG 0x09
304 #define SBDL_REG 0x0A
305 #define SBCL_REG 0x0B
306 /* read bits */
307 #define SBCL_IO 0x01
308 /*write bits */
309 #define SYNC_DIV_AS_ASYNC 0x00
310 #define SYNC_DIV_1_0 0x01
311 #define SYNC_DIV_1_5 0x02
312 #define SYNC_DIV_2_0 0x03
313 #define DSTAT_REG 0x0C
314 #define ILGL_INST_DETECTED 0x01
315 #define WATCH_DOG_INTERRUPT 0x02
316 #define SCRIPT_INT_RECEIVED 0x04
317 #define ABORTED 0x10
318 #define SSTAT0_REG 0x0D
319 #define PARITY_ERROR 0x01
320 #define SCSI_RESET_DETECTED 0x02
321 #define UNEXPECTED_DISCONNECT 0x04
322 #define SCSI_GROSS_ERROR 0x08
323 #define SELECTED 0x10
324 #define SELECTION_TIMEOUT 0x20
325 #define FUNCTION_COMPLETE 0x40
326 #define PHASE_MISMATCH 0x80
327 #define SSTAT1_REG 0x0E
328 #define SIDL_REG_FULL 0x80
329 #define SODR_REG_FULL 0x40
330 #define SODL_REG_FULL 0x20
331 #define SSTAT2_REG 0x0F
332 #define CTEST0_REG 0x14
333 #define BTB_TIMER_DISABLE 0x40
334 #define CTEST1_REG 0x15
335 #define CTEST2_REG 0x16
336 #define CTEST3_REG 0x17
337 #define CTEST4_REG 0x18
338 #define DISABLE_FIFO 0x00
339 #define SLBE 0x10
340 #define SFWR 0x08
341 #define BYTE_LANE0 0x04
342 #define BYTE_LANE1 0x05
343 #define BYTE_LANE2 0x06
344 #define BYTE_LANE3 0x07
345 #define SCSI_ZMODE 0x20
346 #define ZMODE 0x40
347 #define CTEST5_REG 0x19
348 #define MASTER_CONTROL 0x10
349 #define DMA_DIRECTION 0x08
350 #define CTEST7_REG 0x1B
351 #define BURST_DISABLE 0x80 /* 710 only */
352 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
353 #define DFP 0x08
354 #define EVP 0x04
355 #define DIFF 0x01
356 #define CTEST6_REG 0x1A
357 #define TEMP_REG 0x1C
358 #define DFIFO_REG 0x20
359 #define FLUSH_DMA_FIFO 0x80
360 #define CLR_FIFO 0x40
361 #define ISTAT_REG 0x21
362 #define ABORT_OPERATION 0x80
363 #define SOFTWARE_RESET_710 0x40
364 #define DMA_INT_PENDING 0x01
365 #define SCSI_INT_PENDING 0x02
366 #define CONNECTED 0x08
367 #define CTEST8_REG 0x22
368 #define LAST_DIS_ENBL 0x01
369 #define SHORTEN_FILTERING 0x04
370 #define ENABLE_ACTIVE_NEGATION 0x10
371 #define GENERATE_RECEIVE_PARITY 0x20
372 #define CLR_FIFO_710 0x04
373 #define FLUSH_DMA_FIFO_710 0x08
374 #define CTEST9_REG 0x23
375 #define DBC_REG 0x24
376 #define DCMD_REG 0x27
377 #define DNAD_REG 0x28
378 #define DIEN_REG 0x39
379 #define BUS_FAULT 0x20
380 #define ABORT_INT 0x10
381 #define INT_INST_INT 0x04
382 #define WD_INT 0x02
383 #define ILGL_INST_INT 0x01
384 #define DCNTL_REG 0x3B
385 #define SOFTWARE_RESET 0x01
386 #define COMPAT_700_MODE 0x01
387 #define SCRPTS_16BITS 0x20
388 #define ASYNC_DIV_2_0 0x00
389 #define ASYNC_DIV_1_5 0x40
390 #define ASYNC_DIV_1_0 0x80
391 #define ASYNC_DIV_3_0 0xc0
392 #define DMODE_710_REG 0x38
393 #define DMODE_700_REG 0x34
394 #define BURST_LENGTH_1 0x00
395 #define BURST_LENGTH_2 0x40
396 #define BURST_LENGTH_4 0x80
397 #define BURST_LENGTH_8 0xC0
398 #define DMODE_FC1 0x10
399 #define DMODE_FC2 0x20
400 #define BW16 32
401 #define MODE_286 16
402 #define IO_XFER 8
403 #define FIXED_ADDR 4
404
405 #define DSP_REG 0x2C
406 #define DSPS_REG 0x30
407
408 /* Parameters to begin SDTR negotiations. Empirically, I find that
409 * the 53c700-66 cannot handle an offset >8, so don't change this */
410 #define NCR_700_MAX_OFFSET 8
411 /* Was hoping the max offset would be greater for the 710, but
412 * empirically it seems to be 8 also */
413 #define NCR_710_MAX_OFFSET 8
414 #define NCR_700_MIN_XFERP 1
415 #define NCR_710_MIN_XFERP 0
416 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
417
418 #define script_patch_32(dev, script, symbol, value) \
419 { \
420 int i; \
421 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
422 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
423 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
424 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
425 DEBUG((" script, patching %s at %d to 0x%lx\n", \
426 #symbol, A_##symbol##_used[i], (value))); \
427 } \
428 }
429
430 #define script_patch_32_abs(dev, script, symbol, value) \
431 { \
432 int i; \
433 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
434 (script)[A_##symbol##_used[i]] = bS_to_host(value); \
435 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
436 DEBUG((" script, patching %s at %d to 0x%lx\n", \
437 #symbol, A_##symbol##_used[i], (value))); \
438 } \
439 }
440
441 /* Used for patching the SCSI ID in the SELECT instruction */
442 #define script_patch_ID(dev, script, symbol, value) \
443 { \
444 int i; \
445 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
446 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
447 val &= 0xff00ffff; \
448 val |= ((value) & 0xff) << 16; \
449 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
450 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
451 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
452 #symbol, A_##symbol##_used[i], val)); \
453 } \
454 }
455
456 #define script_patch_16(dev, script, symbol, value) \
457 { \
458 int i; \
459 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
460 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
461 val &= 0xffff0000; \
462 val |= ((value) & 0xffff); \
463 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
464 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
465 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
466 #symbol, A_##symbol##_used[i], val)); \
467 } \
468 }
469
470
471 static inline __u8
472 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
473 {
474 const struct NCR_700_Host_Parameters *hostdata
475 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
476
477 return ioread8(hostdata->base + (reg^bE));
478 }
479
480 static inline __u32
481 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
482 {
483 const struct NCR_700_Host_Parameters *hostdata
484 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
485 __u32 value = bEBus ? ioread32be(hostdata->base + reg) :
486 ioread32(hostdata->base + reg);
487 #if 1
488 /* sanity check the register */
489 BUG_ON((reg & 0x3) != 0);
490 #endif
491
492 return value;
493 }
494
495 static inline void
496 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
497 {
498 const struct NCR_700_Host_Parameters *hostdata
499 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
500
501 iowrite8(value, hostdata->base + (reg^bE));
502 }
503
504 static inline void
505 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
506 {
507 const struct NCR_700_Host_Parameters *hostdata
508 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
509
510 #if 1
511 /* sanity check the register */
512 BUG_ON((reg & 0x3) != 0);
513 #endif
514
515 bEBus ? iowrite32be(value, hostdata->base + reg):
516 iowrite32(value, hostdata->base + reg);
517 }
518
519 #endif
Tomato firmware and modifications.