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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / pci / probe.c
blobe015cedf765644e36cb484485f1cd97d58c90834
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 /*
26 * Some device drivers need know if pci is initiated.
27 * Basically, we think pci is not initiated when there
28 * is no device in list of pci_devices.
29 */
30 int no_pci_devices(void)
31 {
32 return list_empty(&pci_devices);
33 }
34
35 EXPORT_SYMBOL(no_pci_devices);
36
37 #ifdef HAVE_PCI_LEGACY
38 /**
39 * pci_create_legacy_files - create legacy I/O port and memory files
40 * @b: bus to create files under
41 *
42 * Some platforms allow access to legacy I/O port and ISA memory space on
43 * a per-bus basis. This routine creates the files and ties them into
44 * their associated read, write and mmap files from pci-sysfs.c
45 */
46 static void pci_create_legacy_files(struct pci_bus *b)
47 {
48 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
49 GFP_ATOMIC);
50 if (b->legacy_io) {
51 b->legacy_io->attr.name = "legacy_io";
52 b->legacy_io->size = 0xffff;
53 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
54 b->legacy_io->attr.owner = THIS_MODULE;
55 b->legacy_io->read = pci_read_legacy_io;
56 b->legacy_io->write = pci_write_legacy_io;
57 class_device_create_bin_file(&b->class_dev, b->legacy_io);
58
59 /* Allocated above after the legacy_io struct */
60 b->legacy_mem = b->legacy_io + 1;
61 b->legacy_mem->attr.name = "legacy_mem";
62 b->legacy_mem->size = 1024*1024;
63 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_mem->attr.owner = THIS_MODULE;
65 b->legacy_mem->mmap = pci_mmap_legacy_mem;
66 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
67 }
68 }
69
70 void pci_remove_legacy_files(struct pci_bus *b)
71 {
72 if (b->legacy_io) {
73 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
74 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
75 kfree(b->legacy_io); /* both are allocated here */
76 }
77 }
78 #else /* !HAVE_PCI_LEGACY */
79 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
80 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
81 #endif /* HAVE_PCI_LEGACY */
82
83 /*
84 * PCI Bus Class Devices
85 */
86 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
87 char *buf)
88 {
89 int ret;
90 cpumask_t cpumask;
91
92 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
93 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
94 if (ret < PAGE_SIZE)
95 buf[ret++] = '\n';
96 return ret;
97 }
98 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
99
100 /*
101 * PCI Bus Class
102 */
103 static void release_pcibus_dev(struct class_device *class_dev)
104 {
105 struct pci_bus *pci_bus = to_pci_bus(class_dev);
106
107 if (pci_bus->bridge)
108 put_device(pci_bus->bridge);
109 kfree(pci_bus);
110 }
111
112 static struct class pcibus_class = {
113 .name = "pci_bus",
114 .release = &release_pcibus_dev,
115 };
116
117 static int __init pcibus_class_init(void)
118 {
119 return class_register(&pcibus_class);
120 }
121 postcore_initcall(pcibus_class_init);
122
123 /*
124 * Translate the low bits of the PCI base
125 * to the resource type
126 */
127 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
128 {
129 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
130 return IORESOURCE_IO;
131
132 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
133 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
134
135 return IORESOURCE_MEM;
136 }
137
138 /*
139 * Find the extent of a PCI decode..
140 */
141 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
142 {
143 u32 size = mask & maxbase; /* Find the significant bits */
144 if (!size)
145 return 0;
146
147 /* Get the lowest of them to find the decode size, and
148 from that the extent. */
149 size = (size & ~(size-1)) - 1;
150
151 /* base == maxbase can be valid only if the BAR has
152 already been programmed with all 1s. */
153 if (base == maxbase && ((base | size) & mask) != mask)
154 return 0;
155
156 return size;
157 }
158
159 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
160 {
161 u64 size = mask & maxbase; /* Find the significant bits */
162 if (!size)
163 return 0;
164
165 /* Get the lowest of them to find the decode size, and
166 from that the extent. */
167 size = (size & ~(size-1)) - 1;
168
169 /* base == maxbase can be valid only if the BAR has
170 already been programmed with all 1s. */
171 if (base == maxbase && ((base | size) & mask) != mask)
172 return 0;
173
174 return size;
175 }
176
177 static inline int is_64bit_memory(u32 mask)
178 {
179 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
180 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
181 return 1;
182 return 0;
183 }
184
185 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
186 {
187 unsigned int pos, reg, next;
188 u32 l, sz;
189 struct resource *res;
190
191 for(pos=0; pos<howmany; pos = next) {
192 u64 l64;
193 u64 sz64;
194 u32 raw_sz;
195
196 next = pos+1;
197 res = &dev->resource[pos];
198 res->name = pci_name(dev);
199 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
200 pci_read_config_dword(dev, reg, &l);
201 pci_write_config_dword(dev, reg, ~0);
202 pci_read_config_dword(dev, reg, &sz);
203 pci_write_config_dword(dev, reg, l);
204 if (!sz || sz == 0xffffffff)
205 continue;
206 if (l == 0xffffffff)
207 l = 0;
208 raw_sz = sz;
209 if ((l & PCI_BASE_ADDRESS_SPACE) ==
210 PCI_BASE_ADDRESS_SPACE_MEMORY) {
211 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
212 /*
213 * For 64bit prefetchable memory sz could be 0, if the
214 * real size is bigger than 4G, so we need to check
215 * szhi for that.
216 */
217 if (!is_64bit_memory(l) && !sz)
218 continue;
219 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
220 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
221 } else {
222 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
223 if (!sz)
224 continue;
225 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
226 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
227 }
228 res->end = res->start + (unsigned long) sz;
229 res->flags |= pci_calc_resource_flags(l);
230 if (is_64bit_memory(l)) {
231 u32 szhi, lhi;
232
233 pci_read_config_dword(dev, reg+4, &lhi);
234 pci_write_config_dword(dev, reg+4, ~0);
235 pci_read_config_dword(dev, reg+4, &szhi);
236 pci_write_config_dword(dev, reg+4, lhi);
237 sz64 = ((u64)szhi << 32) | raw_sz;
238 l64 = ((u64)lhi << 32) | l;
239 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
240 next++;
241 #if BITS_PER_LONG == 64
242 if (!sz64) {
243 res->start = 0;
244 res->end = 0;
245 res->flags = 0;
246 continue;
247 }
248 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
249 res->end = res->start + sz64;
250 #else
251 if (sz64 > 0x100000000ULL) {
252 printk(KERN_ERR "PCI: Unable to handle 64-bit "
253 "BAR for device %s\n", pci_name(dev));
254 res->start = 0;
255 res->flags = 0;
256 } else if (lhi) {
257 /* 64-bit wide address, treat as disabled */
258 pci_write_config_dword(dev, reg,
259 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
260 pci_write_config_dword(dev, reg+4, 0);
261 res->start = 0;
262 res->end = sz;
263 }
264 #endif
265 }
266 }
267 if (rom) {
268 dev->rom_base_reg = rom;
269 res = &dev->resource[PCI_ROM_RESOURCE];
270 res->name = pci_name(dev);
271 pci_read_config_dword(dev, rom, &l);
272 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
273 pci_read_config_dword(dev, rom, &sz);
274 pci_write_config_dword(dev, rom, l);
275 if (l == 0xffffffff)
276 l = 0;
277 if (sz && sz != 0xffffffff) {
278 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
279 if (sz) {
280 res->flags = (l & IORESOURCE_ROM_ENABLE) |
281 IORESOURCE_MEM | IORESOURCE_PREFETCH |
282 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
283 res->start = l & PCI_ROM_ADDRESS_MASK;
284 res->end = res->start + (unsigned long) sz;
285 }
286 }
287 }
288 }
289
290 void __devinit pci_read_bridge_bases(struct pci_bus *child)
291 {
292 struct pci_dev *dev = child->self;
293 u8 io_base_lo, io_limit_lo;
294 u16 mem_base_lo, mem_limit_lo;
295 unsigned long base, limit;
296 struct resource *res;
297 int i;
298
299 if (!dev) /* It's a host bus, nothing to read */
300 return;
301
302 if (dev->transparent) {
303 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
304 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
305 child->resource[i] = child->parent->resource[i - 3];
306 }
307
308 for(i=0; i<3; i++)
309 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
310
311 res = child->resource[0];
312 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
313 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
314 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
315 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
316
317 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
318 u16 io_base_hi, io_limit_hi;
319 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
320 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
321 base |= (io_base_hi << 16);
322 limit |= (io_limit_hi << 16);
323 }
324
325 if (base <= limit) {
326 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
327 if (!res->start)
328 res->start = base;
329 if (!res->end)
330 res->end = limit + 0xfff;
331 }
332
333 res = child->resource[1];
334 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
335 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
336 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
337 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
338 if (base <= limit) {
339 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
340 res->start = base;
341 res->end = limit + 0xfffff;
342 }
343
344 res = child->resource[2];
345 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
346 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
347 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
348 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
349
350 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
351 u32 mem_base_hi, mem_limit_hi;
352 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
353 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
354
355 /*
356 * Some bridges set the base > limit by default, and some
357 * (broken) BIOSes do not initialize them. If we find
358 * this, just assume they are not being used.
359 */
360 if (mem_base_hi <= mem_limit_hi) {
361 #if BITS_PER_LONG == 64
362 base |= ((long) mem_base_hi) << 32;
363 limit |= ((long) mem_limit_hi) << 32;
364 #else
365 if (mem_base_hi || mem_limit_hi) {
366 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
367 return;
368 }
369 #endif
370 }
371 }
372 if (base <= limit) {
373 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
374 res->start = base;
375 res->end = limit + 0xfffff;
376 }
377 }
378
379 static struct pci_bus * pci_alloc_bus(void)
380 {
381 struct pci_bus *b;
382
383 b = kzalloc(sizeof(*b), GFP_KERNEL);
384 if (b) {
385 INIT_LIST_HEAD(&b->node);
386 INIT_LIST_HEAD(&b->children);
387 INIT_LIST_HEAD(&b->devices);
388 }
389 return b;
390 }
391
392 static struct pci_bus * __devinit
393 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
394 {
395 struct pci_bus *child;
396 int i;
397 int retval;
398
399 /*
400 * Allocate a new bus, and inherit stuff from the parent..
401 */
402 child = pci_alloc_bus();
403 if (!child)
404 return NULL;
405
406 child->self = bridge;
407 child->parent = parent;
408 child->ops = parent->ops;
409 child->sysdata = parent->sysdata;
410 child->bus_flags = parent->bus_flags;
411 child->bridge = get_device(&bridge->dev);
412
413 child->class_dev.class = &pcibus_class;
414 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
415 retval = class_device_register(&child->class_dev);
416 if (retval)
417 goto error_register;
418 retval = class_device_create_file(&child->class_dev,
419 &class_device_attr_cpuaffinity);
420 if (retval)
421 goto error_file_create;
422
423 /*
424 * Set up the primary, secondary and subordinate
425 * bus numbers.
426 */
427 child->number = child->secondary = busnr;
428 child->primary = parent->secondary;
429 child->subordinate = 0xff;
430
431 /* Set up default resource pointers and names.. */
432 for (i = 0; i < 4; i++) {
433 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
434 child->resource[i]->name = child->name;
435 }
436 bridge->subordinate = child;
437
438 return child;
439
440 error_file_create:
441 class_device_unregister(&child->class_dev);
442 error_register:
443 kfree(child);
444 return NULL;
445 }
446
447 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
448 {
449 struct pci_bus *child;
450
451 child = pci_alloc_child_bus(parent, dev, busnr);
452 if (child) {
453 down_write(&pci_bus_sem);
454 list_add_tail(&child->node, &parent->children);
455 up_write(&pci_bus_sem);
456 }
457 return child;
458 }
459
460 static void pci_enable_crs(struct pci_dev *dev)
461 {
462 u16 cap, rpctl;
463 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
464 if (!rpcap)
465 return;
466
467 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
468 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
469 return;
470
471 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
472 rpctl |= PCI_EXP_RTCTL_CRSSVE;
473 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
474 }
475
476 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
477 {
478 struct pci_bus *parent = child->parent;
479
480 /* Attempts to fix that up are really dangerous unless
481 we're going to re-assign all bus numbers. */
482 if (!pcibios_assign_all_busses())
483 return;
484
485 while (parent->parent && parent->subordinate < max) {
486 parent->subordinate = max;
487 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
488 parent = parent->parent;
489 }
490 }
491
492 unsigned int pci_scan_child_bus(struct pci_bus *bus);
493
494 /*
495 * If it's a bridge, configure it and scan the bus behind it.
496 * For CardBus bridges, we don't scan behind as the devices will
497 * be handled by the bridge driver itself.
498 *
499 * We need to process bridges in two passes -- first we scan those
500 * already configured by the BIOS and after we are done with all of
501 * them, we proceed to assigning numbers to the remaining buses in
502 * order to avoid overlaps between old and new bus numbers.
503 */
504 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
505 {
506 struct pci_bus *child;
507 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
508 u32 buses, i, j = 0;
509 u16 bctl;
510
511 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
512
513 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
514 pci_name(dev), buses & 0xffffff, pass);
515
516 /* Disable MasterAbortMode during probing to avoid reporting
517 of bus errors (in some architectures) */
518 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
519 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
520 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
521
522 pci_enable_crs(dev);
523
524 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
525 unsigned int cmax, busnr;
526 /*
527 * Bus already configured by firmware, process it in the first
528 * pass and just note the configuration.
529 */
530 if (pass)
531 goto out;
532 busnr = (buses >> 8) & 0xFF;
533
534 /*
535 * If we already got to this bus through a different bridge,
536 * ignore it. This can happen with the i450NX chipset.
537 */
538 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
539 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
540 pci_domain_nr(bus), busnr);
541 goto out;
542 }
543
544 child = pci_add_new_bus(bus, dev, busnr);
545 if (!child)
546 goto out;
547 child->primary = buses & 0xFF;
548 child->subordinate = (buses >> 16) & 0xFF;
549 child->bridge_ctl = bctl;
550
551 cmax = pci_scan_child_bus(child);
552 if (cmax > max)
553 max = cmax;
554 if (child->subordinate > max)
555 max = child->subordinate;
556 } else {
557 /*
558 * We need to assign a number to this bus which we always
559 * do in the second pass.
560 */
561 if (!pass) {
562 if (pcibios_assign_all_busses())
563 /* Temporarily disable forwarding of the
564 configuration cycles on all bridges in
565 this bus segment to avoid possible
566 conflicts in the second pass between two
567 bridges programmed with overlapping
568 bus ranges. */
569 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
570 buses & ~0xffffff);
571 goto out;
572 }
573
574 /* Clear errors */
575 pci_write_config_word(dev, PCI_STATUS, 0xffff);
576
577 /* Prevent assigning a bus number that already exists.
578 * This can happen when a bridge is hot-plugged */
579 if (pci_find_bus(pci_domain_nr(bus), max+1))
580 goto out;
581 child = pci_add_new_bus(bus, dev, ++max);
582 buses = (buses & 0xff000000)
583 | ((unsigned int)(child->primary) << 0)
584 | ((unsigned int)(child->secondary) << 8)
585 | ((unsigned int)(child->subordinate) << 16);
586
587 /*
588 * yenta.c forces a secondary latency timer of 176.
589 * Copy that behaviour here.
590 */
591 if (is_cardbus) {
592 buses &= ~0xff000000;
593 buses |= CARDBUS_LATENCY_TIMER << 24;
594 }
595
596 /*
597 * We need to blast all three values with a single write.
598 */
599 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
600
601 if (!is_cardbus) {
602 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
603 /*
604 * Adjust subordinate busnr in parent buses.
605 * We do this before scanning for children because
606 * some devices may not be detected if the bios
607 * was lazy.
608 */
609 pci_fixup_parent_subordinate_busnr(child, max);
610 /* Now we can scan all subordinate buses... */
611 max = pci_scan_child_bus(child);
612 /*
613 * now fix it up again since we have found
614 * the real value of max.
615 */
616 pci_fixup_parent_subordinate_busnr(child, max);
617 } else {
618 /*
619 * For CardBus bridges, we leave 4 bus numbers
620 * as cards with a PCI-to-PCI bridge can be
621 * inserted later.
622 */
623 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
624 struct pci_bus *parent = bus;
625 if (pci_find_bus(pci_domain_nr(bus),
626 max+i+1))
627 break;
628 while (parent->parent) {
629 if ((!pcibios_assign_all_busses()) &&
630 (parent->subordinate > max) &&
631 (parent->subordinate <= max+i)) {
632 j = 1;
633 }
634 parent = parent->parent;
635 }
636 if (j) {
637 /*
638 * Often, there are two cardbus bridges
639 * -- try to leave one valid bus number
640 * for each one.
641 */
642 i /= 2;
643 break;
644 }
645 }
646 max += i;
647 pci_fixup_parent_subordinate_busnr(child, max);
648 }
649 /*
650 * Set the subordinate bus number to its real value.
651 */
652 child->subordinate = max;
653 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
654 }
655
656 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
657
658 /* Has only triggered on CardBus, fixup is in yenta_socket */
659 while (bus->parent) {
660 if ((child->subordinate > bus->subordinate) ||
661 (child->number > bus->subordinate) ||
662 (child->number < bus->number) ||
663 (child->subordinate < bus->number)) {
664 pr_debug("PCI: Bus #%02x (-#%02x) is %s"
665 "hidden behind%s bridge #%02x (-#%02x)\n",
666 child->number, child->subordinate,
667 (bus->number > child->subordinate &&
668 bus->subordinate < child->number) ?
669 "wholly " : " partially",
670 bus->self->transparent ? " transparent" : " ",
671 bus->number, bus->subordinate);
672 }
673 bus = bus->parent;
674 }
675
676 out:
677 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
678
679 return max;
680 }
681
682 /*
683 * Read interrupt line and base address registers.
684 * The architecture-dependent code can tweak these, of course.
685 */
686 static void pci_read_irq(struct pci_dev *dev)
687 {
688 unsigned char irq;
689
690 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
691 dev->pin = irq;
692 if (irq)
693 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
694 dev->irq = irq;
695 }
696
697 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
698
699 /**
700 * pci_setup_device - fill in class and map information of a device
701 * @dev: the device structure to fill
702 *
703 * Initialize the device structure with information about the device's
704 * vendor,class,memory and IO-space addresses,IRQ lines etc.
705 * Called at initialisation of the PCI subsystem and by CardBus services.
706 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
707 * or CardBus).
708 */
709 static int pci_setup_device(struct pci_dev * dev)
710 {
711 u32 class;
712
713 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
714 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
715
716 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
717 class >>= 8; /* upper 3 bytes */
718 dev->class = class;
719 class >>= 8;
720
721 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
722 dev->vendor, dev->device, class, dev->hdr_type);
723
724 /* "Unknown power state" */
725 dev->current_state = PCI_UNKNOWN;
726
727 /* Early fixups, before probing the BARs */
728 pci_fixup_device(pci_fixup_early, dev);
729 class = dev->class >> 8;
730
731 switch (dev->hdr_type) { /* header type */
732 case PCI_HEADER_TYPE_NORMAL: /* standard header */
733 if (class == PCI_CLASS_BRIDGE_PCI)
734 goto bad;
735 pci_read_irq(dev);
736 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
737 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
738 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
739
740 /*
741 * Do the ugly legacy mode stuff here rather than broken chip
742 * quirk code. Legacy mode ATA controllers have fixed
743 * addresses. These are not always echoed in BAR0-3, and
744 * BAR0-3 in a few cases contain junk!
745 */
746 if (class == PCI_CLASS_STORAGE_IDE) {
747 u8 progif;
748 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
749 if ((progif & 1) == 0) {
750 dev->resource[0].start = 0x1F0;
751 dev->resource[0].end = 0x1F7;
752 dev->resource[0].flags = LEGACY_IO_RESOURCE;
753 dev->resource[1].start = 0x3F6;
754 dev->resource[1].end = 0x3F6;
755 dev->resource[1].flags = LEGACY_IO_RESOURCE;
756 }
757 if ((progif & 4) == 0) {
758 dev->resource[2].start = 0x170;
759 dev->resource[2].end = 0x177;
760 dev->resource[2].flags = LEGACY_IO_RESOURCE;
761 dev->resource[3].start = 0x376;
762 dev->resource[3].end = 0x376;
763 dev->resource[3].flags = LEGACY_IO_RESOURCE;
764 }
765 }
766 break;
767
768 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
769 if (class != PCI_CLASS_BRIDGE_PCI)
770 goto bad;
771 /* The PCI-to-PCI bridge spec requires that subtractive
772 decoding (i.e. transparent) bridge must have programming
773 interface code of 0x01. */
774 pci_read_irq(dev);
775 dev->transparent = ((dev->class & 0xff) == 1);
776 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
777 break;
778
779 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
780 if (class != PCI_CLASS_BRIDGE_CARDBUS)
781 goto bad;
782 pci_read_irq(dev);
783 pci_read_bases(dev, 1, 0);
784 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
785 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
786 break;
787
788 default: /* unknown header */
789 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
790 pci_name(dev), dev->hdr_type);
791 return -1;
792
793 bad:
794 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
795 pci_name(dev), class, dev->hdr_type);
796 dev->class = PCI_CLASS_NOT_DEFINED;
797 }
798
799 /* We found a fine healthy device, go go go... */
800 return 0;
801 }
802
803 /**
804 * pci_release_dev - free a pci device structure when all users of it are finished.
805 * @dev: device that's been disconnected
806 *
807 * Will be called only by the device core when all users of this pci device are
808 * done.
809 */
810 static void pci_release_dev(struct device *dev)
811 {
812 struct pci_dev *pci_dev;
813
814 pci_dev = to_pci_dev(dev);
815 kfree(pci_dev);
816 }
817
818 /**
819 * pci_cfg_space_size - get the configuration space size of the PCI device.
820 * @dev: PCI device
821 *
822 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
823 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
824 * access it. Maybe we don't have a way to generate extended config space
825 * accesses, or the device is behind a reverse Express bridge. So we try
826 * reading the dword at 0x100 which must either be 0 or a valid extended
827 * capability header.
828 */
829 int pci_cfg_space_size(struct pci_dev *dev)
830 {
831 int pos;
832 u32 status;
833
834 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
835 if (!pos) {
836 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
837 if (!pos)
838 goto fail;
839
840 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
841 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
842 goto fail;
843 }
844
845 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
846 goto fail;
847 if (status == 0xffffffff)
848 goto fail;
849
850 return PCI_CFG_SPACE_EXP_SIZE;
851
852 fail:
853 return PCI_CFG_SPACE_SIZE;
854 }
855
856 static void pci_release_bus_bridge_dev(struct device *dev)
857 {
858 kfree(dev);
859 }
860
861 struct pci_dev *alloc_pci_dev(void)
862 {
863 struct pci_dev *dev;
864
865 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
866 if (!dev)
867 return NULL;
868
869 INIT_LIST_HEAD(&dev->global_list);
870 INIT_LIST_HEAD(&dev->bus_list);
871
872 pci_msi_init_pci_dev(dev);
873
874 return dev;
875 }
876 EXPORT_SYMBOL(alloc_pci_dev);
877
878 /*
879 * Read the config data for a PCI device, sanity-check it
880 * and fill in the dev structure...
881 */
882 static struct pci_dev * __devinit
883 pci_scan_device(struct pci_bus *bus, int devfn)
884 {
885 struct pci_dev *dev;
886 u32 l;
887 u8 hdr_type;
888 int delay = 1;
889
890 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
891 return NULL;
892
893 /* some broken boards return 0 or ~0 if a slot is empty: */
894 if (l == 0xffffffff || l == 0x00000000 ||
895 l == 0x0000ffff || l == 0xffff0000)
896 return NULL;
897
898 /* Configuration request Retry Status */
899 while (l == 0xffff0001) {
900 msleep(delay);
901 delay *= 2;
902 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
903 return NULL;
904 /* Card hasn't responded in 60 seconds? Must be stuck. */
905 if (delay > 60 * 1000) {
906 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
907 "responding\n", pci_domain_nr(bus),
908 bus->number, PCI_SLOT(devfn),
909 PCI_FUNC(devfn));
910 return NULL;
911 }
912 }
913
914 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
915 return NULL;
916
917 dev = alloc_pci_dev();
918 if (!dev)
919 return NULL;
920
921 dev->bus = bus;
922 dev->sysdata = bus->sysdata;
923 dev->dev.parent = bus->bridge;
924 dev->dev.bus = &pci_bus_type;
925 dev->devfn = devfn;
926 dev->hdr_type = hdr_type & 0x7f;
927 dev->multifunction = !!(hdr_type & 0x80);
928 dev->vendor = l & 0xffff;
929 dev->device = (l >> 16) & 0xffff;
930 dev->cfg_size = pci_cfg_space_size(dev);
931 dev->error_state = pci_channel_io_normal;
932
933 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
934 set this higher, assuming the system even supports it. */
935 dev->dma_mask = 0xffffffff;
936 if (pci_setup_device(dev) < 0) {
937 kfree(dev);
938 return NULL;
939 }
940
941 return dev;
942 }
943
944 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
945 {
946 device_initialize(&dev->dev);
947 dev->dev.release = pci_release_dev;
948 pci_dev_get(dev);
949
950 set_dev_node(&dev->dev, pcibus_to_node(bus));
951 dev->dev.dma_mask = &dev->dma_mask;
952 dev->dev.coherent_dma_mask = 0xffffffffull;
953
954 /* Fix up broken headers */
955 pci_fixup_device(pci_fixup_header, dev);
956
957 /*
958 * Add the device to our list of discovered devices
959 * and the bus list for fixup functions, etc.
960 */
961 INIT_LIST_HEAD(&dev->global_list);
962 down_write(&pci_bus_sem);
963 list_add_tail(&dev->bus_list, &bus->devices);
964 up_write(&pci_bus_sem);
965 }
966
967 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
968 {
969 struct pci_dev *dev;
970
971 dev = pci_scan_device(bus, devfn);
972 if (!dev)
973 return NULL;
974
975 pci_device_add(dev, bus);
976
977 return dev;
978 }
979
980 /**
981 * pci_scan_slot - scan a PCI slot on a bus for devices.
982 * @bus: PCI bus to scan
983 * @devfn: slot number to scan (must have zero function.)
984 *
985 * Scan a PCI slot on the specified PCI bus for devices, adding
986 * discovered devices to the @bus->devices list. New devices
987 * will have an empty dev->global_list head.
988 */
989 int pci_scan_slot(struct pci_bus *bus, int devfn)
990 {
991 int func, nr = 0;
992 int scan_all_fns;
993
994 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
995
996 for (func = 0; func < 8; func++, devfn++) {
997 struct pci_dev *dev;
998
999 dev = pci_scan_single_device(bus, devfn);
1000 if (dev) {
1001 nr++;
1002
1003 /*
1004 * If this is a single function device,
1005 * don't scan past the first function.
1006 */
1007 if (!dev->multifunction) {
1008 if (func > 0) {
1009 dev->multifunction = 1;
1010 } else {
1011 break;
1012 }
1013 }
1014 } else {
1015 if (func == 0 && !scan_all_fns)
1016 break;
1017 }
1018 }
1019 return nr;
1020 }
1021
1022 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1023 {
1024 unsigned int devfn, pass, max = bus->secondary;
1025 struct pci_dev *dev;
1026
1027 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1028
1029 /* Go find them, Rover! */
1030 for (devfn = 0; devfn < 0x100; devfn += 8)
1031 pci_scan_slot(bus, devfn);
1032
1033 /*
1034 * After performing arch-dependent fixup of the bus, look behind
1035 * all PCI-to-PCI bridges on this bus.
1036 */
1037 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1038 pcibios_fixup_bus(bus);
1039 for (pass=0; pass < 2; pass++)
1040 list_for_each_entry(dev, &bus->devices, bus_list) {
1041 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1042 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1043 max = pci_scan_bridge(bus, dev, max, pass);
1044 }
1045
1046 /*
1047 * We've scanned the bus and so we know all about what's on
1048 * the other side of any bridges that may be on this bus plus
1049 * any devices.
1050 *
1051 * Return how far we've got finding sub-buses.
1052 */
1053 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1054 pci_domain_nr(bus), bus->number, max);
1055 return max;
1056 }
1057
1058 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1059 {
1060 unsigned int max;
1061
1062 max = pci_scan_child_bus(bus);
1063
1064 /*
1065 * Make the discovered devices available.
1066 */
1067 pci_bus_add_devices(bus);
1068
1069 return max;
1070 }
1071
1072 struct pci_bus * pci_create_bus(struct device *parent,
1073 int bus, struct pci_ops *ops, void *sysdata)
1074 {
1075 int error;
1076 struct pci_bus *b;
1077 struct device *dev;
1078
1079 b = pci_alloc_bus();
1080 if (!b)
1081 return NULL;
1082
1083 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1084 if (!dev){
1085 kfree(b);
1086 return NULL;
1087 }
1088
1089 b->sysdata = sysdata;
1090 b->ops = ops;
1091
1092 if (pci_find_bus(pci_domain_nr(b), bus)) {
1093 /* If we already got to this bus through a different bridge, ignore it */
1094 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1095 goto err_out;
1096 }
1097
1098 down_write(&pci_bus_sem);
1099 list_add_tail(&b->node, &pci_root_buses);
1100 up_write(&pci_bus_sem);
1101
1102 memset(dev, 0, sizeof(*dev));
1103 dev->parent = parent;
1104 dev->release = pci_release_bus_bridge_dev;
1105 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1106 error = device_register(dev);
1107 if (error)
1108 goto dev_reg_err;
1109 b->bridge = get_device(dev);
1110
1111 b->class_dev.class = &pcibus_class;
1112 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1113 error = class_device_register(&b->class_dev);
1114 if (error)
1115 goto class_dev_reg_err;
1116 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1117 if (error)
1118 goto class_dev_create_file_err;
1119
1120 /* Create legacy_io and legacy_mem files for this bus */
1121 pci_create_legacy_files(b);
1122
1123 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1124 if (error)
1125 goto sys_create_link_err;
1126
1127 b->number = b->secondary = bus;
1128 b->resource[0] = &ioport_resource;
1129 b->resource[1] = &iomem_resource;
1130
1131 return b;
1132
1133 sys_create_link_err:
1134 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1135 class_dev_create_file_err:
1136 class_device_unregister(&b->class_dev);
1137 class_dev_reg_err:
1138 device_unregister(dev);
1139 dev_reg_err:
1140 down_write(&pci_bus_sem);
1141 list_del(&b->node);
1142 up_write(&pci_bus_sem);
1143 err_out:
1144 kfree(dev);
1145 kfree(b);
1146 return NULL;
1147 }
1148 EXPORT_SYMBOL_GPL(pci_create_bus);
1149
1150 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1151 int bus, struct pci_ops *ops, void *sysdata)
1152 {
1153 struct pci_bus *b;
1154
1155 b = pci_create_bus(parent, bus, ops, sysdata);
1156 if (b)
1157 b->subordinate = pci_scan_child_bus(b);
1158 return b;
1159 }
1160 EXPORT_SYMBOL(pci_scan_bus_parented);
1161
1162 #ifdef CONFIG_HOTPLUG
1163 EXPORT_SYMBOL(pci_add_new_bus);
1164 EXPORT_SYMBOL(pci_do_scan_bus);
1165 EXPORT_SYMBOL(pci_scan_slot);
1166 EXPORT_SYMBOL(pci_scan_bridge);
1167 EXPORT_SYMBOL(pci_scan_single_device);
1168 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1169 #endif
1170
1171 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1172 {
1173 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1174 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1175
1176 if (a->bus->number < b->bus->number) return -1;
1177 else if (a->bus->number > b->bus->number) return 1;
1178
1179 if (a->devfn < b->devfn) return -1;
1180 else if (a->devfn > b->devfn) return 1;
1181
1182 return 0;
1183 }
1184
1185 /*
1186 * Yes, this forcably breaks the klist abstraction temporarily. It
1187 * just wants to sort the klist, not change reference counts and
1188 * take/drop locks rapidly in the process. It does all this while
1189 * holding the lock for the list, so objects can't otherwise be
1190 * added/removed while we're swizzling.
1191 */
1192 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1193 {
1194 struct list_head *pos;
1195 struct klist_node *n;
1196 struct device *dev;
1197 struct pci_dev *b;
1198
1199 list_for_each(pos, list) {
1200 n = container_of(pos, struct klist_node, n_node);
1201 dev = container_of(n, struct device, knode_bus);
1202 b = to_pci_dev(dev);
1203 if (pci_sort_bf_cmp(a, b) <= 0) {
1204 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1205 return;
1206 }
1207 }
1208 list_move_tail(&a->dev.knode_bus.n_node, list);
1209 }
1210
1211 static void __init pci_sort_breadthfirst_klist(void)
1212 {
1213 LIST_HEAD(sorted_devices);
1214 struct list_head *pos, *tmp;
1215 struct klist_node *n;
1216 struct device *dev;
1217 struct pci_dev *pdev;
1218
1219 spin_lock(&pci_bus_type.klist_devices.k_lock);
1220 list_for_each_safe(pos, tmp, &pci_bus_type.klist_devices.k_list) {
1221 n = container_of(pos, struct klist_node, n_node);
1222 dev = container_of(n, struct device, knode_bus);
1223 pdev = to_pci_dev(dev);
1224 pci_insertion_sort_klist(pdev, &sorted_devices);
1225 }
1226 list_splice(&sorted_devices, &pci_bus_type.klist_devices.k_list);
1227 spin_unlock(&pci_bus_type.klist_devices.k_lock);
1228 }
1229
1230 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1231 {
1232 struct pci_dev *b;
1233
1234 list_for_each_entry(b, list, global_list) {
1235 if (pci_sort_bf_cmp(a, b) <= 0) {
1236 list_move_tail(&a->global_list, &b->global_list);
1237 return;
1238 }
1239 }
1240 list_move_tail(&a->global_list, list);
1241 }
1242
1243 static void __init pci_sort_breadthfirst_devices(void)
1244 {
1245 LIST_HEAD(sorted_devices);
1246 struct pci_dev *dev, *tmp;
1247
1248 down_write(&pci_bus_sem);
1249 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1250 pci_insertion_sort_devices(dev, &sorted_devices);
1251 }
1252 list_splice(&sorted_devices, &pci_devices);
1253 up_write(&pci_bus_sem);
1254 }
1255
1256 void __init pci_sort_breadthfirst(void)
1257 {
1258 pci_sort_breadthfirst_devices();
1259 pci_sort_breadthfirst_klist();
1260 }
1261
Tomato firmware and modifications.