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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / net / tg3.c
blob2f3184184ad9b201c82d5c38260de72d4a5f2d6a
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.77"
68 #define DRV_MODULE_RELDATE "May 31, 2007"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307 writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312 return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
356 }
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451 unsigned long flags;
452
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476 unsigned long flags;
477
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520 tp->irq_sync = 0;
521 wmb();
522
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551 }
552
553 /* tg3_restart_ints
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
557 */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
562 mmiowb();
563
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599 return;
600
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
620 }
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS 5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722 }
723
724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
725 {
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735 }
736
737 static int tg3_bmcr_reset(struct tg3 *tp)
738 {
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766 }
767
768 static int tg3_wait_macro_done(struct tg3 *tp)
769 {
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784 }
785
786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787 {
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850 }
851
852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
853 {
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870 }
871
872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873 {
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946 }
947
948 static void tg3_link_report(struct tg3 *);
949
950 /* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953 static int tg3_phy_reset(struct tg3 *tp)
954 {
955 u32 phy_status;
956 int err;
957
958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988 out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071 struct tg3 *tp_peer = tp;
1072
1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074 return;
1075
1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081 /* remove_one() may have been run on the peer. */
1082 if (!dev_peer)
1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1086 }
1087
1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1101 } else {
1102 u32 no_gpio2;
1103 u32 grc_local_ctrl = 0;
1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
1115 }
1116
1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161 }
1162 }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN 0
1168 #define RESET_KIND_INIT 1
1169 #define RESET_KIND_SUSPEND 2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183 sg_dig_ctrl |=
1184 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187 }
1188 return;
1189 }
1190
1191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192 u32 val;
1193
1194 tg3_bmcr_reset(tp);
1195 val = tr32(GRC_MISC_CFG);
1196 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197 udelay(40);
1198 return;
1199 } else {
1200 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203 }
1204
1205 /* The PHY should not be powered down on some chips because
1206 * of bugs.
1207 */
1208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212 return;
1213 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218 u32 misc_host_ctrl;
1219 u16 power_control, power_caps;
1220 int pm = tp->pm_cap;
1221
1222 /* Make sure register accesses (indirect or otherwise)
1223 * will function correctly.
1224 */
1225 pci_write_config_dword(tp->pdev,
1226 TG3PCI_MISC_HOST_CTRL,
1227 tp->misc_host_ctrl);
1228
1229 pci_read_config_word(tp->pdev,
1230 pm + PCI_PM_CTRL,
1231 &power_control);
1232 power_control |= PCI_PM_CTRL_PME_STATUS;
1233 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234 switch (state) {
1235 case PCI_D0:
1236 power_control |= 0;
1237 pci_write_config_word(tp->pdev,
1238 pm + PCI_PM_CTRL,
1239 power_control);
1240 udelay(100); /* Delay after power state change */
1241
1242 /* Switch out of Vaux if it is a NIC */
1243 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246 return 0;
1247
1248 case PCI_D1:
1249 power_control |= 1;
1250 break;
1251
1252 case PCI_D2:
1253 power_control |= 2;
1254 break;
1255
1256 case PCI_D3hot:
1257 power_control |= 3;
1258 break;
1259
1260 default:
1261 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262 "requested.\n",
1263 tp->dev->name, state);
1264 return -EINVAL;
1265 };
1266
1267 power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270 tw32(TG3PCI_MISC_HOST_CTRL,
1271 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273 if (tp->link_config.phy_is_low_power == 0) {
1274 tp->link_config.phy_is_low_power = 1;
1275 tp->link_config.orig_speed = tp->link_config.speed;
1276 tp->link_config.orig_duplex = tp->link_config.duplex;
1277 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278 }
1279
1280 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281 tp->link_config.speed = SPEED_10;
1282 tp->link_config.duplex = DUPLEX_HALF;
1283 tp->link_config.autoneg = AUTONEG_ENABLE;
1284 tg3_setup_phy(tp, 0);
1285 }
1286
1287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288 u32 val;
1289
1290 val = tr32(GRC_VCPU_EXT_CTRL);
1291 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293 int i;
1294 u32 val;
1295
1296 for (i = 0; i < 200; i++) {
1297 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299 break;
1300 msleep(1);
1301 }
1302 }
1303 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305 WOL_DRV_STATE_SHUTDOWN |
1306 WOL_DRV_WOL |
1307 WOL_SET_MAGIC_PKT);
1308
1309 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312 u32 mac_mode;
1313
1314 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316 udelay(40);
1317
1318 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320 else
1321 mac_mode = MAC_MODE_PORT_MODE_MII;
1322
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325 mac_mode |= MAC_MODE_LINK_POLARITY;
1326 } else {
1327 mac_mode = MAC_MODE_PORT_MODE_TBI;
1328 }
1329
1330 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1331 tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337 tw32_f(MAC_MODE, mac_mode);
1338 udelay(100);
1339
1340 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341 udelay(10);
1342 }
1343
1344 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347 u32 base_val;
1348
1349 base_val = tp->pci_clock_ctrl;
1350 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351 CLOCK_CTRL_TXCLK_DISABLE);
1352
1353 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1355 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1357 /* do nothing */
1358 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1359 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360 u32 newbits1, newbits2;
1361
1362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365 CLOCK_CTRL_TXCLK_DISABLE |
1366 CLOCK_CTRL_ALTCLK);
1367 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369 newbits1 = CLOCK_CTRL_625_CORE;
1370 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371 } else {
1372 newbits1 = CLOCK_CTRL_ALTCLK;
1373 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374 }
1375
1376 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377 40);
1378
1379 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380 40);
1381
1382 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383 u32 newbits3;
1384
1385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388 CLOCK_CTRL_TXCLK_DISABLE |
1389 CLOCK_CTRL_44MHZ_CORE);
1390 } else {
1391 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392 }
1393
1394 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395 tp->pci_clock_ctrl | newbits3, 40);
1396 }
1397 }
1398
1399 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1400 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401 tg3_power_down_phy(tp);
1402
1403 tg3_frob_aux_power(tp);
1404
1405 /* Workaround for unstable PLL clock */
1406 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408 u32 val = tr32(0x7d00);
1409
1410 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411 tw32(0x7d00, val);
1412 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1413 int err;
1414
1415 err = tg3_nvram_lock(tp);
1416 tg3_halt_cpu(tp, RX_CPU_BASE);
1417 if (!err)
1418 tg3_nvram_unlock(tp);
1419 }
1420 }
1421
1422 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1424 /* Finally, set the new power state. */
1425 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1426 udelay(100); /* Delay after power state change */
1427
1428 return 0;
1429 }
1430
1431 static void tg3_link_report(struct tg3 *tp)
1432 {
1433 if (!netif_carrier_ok(tp->dev)) {
1434 if (netif_msg_link(tp))
1435 printk(KERN_INFO PFX "%s: Link is down.\n",
1436 tp->dev->name);
1437 } else if (netif_msg_link(tp)) {
1438 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439 tp->dev->name,
1440 (tp->link_config.active_speed == SPEED_1000 ?
1441 1000 :
1442 (tp->link_config.active_speed == SPEED_100 ?
1443 100 : 10)),
1444 (tp->link_config.active_duplex == DUPLEX_FULL ?
1445 "full" : "half"));
1446
1447 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448 "%s for RX.\n",
1449 tp->dev->name,
1450 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452 }
1453 }
1454
1455 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456 {
1457 u32 new_tg3_flags = 0;
1458 u32 old_rx_mode = tp->rx_mode;
1459 u32 old_tx_mode = tp->tx_mode;
1460
1461 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1462
1463 /* Convert 1000BaseX flow control bits to 1000BaseT
1464 * bits before resolving flow control.
1465 */
1466 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468 ADVERTISE_PAUSE_ASYM);
1469 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471 if (local_adv & ADVERTISE_1000XPAUSE)
1472 local_adv |= ADVERTISE_PAUSE_CAP;
1473 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474 local_adv |= ADVERTISE_PAUSE_ASYM;
1475 if (remote_adv & LPA_1000XPAUSE)
1476 remote_adv |= LPA_PAUSE_CAP;
1477 if (remote_adv & LPA_1000XPAUSE_ASYM)
1478 remote_adv |= LPA_PAUSE_ASYM;
1479 }
1480
1481 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483 if (remote_adv & LPA_PAUSE_CAP)
1484 new_tg3_flags |=
1485 (TG3_FLAG_RX_PAUSE |
1486 TG3_FLAG_TX_PAUSE);
1487 else if (remote_adv & LPA_PAUSE_ASYM)
1488 new_tg3_flags |=
1489 (TG3_FLAG_RX_PAUSE);
1490 } else {
1491 if (remote_adv & LPA_PAUSE_CAP)
1492 new_tg3_flags |=
1493 (TG3_FLAG_RX_PAUSE |
1494 TG3_FLAG_TX_PAUSE);
1495 }
1496 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497 if ((remote_adv & LPA_PAUSE_CAP) &&
1498 (remote_adv & LPA_PAUSE_ASYM))
1499 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500 }
1501
1502 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503 tp->tg3_flags |= new_tg3_flags;
1504 } else {
1505 new_tg3_flags = tp->tg3_flags;
1506 }
1507
1508 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510 else
1511 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513 if (old_rx_mode != tp->rx_mode) {
1514 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515 }
1516
1517 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519 else
1520 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522 if (old_tx_mode != tp->tx_mode) {
1523 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524 }
1525 }
1526
1527 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528 {
1529 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530 case MII_TG3_AUX_STAT_10HALF:
1531 *speed = SPEED_10;
1532 *duplex = DUPLEX_HALF;
1533 break;
1534
1535 case MII_TG3_AUX_STAT_10FULL:
1536 *speed = SPEED_10;
1537 *duplex = DUPLEX_FULL;
1538 break;
1539
1540 case MII_TG3_AUX_STAT_100HALF:
1541 *speed = SPEED_100;
1542 *duplex = DUPLEX_HALF;
1543 break;
1544
1545 case MII_TG3_AUX_STAT_100FULL:
1546 *speed = SPEED_100;
1547 *duplex = DUPLEX_FULL;
1548 break;
1549
1550 case MII_TG3_AUX_STAT_1000HALF:
1551 *speed = SPEED_1000;
1552 *duplex = DUPLEX_HALF;
1553 break;
1554
1555 case MII_TG3_AUX_STAT_1000FULL:
1556 *speed = SPEED_1000;
1557 *duplex = DUPLEX_FULL;
1558 break;
1559
1560 default:
1561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563 SPEED_10;
1564 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565 DUPLEX_HALF;
1566 break;
1567 }
1568 *speed = SPEED_INVALID;
1569 *duplex = DUPLEX_INVALID;
1570 break;
1571 };
1572 }
1573
1574 static void tg3_phy_copper_begin(struct tg3 *tp)
1575 {
1576 u32 new_adv;
1577 int i;
1578
1579 if (tp->link_config.phy_is_low_power) {
1580 /* Entering low power mode. Disable gigabit and
1581 * 100baseT advertisements.
1582 */
1583 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591 } else if (tp->link_config.speed == SPEED_INVALID) {
1592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593 tp->link_config.advertising &=
1594 ~(ADVERTISED_1000baseT_Half |
1595 ADVERTISED_1000baseT_Full);
1596
1597 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599 new_adv |= ADVERTISE_10HALF;
1600 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601 new_adv |= ADVERTISE_10FULL;
1602 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603 new_adv |= ADVERTISE_100HALF;
1604 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605 new_adv |= ADVERTISE_100FULL;
1606 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608 if (tp->link_config.advertising &
1609 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610 new_adv = 0;
1611 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619 MII_TG3_CTRL_ENABLE_AS_MASTER);
1620 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621 } else {
1622 tg3_writephy(tp, MII_TG3_CTRL, 0);
1623 }
1624 } else {
1625 /* Asking for a specific link mode. */
1626 if (tp->link_config.speed == SPEED_1000) {
1627 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630 if (tp->link_config.duplex == DUPLEX_FULL)
1631 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632 else
1633 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637 MII_TG3_CTRL_ENABLE_AS_MASTER);
1638 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639 } else {
1640 tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643 if (tp->link_config.speed == SPEED_100) {
1644 if (tp->link_config.duplex == DUPLEX_FULL)
1645 new_adv |= ADVERTISE_100FULL;
1646 else
1647 new_adv |= ADVERTISE_100HALF;
1648 } else {
1649 if (tp->link_config.duplex == DUPLEX_FULL)
1650 new_adv |= ADVERTISE_10FULL;
1651 else
1652 new_adv |= ADVERTISE_10HALF;
1653 }
1654 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 }
1656 }
1657
1658 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659 tp->link_config.speed != SPEED_INVALID) {
1660 u32 bmcr, orig_bmcr;
1661
1662 tp->link_config.active_speed = tp->link_config.speed;
1663 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665 bmcr = 0;
1666 switch (tp->link_config.speed) {
1667 default:
1668 case SPEED_10:
1669 break;
1670
1671 case SPEED_100:
1672 bmcr |= BMCR_SPEED100;
1673 break;
1674
1675 case SPEED_1000:
1676 bmcr |= TG3_BMCR_SPEED1000;
1677 break;
1678 };
1679
1680 if (tp->link_config.duplex == DUPLEX_FULL)
1681 bmcr |= BMCR_FULLDPLX;
1682
1683 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684 (bmcr != orig_bmcr)) {
1685 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686 for (i = 0; i < 1500; i++) {
1687 u32 tmp;
1688
1689 udelay(10);
1690 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691 tg3_readphy(tp, MII_BMSR, &tmp))
1692 continue;
1693 if (!(tmp & BMSR_LSTATUS)) {
1694 udelay(40);
1695 break;
1696 }
1697 }
1698 tg3_writephy(tp, MII_BMCR, bmcr);
1699 udelay(40);
1700 }
1701 } else {
1702 tg3_writephy(tp, MII_BMCR,
1703 BMCR_ANENABLE | BMCR_ANRESTART);
1704 }
1705 }
1706
1707 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708 {
1709 int err;
1710
1711 /* Turn off tap power management. */
1712 /* Set Extended packet length bit */
1713 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730 udelay(40);
1731
1732 return err;
1733 }
1734
1735 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1736 {
1737 u32 adv_reg, all_mask = 0;
1738
1739 if (mask & ADVERTISED_10baseT_Half)
1740 all_mask |= ADVERTISE_10HALF;
1741 if (mask & ADVERTISED_10baseT_Full)
1742 all_mask |= ADVERTISE_10FULL;
1743 if (mask & ADVERTISED_100baseT_Half)
1744 all_mask |= ADVERTISE_100HALF;
1745 if (mask & ADVERTISED_100baseT_Full)
1746 all_mask |= ADVERTISE_100FULL;
1747
1748 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749 return 0;
1750
1751 if ((adv_reg & all_mask) != all_mask)
1752 return 0;
1753 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754 u32 tg3_ctrl;
1755
1756 all_mask = 0;
1757 if (mask & ADVERTISED_1000baseT_Half)
1758 all_mask |= ADVERTISE_1000HALF;
1759 if (mask & ADVERTISED_1000baseT_Full)
1760 all_mask |= ADVERTISE_1000FULL;
1761
1762 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763 return 0;
1764
1765 if ((tg3_ctrl & all_mask) != all_mask)
1766 return 0;
1767 }
1768 return 1;
1769 }
1770
1771 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772 {
1773 int current_link_up;
1774 u32 bmsr, dummy;
1775 u16 current_speed;
1776 u8 current_duplex;
1777 int i, err;
1778
1779 tw32(MAC_EVENT, 0);
1780
1781 tw32_f(MAC_STATUS,
1782 (MAC_STATUS_SYNC_CHANGED |
1783 MAC_STATUS_CFG_CHANGED |
1784 MAC_STATUS_MI_COMPLETION |
1785 MAC_STATUS_LNKSTATE_CHANGED));
1786 udelay(40);
1787
1788 tp->mi_mode = MAC_MI_MODE_BASE;
1789 tw32_f(MAC_MI_MODE, tp->mi_mode);
1790 udelay(80);
1791
1792 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794 /* Some third-party PHYs need to be reset on link going
1795 * down.
1796 */
1797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800 netif_carrier_ok(tp->dev)) {
1801 tg3_readphy(tp, MII_BMSR, &bmsr);
1802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803 !(bmsr & BMSR_LSTATUS))
1804 force_reset = 1;
1805 }
1806 if (force_reset)
1807 tg3_phy_reset(tp);
1808
1809 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810 tg3_readphy(tp, MII_BMSR, &bmsr);
1811 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813 bmsr = 0;
1814
1815 if (!(bmsr & BMSR_LSTATUS)) {
1816 err = tg3_init_5401phy_dsp(tp);
1817 if (err)
1818 return err;
1819
1820 tg3_readphy(tp, MII_BMSR, &bmsr);
1821 for (i = 0; i < 1000; i++) {
1822 udelay(10);
1823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824 (bmsr & BMSR_LSTATUS)) {
1825 udelay(40);
1826 break;
1827 }
1828 }
1829
1830 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831 !(bmsr & BMSR_LSTATUS) &&
1832 tp->link_config.active_speed == SPEED_1000) {
1833 err = tg3_phy_reset(tp);
1834 if (!err)
1835 err = tg3_init_5401phy_dsp(tp);
1836 if (err)
1837 return err;
1838 }
1839 }
1840 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842 /* 5701 {A0,B0} CRC bug workaround */
1843 tg3_writephy(tp, 0x15, 0x0a75);
1844 tg3_writephy(tp, 0x1c, 0x8c68);
1845 tg3_writephy(tp, 0x1c, 0x8d68);
1846 tg3_writephy(tp, 0x1c, 0x8c68);
1847 }
1848
1849 /* Clear pending interrupts... */
1850 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863 else
1864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865 }
1866
1867 current_link_up = 0;
1868 current_speed = SPEED_INVALID;
1869 current_duplex = DUPLEX_INVALID;
1870
1871 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872 u32 val;
1873
1874 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876 if (!(val & (1 << 10))) {
1877 val |= (1 << 10);
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879 goto relink;
1880 }
1881 }
1882
1883 bmsr = 0;
1884 for (i = 0; i < 100; i++) {
1885 tg3_readphy(tp, MII_BMSR, &bmsr);
1886 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887 (bmsr & BMSR_LSTATUS))
1888 break;
1889 udelay(40);
1890 }
1891
1892 if (bmsr & BMSR_LSTATUS) {
1893 u32 aux_stat, bmcr;
1894
1895 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896 for (i = 0; i < 2000; i++) {
1897 udelay(10);
1898 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899 aux_stat)
1900 break;
1901 }
1902
1903 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904 &current_speed,
1905 &current_duplex);
1906
1907 bmcr = 0;
1908 for (i = 0; i < 200; i++) {
1909 tg3_readphy(tp, MII_BMCR, &bmcr);
1910 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911 continue;
1912 if (bmcr && bmcr != 0x7fff)
1913 break;
1914 udelay(10);
1915 }
1916
1917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918 if (bmcr & BMCR_ANENABLE) {
1919 current_link_up = 1;
1920
1921 /* Force autoneg restart if we are exiting
1922 * low power mode.
1923 */
1924 if (!tg3_copper_is_advertising_all(tp,
1925 tp->link_config.advertising))
1926 current_link_up = 0;
1927 } else {
1928 current_link_up = 0;
1929 }
1930 } else {
1931 if (!(bmcr & BMCR_ANENABLE) &&
1932 tp->link_config.speed == current_speed &&
1933 tp->link_config.duplex == current_duplex) {
1934 current_link_up = 1;
1935 } else {
1936 current_link_up = 0;
1937 }
1938 }
1939
1940 tp->link_config.active_speed = current_speed;
1941 tp->link_config.active_duplex = current_duplex;
1942 }
1943
1944 if (current_link_up == 1 &&
1945 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947 u32 local_adv, remote_adv;
1948
1949 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950 local_adv = 0;
1951 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954 remote_adv = 0;
1955
1956 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958 /* If we are not advertising full pause capability,
1959 * something is wrong. Bring the link down and reconfigure.
1960 */
1961 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962 current_link_up = 0;
1963 } else {
1964 tg3_setup_flow_control(tp, local_adv, remote_adv);
1965 }
1966 }
1967 relink:
1968 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1969 u32 tmp;
1970
1971 tg3_phy_copper_begin(tp);
1972
1973 tg3_readphy(tp, MII_BMSR, &tmp);
1974 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975 (tmp & BMSR_LSTATUS))
1976 current_link_up = 1;
1977 }
1978
1979 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980 if (current_link_up == 1) {
1981 if (tp->link_config.active_speed == SPEED_100 ||
1982 tp->link_config.active_speed == SPEED_10)
1983 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984 else
1985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986 } else
1987 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990 if (tp->link_config.active_duplex == DUPLEX_HALF)
1991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996 (current_link_up == 1 &&
1997 tp->link_config.active_speed == SPEED_10))
1998 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999 } else {
2000 if (current_link_up == 1)
2001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002 }
2003
2004 /* ??? Without this setting Netgear GA302T PHY does not
2005 * ??? send/receive packets...
2006 */
2007 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011 udelay(80);
2012 }
2013
2014 tw32_f(MAC_MODE, tp->mac_mode);
2015 udelay(40);
2016
2017 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018 /* Polled via timer. */
2019 tw32_f(MAC_EVENT, 0);
2020 } else {
2021 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022 }
2023 udelay(40);
2024
2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026 current_link_up == 1 &&
2027 tp->link_config.active_speed == SPEED_1000 &&
2028 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030 udelay(120);
2031 tw32_f(MAC_STATUS,
2032 (MAC_STATUS_SYNC_CHANGED |
2033 MAC_STATUS_CFG_CHANGED));
2034 udelay(40);
2035 tg3_write_mem(tp,
2036 NIC_SRAM_FIRMWARE_MBOX,
2037 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038 }
2039
2040 if (current_link_up != netif_carrier_ok(tp->dev)) {
2041 if (current_link_up)
2042 netif_carrier_on(tp->dev);
2043 else
2044 netif_carrier_off(tp->dev);
2045 tg3_link_report(tp);
2046 }
2047
2048 return 0;
2049 }
2050
2051 struct tg3_fiber_aneginfo {
2052 int state;
2053 #define ANEG_STATE_UNKNOWN 0
2054 #define ANEG_STATE_AN_ENABLE 1
2055 #define ANEG_STATE_RESTART_INIT 2
2056 #define ANEG_STATE_RESTART 3
2057 #define ANEG_STATE_DISABLE_LINK_OK 4
2058 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2059 #define ANEG_STATE_ABILITY_DETECT 6
2060 #define ANEG_STATE_ACK_DETECT_INIT 7
2061 #define ANEG_STATE_ACK_DETECT 8
2062 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2063 #define ANEG_STATE_COMPLETE_ACK 10
2064 #define ANEG_STATE_IDLE_DETECT_INIT 11
2065 #define ANEG_STATE_IDLE_DETECT 12
2066 #define ANEG_STATE_LINK_OK 13
2067 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2068 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2069
2070 u32 flags;
2071 #define MR_AN_ENABLE 0x00000001
2072 #define MR_RESTART_AN 0x00000002
2073 #define MR_AN_COMPLETE 0x00000004
2074 #define MR_PAGE_RX 0x00000008
2075 #define MR_NP_LOADED 0x00000010
2076 #define MR_TOGGLE_TX 0x00000020
2077 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2078 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2079 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2080 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2081 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2084 #define MR_TOGGLE_RX 0x00002000
2085 #define MR_NP_RX 0x00004000
2086
2087 #define MR_LINK_OK 0x80000000
2088
2089 unsigned long link_time, cur_time;
2090
2091 u32 ability_match_cfg;
2092 int ability_match_count;
2093
2094 char ability_match, idle_match, ack_match;
2095
2096 u32 txconfig, rxconfig;
2097 #define ANEG_CFG_NP 0x00000080
2098 #define ANEG_CFG_ACK 0x00000040
2099 #define ANEG_CFG_RF2 0x00000020
2100 #define ANEG_CFG_RF1 0x00000010
2101 #define ANEG_CFG_PS2 0x00000001
2102 #define ANEG_CFG_PS1 0x00008000
2103 #define ANEG_CFG_HD 0x00004000
2104 #define ANEG_CFG_FD 0x00002000
2105 #define ANEG_CFG_INVAL 0x00001f06
2106
2107 };
2108 #define ANEG_OK 0
2109 #define ANEG_DONE 1
2110 #define ANEG_TIMER_ENAB 2
2111 #define ANEG_FAILED -1
2112
2113 #define ANEG_STATE_SETTLE_TIME 10000
2114
2115 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116 struct tg3_fiber_aneginfo *ap)
2117 {
2118 unsigned long delta;
2119 u32 rx_cfg_reg;
2120 int ret;
2121
2122 if (ap->state == ANEG_STATE_UNKNOWN) {
2123 ap->rxconfig = 0;
2124 ap->link_time = 0;
2125 ap->cur_time = 0;
2126 ap->ability_match_cfg = 0;
2127 ap->ability_match_count = 0;
2128 ap->ability_match = 0;
2129 ap->idle_match = 0;
2130 ap->ack_match = 0;
2131 }
2132 ap->cur_time++;
2133
2134 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137 if (rx_cfg_reg != ap->ability_match_cfg) {
2138 ap->ability_match_cfg = rx_cfg_reg;
2139 ap->ability_match = 0;
2140 ap->ability_match_count = 0;
2141 } else {
2142 if (++ap->ability_match_count > 1) {
2143 ap->ability_match = 1;
2144 ap->ability_match_cfg = rx_cfg_reg;
2145 }
2146 }
2147 if (rx_cfg_reg & ANEG_CFG_ACK)
2148 ap->ack_match = 1;
2149 else
2150 ap->ack_match = 0;
2151
2152 ap->idle_match = 0;
2153 } else {
2154 ap->idle_match = 1;
2155 ap->ability_match_cfg = 0;
2156 ap->ability_match_count = 0;
2157 ap->ability_match = 0;
2158 ap->ack_match = 0;
2159
2160 rx_cfg_reg = 0;
2161 }
2162
2163 ap->rxconfig = rx_cfg_reg;
2164 ret = ANEG_OK;
2165
2166 switch(ap->state) {
2167 case ANEG_STATE_UNKNOWN:
2168 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169 ap->state = ANEG_STATE_AN_ENABLE;
2170
2171 /* fallthru */
2172 case ANEG_STATE_AN_ENABLE:
2173 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174 if (ap->flags & MR_AN_ENABLE) {
2175 ap->link_time = 0;
2176 ap->cur_time = 0;
2177 ap->ability_match_cfg = 0;
2178 ap->ability_match_count = 0;
2179 ap->ability_match = 0;
2180 ap->idle_match = 0;
2181 ap->ack_match = 0;
2182
2183 ap->state = ANEG_STATE_RESTART_INIT;
2184 } else {
2185 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186 }
2187 break;
2188
2189 case ANEG_STATE_RESTART_INIT:
2190 ap->link_time = ap->cur_time;
2191 ap->flags &= ~(MR_NP_LOADED);
2192 ap->txconfig = 0;
2193 tw32(MAC_TX_AUTO_NEG, 0);
2194 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195 tw32_f(MAC_MODE, tp->mac_mode);
2196 udelay(40);
2197
2198 ret = ANEG_TIMER_ENAB;
2199 ap->state = ANEG_STATE_RESTART;
2200
2201 /* fallthru */
2202 case ANEG_STATE_RESTART:
2203 delta = ap->cur_time - ap->link_time;
2204 if (delta > ANEG_STATE_SETTLE_TIME) {
2205 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206 } else {
2207 ret = ANEG_TIMER_ENAB;
2208 }
2209 break;
2210
2211 case ANEG_STATE_DISABLE_LINK_OK:
2212 ret = ANEG_DONE;
2213 break;
2214
2215 case ANEG_STATE_ABILITY_DETECT_INIT:
2216 ap->flags &= ~(MR_TOGGLE_TX);
2217 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220 tw32_f(MAC_MODE, tp->mac_mode);
2221 udelay(40);
2222
2223 ap->state = ANEG_STATE_ABILITY_DETECT;
2224 break;
2225
2226 case ANEG_STATE_ABILITY_DETECT:
2227 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229 }
2230 break;
2231
2232 case ANEG_STATE_ACK_DETECT_INIT:
2233 ap->txconfig |= ANEG_CFG_ACK;
2234 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236 tw32_f(MAC_MODE, tp->mac_mode);
2237 udelay(40);
2238
2239 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241 /* fallthru */
2242 case ANEG_STATE_ACK_DETECT:
2243 if (ap->ack_match != 0) {
2244 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247 } else {
2248 ap->state = ANEG_STATE_AN_ENABLE;
2249 }
2250 } else if (ap->ability_match != 0 &&
2251 ap->rxconfig == 0) {
2252 ap->state = ANEG_STATE_AN_ENABLE;
2253 }
2254 break;
2255
2256 case ANEG_STATE_COMPLETE_ACK_INIT:
2257 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258 ret = ANEG_FAILED;
2259 break;
2260 }
2261 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262 MR_LP_ADV_HALF_DUPLEX |
2263 MR_LP_ADV_SYM_PAUSE |
2264 MR_LP_ADV_ASYM_PAUSE |
2265 MR_LP_ADV_REMOTE_FAULT1 |
2266 MR_LP_ADV_REMOTE_FAULT2 |
2267 MR_LP_ADV_NEXT_PAGE |
2268 MR_TOGGLE_RX |
2269 MR_NP_RX);
2270 if (ap->rxconfig & ANEG_CFG_FD)
2271 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272 if (ap->rxconfig & ANEG_CFG_HD)
2273 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274 if (ap->rxconfig & ANEG_CFG_PS1)
2275 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276 if (ap->rxconfig & ANEG_CFG_PS2)
2277 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278 if (ap->rxconfig & ANEG_CFG_RF1)
2279 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280 if (ap->rxconfig & ANEG_CFG_RF2)
2281 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282 if (ap->rxconfig & ANEG_CFG_NP)
2283 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285 ap->link_time = ap->cur_time;
2286
2287 ap->flags ^= (MR_TOGGLE_TX);
2288 if (ap->rxconfig & 0x0008)
2289 ap->flags |= MR_TOGGLE_RX;
2290 if (ap->rxconfig & ANEG_CFG_NP)
2291 ap->flags |= MR_NP_RX;
2292 ap->flags |= MR_PAGE_RX;
2293
2294 ap->state = ANEG_STATE_COMPLETE_ACK;
2295 ret = ANEG_TIMER_ENAB;
2296 break;
2297
2298 case ANEG_STATE_COMPLETE_ACK:
2299 if (ap->ability_match != 0 &&
2300 ap->rxconfig == 0) {
2301 ap->state = ANEG_STATE_AN_ENABLE;
2302 break;
2303 }
2304 delta = ap->cur_time - ap->link_time;
2305 if (delta > ANEG_STATE_SETTLE_TIME) {
2306 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308 } else {
2309 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310 !(ap->flags & MR_NP_RX)) {
2311 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312 } else {
2313 ret = ANEG_FAILED;
2314 }
2315 }
2316 }
2317 break;
2318
2319 case ANEG_STATE_IDLE_DETECT_INIT:
2320 ap->link_time = ap->cur_time;
2321 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322 tw32_f(MAC_MODE, tp->mac_mode);
2323 udelay(40);
2324
2325 ap->state = ANEG_STATE_IDLE_DETECT;
2326 ret = ANEG_TIMER_ENAB;
2327 break;
2328
2329 case ANEG_STATE_IDLE_DETECT:
2330 if (ap->ability_match != 0 &&
2331 ap->rxconfig == 0) {
2332 ap->state = ANEG_STATE_AN_ENABLE;
2333 break;
2334 }
2335 delta = ap->cur_time - ap->link_time;
2336 if (delta > ANEG_STATE_SETTLE_TIME) {
2337 /* XXX another gem from the Broadcom driver :( */
2338 ap->state = ANEG_STATE_LINK_OK;
2339 }
2340 break;
2341
2342 case ANEG_STATE_LINK_OK:
2343 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344 ret = ANEG_DONE;
2345 break;
2346
2347 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348 /* ??? unimplemented */
2349 break;
2350
2351 case ANEG_STATE_NEXT_PAGE_WAIT:
2352 /* ??? unimplemented */
2353 break;
2354
2355 default:
2356 ret = ANEG_FAILED;
2357 break;
2358 };
2359
2360 return ret;
2361 }
2362
2363 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364 {
2365 int res = 0;
2366 struct tg3_fiber_aneginfo aninfo;
2367 int status = ANEG_FAILED;
2368 unsigned int tick;
2369 u32 tmp;
2370
2371 tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375 udelay(40);
2376
2377 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378 udelay(40);
2379
2380 memset(&aninfo, 0, sizeof(aninfo));
2381 aninfo.flags |= MR_AN_ENABLE;
2382 aninfo.state = ANEG_STATE_UNKNOWN;
2383 aninfo.cur_time = 0;
2384 tick = 0;
2385 while (++tick < 195000) {
2386 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387 if (status == ANEG_DONE || status == ANEG_FAILED)
2388 break;
2389
2390 udelay(1);
2391 }
2392
2393 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394 tw32_f(MAC_MODE, tp->mac_mode);
2395 udelay(40);
2396
2397 *flags = aninfo.flags;
2398
2399 if (status == ANEG_DONE &&
2400 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401 MR_LP_ADV_FULL_DUPLEX)))
2402 res = 1;
2403
2404 return res;
2405 }
2406
2407 static void tg3_init_bcm8002(struct tg3 *tp)
2408 {
2409 u32 mac_status = tr32(MAC_STATUS);
2410 int i;
2411
2412 /* Reset when initting first time or we have a link. */
2413 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414 !(mac_status & MAC_STATUS_PCS_SYNCED))
2415 return;
2416
2417 /* Set PLL lock range. */
2418 tg3_writephy(tp, 0x16, 0x8007);
2419
2420 /* SW reset */
2421 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423 /* Wait for reset to complete. */
2424 /* XXX schedule_timeout() ... */
2425 for (i = 0; i < 500; i++)
2426 udelay(10);
2427
2428 /* Config mode; select PMA/Ch 1 regs. */
2429 tg3_writephy(tp, 0x10, 0x8411);
2430
2431 /* Enable auto-lock and comdet, select txclk for tx. */
2432 tg3_writephy(tp, 0x11, 0x0a10);
2433
2434 tg3_writephy(tp, 0x18, 0x00a0);
2435 tg3_writephy(tp, 0x16, 0x41ff);
2436
2437 /* Assert and deassert POR. */
2438 tg3_writephy(tp, 0x13, 0x0400);
2439 udelay(40);
2440 tg3_writephy(tp, 0x13, 0x0000);
2441
2442 tg3_writephy(tp, 0x11, 0x0a50);
2443 udelay(40);
2444 tg3_writephy(tp, 0x11, 0x0a10);
2445
2446 /* Wait for signal to stabilize */
2447 /* XXX schedule_timeout() ... */
2448 for (i = 0; i < 15000; i++)
2449 udelay(10);
2450
2451 /* Deselect the channel register so we can read the PHYID
2452 * later.
2453 */
2454 tg3_writephy(tp, 0x10, 0x8011);
2455 }
2456
2457 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458 {
2459 u32 sg_dig_ctrl, sg_dig_status;
2460 u32 serdes_cfg, expected_sg_dig_ctrl;
2461 int workaround, port_a;
2462 int current_link_up;
2463
2464 serdes_cfg = 0;
2465 expected_sg_dig_ctrl = 0;
2466 workaround = 0;
2467 port_a = 1;
2468 current_link_up = 0;
2469
2470 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472 workaround = 1;
2473 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474 port_a = 0;
2475
2476 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477 /* preserve bits 20-23 for voltage regulator */
2478 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479 }
2480
2481 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484 if (sg_dig_ctrl & (1 << 31)) {
2485 if (workaround) {
2486 u32 val = serdes_cfg;
2487
2488 if (port_a)
2489 val |= 0xc010000;
2490 else
2491 val |= 0x4010000;
2492 tw32_f(MAC_SERDES_CFG, val);
2493 }
2494 tw32_f(SG_DIG_CTRL, 0x01388400);
2495 }
2496 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497 tg3_setup_flow_control(tp, 0, 0);
2498 current_link_up = 1;
2499 }
2500 goto out;
2501 }
2502
2503 /* Want auto-negotiation. */
2504 expected_sg_dig_ctrl = 0x81388400;
2505
2506 /* Pause capability */
2507 expected_sg_dig_ctrl |= (1 << 11);
2508
2509 /* Asymettric pause */
2510 expected_sg_dig_ctrl |= (1 << 12);
2511
2512 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2513 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514 tp->serdes_counter &&
2515 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516 MAC_STATUS_RCVD_CFG)) ==
2517 MAC_STATUS_PCS_SYNCED)) {
2518 tp->serdes_counter--;
2519 current_link_up = 1;
2520 goto out;
2521 }
2522 restart_autoneg:
2523 if (workaround)
2524 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526 udelay(5);
2527 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
2529 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2531 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532 MAC_STATUS_SIGNAL_DET)) {
2533 sg_dig_status = tr32(SG_DIG_STATUS);
2534 mac_status = tr32(MAC_STATUS);
2535
2536 if ((sg_dig_status & (1 << 1)) &&
2537 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538 u32 local_adv, remote_adv;
2539
2540 local_adv = ADVERTISE_PAUSE_CAP;
2541 remote_adv = 0;
2542 if (sg_dig_status & (1 << 19))
2543 remote_adv |= LPA_PAUSE_CAP;
2544 if (sg_dig_status & (1 << 20))
2545 remote_adv |= LPA_PAUSE_ASYM;
2546
2547 tg3_setup_flow_control(tp, local_adv, remote_adv);
2548 current_link_up = 1;
2549 tp->serdes_counter = 0;
2550 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2551 } else if (!(sg_dig_status & (1 << 1))) {
2552 if (tp->serdes_counter)
2553 tp->serdes_counter--;
2554 else {
2555 if (workaround) {
2556 u32 val = serdes_cfg;
2557
2558 if (port_a)
2559 val |= 0xc010000;
2560 else
2561 val |= 0x4010000;
2562
2563 tw32_f(MAC_SERDES_CFG, val);
2564 }
2565
2566 tw32_f(SG_DIG_CTRL, 0x01388400);
2567 udelay(40);
2568
2569 /* Link parallel detection - link is up */
2570 /* only if we have PCS_SYNC and not */
2571 /* receiving config code words */
2572 mac_status = tr32(MAC_STATUS);
2573 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575 tg3_setup_flow_control(tp, 0, 0);
2576 current_link_up = 1;
2577 tp->tg3_flags2 |=
2578 TG3_FLG2_PARALLEL_DETECT;
2579 tp->serdes_counter =
2580 SERDES_PARALLEL_DET_TIMEOUT;
2581 } else
2582 goto restart_autoneg;
2583 }
2584 }
2585 } else {
2586 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2588 }
2589
2590 out:
2591 return current_link_up;
2592 }
2593
2594 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595 {
2596 int current_link_up = 0;
2597
2598 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2599 goto out;
2600
2601 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602 u32 flags;
2603 int i;
2604
2605 if (fiber_autoneg(tp, &flags)) {
2606 u32 local_adv, remote_adv;
2607
2608 local_adv = ADVERTISE_PAUSE_CAP;
2609 remote_adv = 0;
2610 if (flags & MR_LP_ADV_SYM_PAUSE)
2611 remote_adv |= LPA_PAUSE_CAP;
2612 if (flags & MR_LP_ADV_ASYM_PAUSE)
2613 remote_adv |= LPA_PAUSE_ASYM;
2614
2615 tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617 current_link_up = 1;
2618 }
2619 for (i = 0; i < 30; i++) {
2620 udelay(20);
2621 tw32_f(MAC_STATUS,
2622 (MAC_STATUS_SYNC_CHANGED |
2623 MAC_STATUS_CFG_CHANGED));
2624 udelay(40);
2625 if ((tr32(MAC_STATUS) &
2626 (MAC_STATUS_SYNC_CHANGED |
2627 MAC_STATUS_CFG_CHANGED)) == 0)
2628 break;
2629 }
2630
2631 mac_status = tr32(MAC_STATUS);
2632 if (current_link_up == 0 &&
2633 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2634 !(mac_status & MAC_STATUS_RCVD_CFG))
2635 current_link_up = 1;
2636 } else {
2637 /* Forcing 1000FD link up. */
2638 current_link_up = 1;
2639
2640 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641 udelay(40);
2642 }
2643
2644 out:
2645 return current_link_up;
2646 }
2647
2648 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2649 {
2650 u32 orig_pause_cfg;
2651 u16 orig_active_speed;
2652 u8 orig_active_duplex;
2653 u32 mac_status;
2654 int current_link_up;
2655 int i;
2656
2657 orig_pause_cfg =
2658 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2659 TG3_FLAG_TX_PAUSE));
2660 orig_active_speed = tp->link_config.active_speed;
2661 orig_active_duplex = tp->link_config.active_duplex;
2662
2663 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2664 netif_carrier_ok(tp->dev) &&
2665 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2666 mac_status = tr32(MAC_STATUS);
2667 mac_status &= (MAC_STATUS_PCS_SYNCED |
2668 MAC_STATUS_SIGNAL_DET |
2669 MAC_STATUS_CFG_CHANGED |
2670 MAC_STATUS_RCVD_CFG);
2671 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2672 MAC_STATUS_SIGNAL_DET)) {
2673 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2674 MAC_STATUS_CFG_CHANGED));
2675 return 0;
2676 }
2677 }
2678
2679 tw32_f(MAC_TX_AUTO_NEG, 0);
2680
2681 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2682 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2683 tw32_f(MAC_MODE, tp->mac_mode);
2684 udelay(40);
2685
2686 if (tp->phy_id == PHY_ID_BCM8002)
2687 tg3_init_bcm8002(tp);
2688
2689 /* Enable link change event even when serdes polling. */
2690 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2691 udelay(40);
2692
2693 current_link_up = 0;
2694 mac_status = tr32(MAC_STATUS);
2695
2696 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2697 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2698 else
2699 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700
2701 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702 tw32_f(MAC_MODE, tp->mac_mode);
2703 udelay(40);
2704
2705 tp->hw_status->status =
2706 (SD_STATUS_UPDATED |
2707 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2708
2709 for (i = 0; i < 100; i++) {
2710 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2711 MAC_STATUS_CFG_CHANGED));
2712 udelay(5);
2713 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2714 MAC_STATUS_CFG_CHANGED |
2715 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2716 break;
2717 }
2718
2719 mac_status = tr32(MAC_STATUS);
2720 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2721 current_link_up = 0;
2722 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2723 tp->serdes_counter == 0) {
2724 tw32_f(MAC_MODE, (tp->mac_mode |
2725 MAC_MODE_SEND_CONFIGS));
2726 udelay(1);
2727 tw32_f(MAC_MODE, tp->mac_mode);
2728 }
2729 }
2730
2731 if (current_link_up == 1) {
2732 tp->link_config.active_speed = SPEED_1000;
2733 tp->link_config.active_duplex = DUPLEX_FULL;
2734 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2735 LED_CTRL_LNKLED_OVERRIDE |
2736 LED_CTRL_1000MBPS_ON));
2737 } else {
2738 tp->link_config.active_speed = SPEED_INVALID;
2739 tp->link_config.active_duplex = DUPLEX_INVALID;
2740 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2741 LED_CTRL_LNKLED_OVERRIDE |
2742 LED_CTRL_TRAFFIC_OVERRIDE));
2743 }
2744
2745 if (current_link_up != netif_carrier_ok(tp->dev)) {
2746 if (current_link_up)
2747 netif_carrier_on(tp->dev);
2748 else
2749 netif_carrier_off(tp->dev);
2750 tg3_link_report(tp);
2751 } else {
2752 u32 now_pause_cfg =
2753 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2754 TG3_FLAG_TX_PAUSE);
2755 if (orig_pause_cfg != now_pause_cfg ||
2756 orig_active_speed != tp->link_config.active_speed ||
2757 orig_active_duplex != tp->link_config.active_duplex)
2758 tg3_link_report(tp);
2759 }
2760
2761 return 0;
2762 }
2763
2764 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2765 {
2766 int current_link_up, err = 0;
2767 u32 bmsr, bmcr;
2768 u16 current_speed;
2769 u8 current_duplex;
2770
2771 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2772 tw32_f(MAC_MODE, tp->mac_mode);
2773 udelay(40);
2774
2775 tw32(MAC_EVENT, 0);
2776
2777 tw32_f(MAC_STATUS,
2778 (MAC_STATUS_SYNC_CHANGED |
2779 MAC_STATUS_CFG_CHANGED |
2780 MAC_STATUS_MI_COMPLETION |
2781 MAC_STATUS_LNKSTATE_CHANGED));
2782 udelay(40);
2783
2784 if (force_reset)
2785 tg3_phy_reset(tp);
2786
2787 current_link_up = 0;
2788 current_speed = SPEED_INVALID;
2789 current_duplex = DUPLEX_INVALID;
2790
2791 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2792 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2794 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2795 bmsr |= BMSR_LSTATUS;
2796 else
2797 bmsr &= ~BMSR_LSTATUS;
2798 }
2799
2800 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2801
2802 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2803 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2804 /* do nothing, just check for link up at the end */
2805 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2806 u32 adv, new_adv;
2807
2808 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2809 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2810 ADVERTISE_1000XPAUSE |
2811 ADVERTISE_1000XPSE_ASYM |
2812 ADVERTISE_SLCT);
2813
2814 /* Always advertise symmetric PAUSE just like copper */
2815 new_adv |= ADVERTISE_1000XPAUSE;
2816
2817 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2818 new_adv |= ADVERTISE_1000XHALF;
2819 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2820 new_adv |= ADVERTISE_1000XFULL;
2821
2822 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2823 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2824 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2825 tg3_writephy(tp, MII_BMCR, bmcr);
2826
2827 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2828 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2830
2831 return err;
2832 }
2833 } else {
2834 u32 new_bmcr;
2835
2836 bmcr &= ~BMCR_SPEED1000;
2837 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2838
2839 if (tp->link_config.duplex == DUPLEX_FULL)
2840 new_bmcr |= BMCR_FULLDPLX;
2841
2842 if (new_bmcr != bmcr) {
2843 /* BMCR_SPEED1000 is a reserved bit that needs
2844 * to be set on write.
2845 */
2846 new_bmcr |= BMCR_SPEED1000;
2847
2848 /* Force a linkdown */
2849 if (netif_carrier_ok(tp->dev)) {
2850 u32 adv;
2851
2852 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2853 adv &= ~(ADVERTISE_1000XFULL |
2854 ADVERTISE_1000XHALF |
2855 ADVERTISE_SLCT);
2856 tg3_writephy(tp, MII_ADVERTISE, adv);
2857 tg3_writephy(tp, MII_BMCR, bmcr |
2858 BMCR_ANRESTART |
2859 BMCR_ANENABLE);
2860 udelay(10);
2861 netif_carrier_off(tp->dev);
2862 }
2863 tg3_writephy(tp, MII_BMCR, new_bmcr);
2864 bmcr = new_bmcr;
2865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2866 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2867 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2868 ASIC_REV_5714) {
2869 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2870 bmsr |= BMSR_LSTATUS;
2871 else
2872 bmsr &= ~BMSR_LSTATUS;
2873 }
2874 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2875 }
2876 }
2877
2878 if (bmsr & BMSR_LSTATUS) {
2879 current_speed = SPEED_1000;
2880 current_link_up = 1;
2881 if (bmcr & BMCR_FULLDPLX)
2882 current_duplex = DUPLEX_FULL;
2883 else
2884 current_duplex = DUPLEX_HALF;
2885
2886 if (bmcr & BMCR_ANENABLE) {
2887 u32 local_adv, remote_adv, common;
2888
2889 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2890 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2891 common = local_adv & remote_adv;
2892 if (common & (ADVERTISE_1000XHALF |
2893 ADVERTISE_1000XFULL)) {
2894 if (common & ADVERTISE_1000XFULL)
2895 current_duplex = DUPLEX_FULL;
2896 else
2897 current_duplex = DUPLEX_HALF;
2898
2899 tg3_setup_flow_control(tp, local_adv,
2900 remote_adv);
2901 }
2902 else
2903 current_link_up = 0;
2904 }
2905 }
2906
2907 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2908 if (tp->link_config.active_duplex == DUPLEX_HALF)
2909 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2910
2911 tw32_f(MAC_MODE, tp->mac_mode);
2912 udelay(40);
2913
2914 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2915
2916 tp->link_config.active_speed = current_speed;
2917 tp->link_config.active_duplex = current_duplex;
2918
2919 if (current_link_up != netif_carrier_ok(tp->dev)) {
2920 if (current_link_up)
2921 netif_carrier_on(tp->dev);
2922 else {
2923 netif_carrier_off(tp->dev);
2924 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2925 }
2926 tg3_link_report(tp);
2927 }
2928 return err;
2929 }
2930
2931 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2932 {
2933 if (tp->serdes_counter) {
2934 /* Give autoneg time to complete. */
2935 tp->serdes_counter--;
2936 return;
2937 }
2938 if (!netif_carrier_ok(tp->dev) &&
2939 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2940 u32 bmcr;
2941
2942 tg3_readphy(tp, MII_BMCR, &bmcr);
2943 if (bmcr & BMCR_ANENABLE) {
2944 u32 phy1, phy2;
2945
2946 /* Select shadow register 0x1f */
2947 tg3_writephy(tp, 0x1c, 0x7c00);
2948 tg3_readphy(tp, 0x1c, &phy1);
2949
2950 /* Select expansion interrupt status register */
2951 tg3_writephy(tp, 0x17, 0x0f01);
2952 tg3_readphy(tp, 0x15, &phy2);
2953 tg3_readphy(tp, 0x15, &phy2);
2954
2955 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2956 /* We have signal detect and not receiving
2957 * config code words, link is up by parallel
2958 * detection.
2959 */
2960
2961 bmcr &= ~BMCR_ANENABLE;
2962 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2963 tg3_writephy(tp, MII_BMCR, bmcr);
2964 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2965 }
2966 }
2967 }
2968 else if (netif_carrier_ok(tp->dev) &&
2969 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2970 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2971 u32 phy2;
2972
2973 /* Select expansion interrupt status register */
2974 tg3_writephy(tp, 0x17, 0x0f01);
2975 tg3_readphy(tp, 0x15, &phy2);
2976 if (phy2 & 0x20) {
2977 u32 bmcr;
2978
2979 /* Config code words received, turn on autoneg. */
2980 tg3_readphy(tp, MII_BMCR, &bmcr);
2981 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2982
2983 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2984
2985 }
2986 }
2987 }
2988
2989 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2990 {
2991 int err;
2992
2993 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2994 err = tg3_setup_fiber_phy(tp, force_reset);
2995 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2996 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2997 } else {
2998 err = tg3_setup_copper_phy(tp, force_reset);
2999 }
3000
3001 if (tp->link_config.active_speed == SPEED_1000 &&
3002 tp->link_config.active_duplex == DUPLEX_HALF)
3003 tw32(MAC_TX_LENGTHS,
3004 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3005 (6 << TX_LENGTHS_IPG_SHIFT) |
3006 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3007 else
3008 tw32(MAC_TX_LENGTHS,
3009 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3010 (6 << TX_LENGTHS_IPG_SHIFT) |
3011 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3012
3013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3014 if (netif_carrier_ok(tp->dev)) {
3015 tw32(HOSTCC_STAT_COAL_TICKS,
3016 tp->coal.stats_block_coalesce_usecs);
3017 } else {
3018 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3019 }
3020 }
3021
3022 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3023 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3024 if (!netif_carrier_ok(tp->dev))
3025 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3026 tp->pwrmgmt_thresh;
3027 else
3028 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3029 tw32(PCIE_PWR_MGMT_THRESH, val);
3030 }
3031
3032 return err;
3033 }
3034
3035 /* This is called whenever we suspect that the system chipset is re-
3036 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3037 * is bogus tx completions. We try to recover by setting the
3038 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3039 * in the workqueue.
3040 */
3041 static void tg3_tx_recover(struct tg3 *tp)
3042 {
3043 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3044 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3045
3046 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3047 "mapped I/O cycles to the network device, attempting to "
3048 "recover. Please report the problem to the driver maintainer "
3049 "and include system chipset information.\n", tp->dev->name);
3050
3051 spin_lock(&tp->lock);
3052 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3053 spin_unlock(&tp->lock);
3054 }
3055
3056 static inline u32 tg3_tx_avail(struct tg3 *tp)
3057 {
3058 smp_mb();
3059 return (tp->tx_pending -
3060 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3061 }
3062
3063 /* Tigon3 never reports partial packet sends. So we do not
3064 * need special logic to handle SKBs that have not had all
3065 * of their frags sent yet, like SunGEM does.
3066 */
3067 static void tg3_tx(struct tg3 *tp)
3068 {
3069 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3070 u32 sw_idx = tp->tx_cons;
3071
3072 while (sw_idx != hw_idx) {
3073 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3074 struct sk_buff *skb = ri->skb;
3075 int i, tx_bug = 0;
3076
3077 if (unlikely(skb == NULL)) {
3078 tg3_tx_recover(tp);
3079 return;
3080 }
3081
3082 pci_unmap_single(tp->pdev,
3083 pci_unmap_addr(ri, mapping),
3084 skb_headlen(skb),
3085 PCI_DMA_TODEVICE);
3086
3087 ri->skb = NULL;
3088
3089 sw_idx = NEXT_TX(sw_idx);
3090
3091 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3092 ri = &tp->tx_buffers[sw_idx];
3093 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3094 tx_bug = 1;
3095
3096 pci_unmap_page(tp->pdev,
3097 pci_unmap_addr(ri, mapping),
3098 skb_shinfo(skb)->frags[i].size,
3099 PCI_DMA_TODEVICE);
3100
3101 sw_idx = NEXT_TX(sw_idx);
3102 }
3103
3104 dev_kfree_skb(skb);
3105
3106 if (unlikely(tx_bug)) {
3107 tg3_tx_recover(tp);
3108 return;
3109 }
3110 }
3111
3112 tp->tx_cons = sw_idx;
3113
3114 /* Need to make the tx_cons update visible to tg3_start_xmit()
3115 * before checking for netif_queue_stopped(). Without the
3116 * memory barrier, there is a small possibility that tg3_start_xmit()
3117 * will miss it and cause the queue to be stopped forever.
3118 */
3119 smp_mb();
3120
3121 if (unlikely(netif_queue_stopped(tp->dev) &&
3122 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3123 netif_tx_lock(tp->dev);
3124 if (netif_queue_stopped(tp->dev) &&
3125 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3126 netif_wake_queue(tp->dev);
3127 netif_tx_unlock(tp->dev);
3128 }
3129 }
3130
3131 /* Returns size of skb allocated or < 0 on error.
3132 *
3133 * We only need to fill in the address because the other members
3134 * of the RX descriptor are invariant, see tg3_init_rings.
3135 *
3136 * Note the purposeful assymetry of cpu vs. chip accesses. For
3137 * posting buffers we only dirty the first cache line of the RX
3138 * descriptor (containing the address). Whereas for the RX status
3139 * buffers the cpu only reads the last cacheline of the RX descriptor
3140 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3141 */
3142 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3143 int src_idx, u32 dest_idx_unmasked)
3144 {
3145 struct tg3_rx_buffer_desc *desc;
3146 struct ring_info *map, *src_map;
3147 struct sk_buff *skb;
3148 dma_addr_t mapping;
3149 int skb_size, dest_idx;
3150
3151 src_map = NULL;
3152 switch (opaque_key) {
3153 case RXD_OPAQUE_RING_STD:
3154 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3155 desc = &tp->rx_std[dest_idx];
3156 map = &tp->rx_std_buffers[dest_idx];
3157 if (src_idx >= 0)
3158 src_map = &tp->rx_std_buffers[src_idx];
3159 skb_size = tp->rx_pkt_buf_sz;
3160 break;
3161
3162 case RXD_OPAQUE_RING_JUMBO:
3163 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3164 desc = &tp->rx_jumbo[dest_idx];
3165 map = &tp->rx_jumbo_buffers[dest_idx];
3166 if (src_idx >= 0)
3167 src_map = &tp->rx_jumbo_buffers[src_idx];
3168 skb_size = RX_JUMBO_PKT_BUF_SZ;
3169 break;
3170
3171 default:
3172 return -EINVAL;
3173 };
3174
3175 /* Do not overwrite any of the map or rp information
3176 * until we are sure we can commit to a new buffer.
3177 *
3178 * Callers depend upon this behavior and assume that
3179 * we leave everything unchanged if we fail.
3180 */
3181 skb = netdev_alloc_skb(tp->dev, skb_size);
3182 if (skb == NULL)
3183 return -ENOMEM;
3184
3185 skb_reserve(skb, tp->rx_offset);
3186
3187 mapping = pci_map_single(tp->pdev, skb->data,
3188 skb_size - tp->rx_offset,
3189 PCI_DMA_FROMDEVICE);
3190
3191 map->skb = skb;
3192 pci_unmap_addr_set(map, mapping, mapping);
3193
3194 if (src_map != NULL)
3195 src_map->skb = NULL;
3196
3197 desc->addr_hi = ((u64)mapping >> 32);
3198 desc->addr_lo = ((u64)mapping & 0xffffffff);
3199
3200 return skb_size;
3201 }
3202
3203 /* We only need to move over in the address because the other
3204 * members of the RX descriptor are invariant. See notes above
3205 * tg3_alloc_rx_skb for full details.
3206 */
3207 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3208 int src_idx, u32 dest_idx_unmasked)
3209 {
3210 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3211 struct ring_info *src_map, *dest_map;
3212 int dest_idx;
3213
3214 switch (opaque_key) {
3215 case RXD_OPAQUE_RING_STD:
3216 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3217 dest_desc = &tp->rx_std[dest_idx];
3218 dest_map = &tp->rx_std_buffers[dest_idx];
3219 src_desc = &tp->rx_std[src_idx];
3220 src_map = &tp->rx_std_buffers[src_idx];
3221 break;
3222
3223 case RXD_OPAQUE_RING_JUMBO:
3224 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3225 dest_desc = &tp->rx_jumbo[dest_idx];
3226 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3227 src_desc = &tp->rx_jumbo[src_idx];
3228 src_map = &tp->rx_jumbo_buffers[src_idx];
3229 break;
3230
3231 default:
3232 return;
3233 };
3234
3235 dest_map->skb = src_map->skb;
3236 pci_unmap_addr_set(dest_map, mapping,
3237 pci_unmap_addr(src_map, mapping));
3238 dest_desc->addr_hi = src_desc->addr_hi;
3239 dest_desc->addr_lo = src_desc->addr_lo;
3240
3241 src_map->skb = NULL;
3242 }
3243
3244 #if TG3_VLAN_TAG_USED
3245 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3246 {
3247 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3248 }
3249 #endif
3250
3251 /* The RX ring scheme is composed of multiple rings which post fresh
3252 * buffers to the chip, and one special ring the chip uses to report
3253 * status back to the host.
3254 *
3255 * The special ring reports the status of received packets to the
3256 * host. The chip does not write into the original descriptor the
3257 * RX buffer was obtained from. The chip simply takes the original
3258 * descriptor as provided by the host, updates the status and length
3259 * field, then writes this into the next status ring entry.
3260 *
3261 * Each ring the host uses to post buffers to the chip is described
3262 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3263 * it is first placed into the on-chip ram. When the packet's length
3264 * is known, it walks down the TG3_BDINFO entries to select the ring.
3265 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3266 * which is within the range of the new packet's length is chosen.
3267 *
3268 * The "separate ring for rx status" scheme may sound queer, but it makes
3269 * sense from a cache coherency perspective. If only the host writes
3270 * to the buffer post rings, and only the chip writes to the rx status
3271 * rings, then cache lines never move beyond shared-modified state.
3272 * If both the host and chip were to write into the same ring, cache line
3273 * eviction could occur since both entities want it in an exclusive state.
3274 */
3275 static int tg3_rx(struct tg3 *tp, int budget)
3276 {
3277 u32 work_mask, rx_std_posted = 0;
3278 u32 sw_idx = tp->rx_rcb_ptr;
3279 u16 hw_idx;
3280 int received;
3281
3282 hw_idx = tp->hw_status->idx[0].rx_producer;
3283 /*
3284 * We need to order the read of hw_idx and the read of
3285 * the opaque cookie.
3286 */
3287 rmb();
3288 work_mask = 0;
3289 received = 0;
3290 while (sw_idx != hw_idx && budget > 0) {
3291 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3292 unsigned int len;
3293 struct sk_buff *skb;
3294 dma_addr_t dma_addr;
3295 u32 opaque_key, desc_idx, *post_ptr;
3296
3297 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3298 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3299 if (opaque_key == RXD_OPAQUE_RING_STD) {
3300 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3301 mapping);
3302 skb = tp->rx_std_buffers[desc_idx].skb;
3303 post_ptr = &tp->rx_std_ptr;
3304 rx_std_posted++;
3305 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3306 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3307 mapping);
3308 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3309 post_ptr = &tp->rx_jumbo_ptr;
3310 }
3311 else {
3312 goto next_pkt_nopost;
3313 }
3314
3315 work_mask |= opaque_key;
3316
3317 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3318 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3319 drop_it:
3320 tg3_recycle_rx(tp, opaque_key,
3321 desc_idx, *post_ptr);
3322 drop_it_no_recycle:
3323 /* Other statistics kept track of by card. */
3324 tp->net_stats.rx_dropped++;
3325 goto next_pkt;
3326 }
3327
3328 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3329
3330 if (len > RX_COPY_THRESHOLD
3331 && tp->rx_offset == 2
3332 /* rx_offset != 2 iff this is a 5701 card running
3333 * in PCI-X mode [see tg3_get_invariants()] */
3334 ) {
3335 int skb_size;
3336
3337 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3338 desc_idx, *post_ptr);
3339 if (skb_size < 0)
3340 goto drop_it;
3341
3342 pci_unmap_single(tp->pdev, dma_addr,
3343 skb_size - tp->rx_offset,
3344 PCI_DMA_FROMDEVICE);
3345
3346 skb_put(skb, len);
3347 } else {
3348 struct sk_buff *copy_skb;
3349
3350 tg3_recycle_rx(tp, opaque_key,
3351 desc_idx, *post_ptr);
3352
3353 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3354 if (copy_skb == NULL)
3355 goto drop_it_no_recycle;
3356
3357 skb_reserve(copy_skb, 2);
3358 skb_put(copy_skb, len);
3359 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3360 skb_copy_from_linear_data(skb, copy_skb->data, len);
3361 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3362
3363 /* We'll reuse the original ring buffer. */
3364 skb = copy_skb;
3365 }
3366
3367 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3368 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3369 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3370 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3371 skb->ip_summed = CHECKSUM_UNNECESSARY;
3372 else
3373 skb->ip_summed = CHECKSUM_NONE;
3374
3375 skb->protocol = eth_type_trans(skb, tp->dev);
3376 #if TG3_VLAN_TAG_USED
3377 if (tp->vlgrp != NULL &&
3378 desc->type_flags & RXD_FLAG_VLAN) {
3379 tg3_vlan_rx(tp, skb,
3380 desc->err_vlan & RXD_VLAN_MASK);
3381 } else
3382 #endif
3383 netif_receive_skb(skb);
3384
3385 tp->dev->last_rx = jiffies;
3386 received++;
3387 budget--;
3388
3389 next_pkt:
3390 (*post_ptr)++;
3391
3392 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3393 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3394
3395 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3396 TG3_64BIT_REG_LOW, idx);
3397 work_mask &= ~RXD_OPAQUE_RING_STD;
3398 rx_std_posted = 0;
3399 }
3400 next_pkt_nopost:
3401 sw_idx++;
3402 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3403
3404 /* Refresh hw_idx to see if there is new work */
3405 if (sw_idx == hw_idx) {
3406 hw_idx = tp->hw_status->idx[0].rx_producer;
3407 rmb();
3408 }
3409 }
3410
3411 /* ACK the status ring. */
3412 tp->rx_rcb_ptr = sw_idx;
3413 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3414
3415 /* Refill RX ring(s). */
3416 if (work_mask & RXD_OPAQUE_RING_STD) {
3417 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3418 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3419 sw_idx);
3420 }
3421 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3422 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3423 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3424 sw_idx);
3425 }
3426 mmiowb();
3427
3428 return received;
3429 }
3430
3431 static int tg3_poll(struct net_device *netdev, int *budget)
3432 {
3433 struct tg3 *tp = netdev_priv(netdev);
3434 struct tg3_hw_status *sblk = tp->hw_status;
3435 int done;
3436
3437 /* handle link change and other phy events */
3438 if (!(tp->tg3_flags &
3439 (TG3_FLAG_USE_LINKCHG_REG |
3440 TG3_FLAG_POLL_SERDES))) {
3441 if (sblk->status & SD_STATUS_LINK_CHG) {
3442 sblk->status = SD_STATUS_UPDATED |
3443 (sblk->status & ~SD_STATUS_LINK_CHG);
3444 spin_lock(&tp->lock);
3445 tg3_setup_phy(tp, 0);
3446 spin_unlock(&tp->lock);
3447 }
3448 }
3449
3450 /* run TX completion thread */
3451 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3452 tg3_tx(tp);
3453 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3454 netif_rx_complete(netdev);
3455 schedule_work(&tp->reset_task);
3456 return 0;
3457 }
3458 }
3459
3460 /* run RX thread, within the bounds set by NAPI.
3461 * All RX "locking" is done by ensuring outside
3462 * code synchronizes with dev->poll()
3463 */
3464 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3465 int orig_budget = *budget;
3466 int work_done;
3467
3468 if (orig_budget > netdev->quota)
3469 orig_budget = netdev->quota;
3470
3471 work_done = tg3_rx(tp, orig_budget);
3472
3473 *budget -= work_done;
3474 netdev->quota -= work_done;
3475 }
3476
3477 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3478 tp->last_tag = sblk->status_tag;
3479 rmb();
3480 } else
3481 sblk->status &= ~SD_STATUS_UPDATED;
3482
3483 /* if no more work, tell net stack and NIC we're done */
3484 done = !tg3_has_work(tp);
3485 if (done) {
3486 netif_rx_complete(netdev);
3487 tg3_restart_ints(tp);
3488 }
3489
3490 return (done ? 0 : 1);
3491 }
3492
3493 static void tg3_irq_quiesce(struct tg3 *tp)
3494 {
3495 BUG_ON(tp->irq_sync);
3496
3497 tp->irq_sync = 1;
3498 smp_mb();
3499
3500 synchronize_irq(tp->pdev->irq);
3501 }
3502
3503 static inline int tg3_irq_sync(struct tg3 *tp)
3504 {
3505 return tp->irq_sync;
3506 }
3507
3508 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3509 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3510 * with as well. Most of the time, this is not necessary except when
3511 * shutting down the device.
3512 */
3513 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3514 {
3515 if (irq_sync)
3516 tg3_irq_quiesce(tp);
3517 spin_lock_bh(&tp->lock);
3518 }
3519
3520 static inline void tg3_full_unlock(struct tg3 *tp)
3521 {
3522 spin_unlock_bh(&tp->lock);
3523 }
3524
3525 /* One-shot MSI handler - Chip automatically disables interrupt
3526 * after sending MSI so driver doesn't have to do it.
3527 */
3528 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3529 {
3530 struct net_device *dev = dev_id;
3531 struct tg3 *tp = netdev_priv(dev);
3532
3533 prefetch(tp->hw_status);
3534 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3535
3536 if (likely(!tg3_irq_sync(tp)))
3537 netif_rx_schedule(dev); /* schedule NAPI poll */
3538
3539 return IRQ_HANDLED;
3540 }
3541
3542 /* MSI ISR - No need to check for interrupt sharing and no need to
3543 * flush status block and interrupt mailbox. PCI ordering rules
3544 * guarantee that MSI will arrive after the status block.
3545 */
3546 static irqreturn_t tg3_msi(int irq, void *dev_id)
3547 {
3548 struct net_device *dev = dev_id;
3549 struct tg3 *tp = netdev_priv(dev);
3550
3551 prefetch(tp->hw_status);
3552 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3553 /*
3554 * Writing any value to intr-mbox-0 clears PCI INTA# and
3555 * chip-internal interrupt pending events.
3556 * Writing non-zero to intr-mbox-0 additional tells the
3557 * NIC to stop sending us irqs, engaging "in-intr-handler"
3558 * event coalescing.
3559 */
3560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3561 if (likely(!tg3_irq_sync(tp)))
3562 netif_rx_schedule(dev); /* schedule NAPI poll */
3563
3564 return IRQ_RETVAL(1);
3565 }
3566
3567 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3568 {
3569 struct net_device *dev = dev_id;
3570 struct tg3 *tp = netdev_priv(dev);
3571 struct tg3_hw_status *sblk = tp->hw_status;
3572 unsigned int handled = 1;
3573
3574 /* In INTx mode, it is possible for the interrupt to arrive at
3575 * the CPU before the status block posted prior to the interrupt.
3576 * Reading the PCI State register will confirm whether the
3577 * interrupt is ours and will flush the status block.
3578 */
3579 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3580 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3581 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3582 handled = 0;
3583 goto out;
3584 }
3585 }
3586
3587 /*
3588 * Writing any value to intr-mbox-0 clears PCI INTA# and
3589 * chip-internal interrupt pending events.
3590 * Writing non-zero to intr-mbox-0 additional tells the
3591 * NIC to stop sending us irqs, engaging "in-intr-handler"
3592 * event coalescing.
3593 *
3594 * Flush the mailbox to de-assert the IRQ immediately to prevent
3595 * spurious interrupts. The flush impacts performance but
3596 * excessive spurious interrupts can be worse in some cases.
3597 */
3598 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3599 if (tg3_irq_sync(tp))
3600 goto out;
3601 sblk->status &= ~SD_STATUS_UPDATED;
3602 if (likely(tg3_has_work(tp))) {
3603 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3604 netif_rx_schedule(dev); /* schedule NAPI poll */
3605 } else {
3606 /* No work, shared interrupt perhaps? re-enable
3607 * interrupts, and flush that PCI write
3608 */
3609 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3610 0x00000000);
3611 }
3612 out:
3613 return IRQ_RETVAL(handled);
3614 }
3615
3616 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3617 {
3618 struct net_device *dev = dev_id;
3619 struct tg3 *tp = netdev_priv(dev);
3620 struct tg3_hw_status *sblk = tp->hw_status;
3621 unsigned int handled = 1;
3622
3623 /* In INTx mode, it is possible for the interrupt to arrive at
3624 * the CPU before the status block posted prior to the interrupt.
3625 * Reading the PCI State register will confirm whether the
3626 * interrupt is ours and will flush the status block.
3627 */
3628 if (unlikely(sblk->status_tag == tp->last_tag)) {
3629 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3630 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3631 handled = 0;
3632 goto out;
3633 }
3634 }
3635
3636 /*
3637 * writing any value to intr-mbox-0 clears PCI INTA# and
3638 * chip-internal interrupt pending events.
3639 * writing non-zero to intr-mbox-0 additional tells the
3640 * NIC to stop sending us irqs, engaging "in-intr-handler"
3641 * event coalescing.
3642 *
3643 * Flush the mailbox to de-assert the IRQ immediately to prevent
3644 * spurious interrupts. The flush impacts performance but
3645 * excessive spurious interrupts can be worse in some cases.
3646 */
3647 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3648 if (tg3_irq_sync(tp))
3649 goto out;
3650 if (netif_rx_schedule_prep(dev)) {
3651 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3652 /* Update last_tag to mark that this status has been
3653 * seen. Because interrupt may be shared, we may be
3654 * racing with tg3_poll(), so only update last_tag
3655 * if tg3_poll() is not scheduled.
3656 */
3657 tp->last_tag = sblk->status_tag;
3658 __netif_rx_schedule(dev);
3659 }
3660 out:
3661 return IRQ_RETVAL(handled);
3662 }
3663
3664 /* ISR for interrupt test */
3665 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3666 {
3667 struct net_device *dev = dev_id;
3668 struct tg3 *tp = netdev_priv(dev);
3669 struct tg3_hw_status *sblk = tp->hw_status;
3670
3671 if ((sblk->status & SD_STATUS_UPDATED) ||
3672 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3673 tg3_disable_ints(tp);
3674 return IRQ_RETVAL(1);
3675 }
3676 return IRQ_RETVAL(0);
3677 }
3678
3679 static int tg3_init_hw(struct tg3 *, int);
3680 static int tg3_halt(struct tg3 *, int, int);
3681
3682 /* Restart hardware after configuration changes, self-test, etc.
3683 * Invoked with tp->lock held.
3684 */
3685 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3686 {
3687 int err;
3688
3689 err = tg3_init_hw(tp, reset_phy);
3690 if (err) {
3691 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3692 "aborting.\n", tp->dev->name);
3693 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3694 tg3_full_unlock(tp);
3695 del_timer_sync(&tp->timer);
3696 tp->irq_sync = 0;
3697 netif_poll_enable(tp->dev);
3698 dev_close(tp->dev);
3699 tg3_full_lock(tp, 0);
3700 }
3701 return err;
3702 }
3703
3704 #ifdef CONFIG_NET_POLL_CONTROLLER
3705 static void tg3_poll_controller(struct net_device *dev)
3706 {
3707 struct tg3 *tp = netdev_priv(dev);
3708
3709 tg3_interrupt(tp->pdev->irq, dev);
3710 }
3711 #endif
3712
3713 static void tg3_reset_task(struct work_struct *work)
3714 {
3715 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3716 unsigned int restart_timer;
3717
3718 tg3_full_lock(tp, 0);
3719
3720 if (!netif_running(tp->dev)) {
3721 tg3_full_unlock(tp);
3722 return;
3723 }
3724
3725 tg3_full_unlock(tp);
3726
3727 tg3_netif_stop(tp);
3728
3729 tg3_full_lock(tp, 1);
3730
3731 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3732 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3733
3734 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3735 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3736 tp->write32_rx_mbox = tg3_write_flush_reg32;
3737 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3738 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3739 }
3740
3741 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3742 if (tg3_init_hw(tp, 1))
3743 goto out;
3744
3745 tg3_netif_start(tp);
3746
3747 if (restart_timer)
3748 mod_timer(&tp->timer, jiffies + 1);
3749
3750 out:
3751 tg3_full_unlock(tp);
3752 }
3753
3754 static void tg3_dump_short_state(struct tg3 *tp)
3755 {
3756 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3757 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3758 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3759 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3760 }
3761
3762 static void tg3_tx_timeout(struct net_device *dev)
3763 {
3764 struct tg3 *tp = netdev_priv(dev);
3765
3766 if (netif_msg_tx_err(tp)) {
3767 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3768 dev->name);
3769 tg3_dump_short_state(tp);
3770 }
3771
3772 schedule_work(&tp->reset_task);
3773 }
3774
3775 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3776 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3777 {
3778 u32 base = (u32) mapping & 0xffffffff;
3779
3780 return ((base > 0xffffdcc0) &&
3781 (base + len + 8 < base));
3782 }
3783
3784 /* Test for DMA addresses > 40-bit */
3785 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3786 int len)
3787 {
3788 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3789 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3790 return (((u64) mapping + len) > DMA_40BIT_MASK);
3791 return 0;
3792 #else
3793 return 0;
3794 #endif
3795 }
3796
3797 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3798
3799 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3800 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3801 u32 last_plus_one, u32 *start,
3802 u32 base_flags, u32 mss)
3803 {
3804 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3805 dma_addr_t new_addr = 0;
3806 u32 entry = *start;
3807 int i, ret = 0;
3808
3809 if (!new_skb) {
3810 ret = -1;
3811 } else {
3812 /* New SKB is guaranteed to be linear. */
3813 entry = *start;
3814 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3815 PCI_DMA_TODEVICE);
3816 /* Make sure new skb does not cross any 4G boundaries.
3817 * Drop the packet if it does.
3818 */
3819 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3820 ret = -1;
3821 dev_kfree_skb(new_skb);
3822 new_skb = NULL;
3823 } else {
3824 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3825 base_flags, 1 | (mss << 1));
3826 *start = NEXT_TX(entry);
3827 }
3828 }
3829
3830 /* Now clean up the sw ring entries. */
3831 i = 0;
3832 while (entry != last_plus_one) {
3833 int len;
3834
3835 if (i == 0)
3836 len = skb_headlen(skb);
3837 else
3838 len = skb_shinfo(skb)->frags[i-1].size;
3839 pci_unmap_single(tp->pdev,
3840 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3841 len, PCI_DMA_TODEVICE);
3842 if (i == 0) {
3843 tp->tx_buffers[entry].skb = new_skb;
3844 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3845 } else {
3846 tp->tx_buffers[entry].skb = NULL;
3847 }
3848 entry = NEXT_TX(entry);
3849 i++;
3850 }
3851
3852 dev_kfree_skb(skb);
3853
3854 return ret;
3855 }
3856
3857 static void tg3_set_txd(struct tg3 *tp, int entry,
3858 dma_addr_t mapping, int len, u32 flags,
3859 u32 mss_and_is_end)
3860 {
3861 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3862 int is_end = (mss_and_is_end & 0x1);
3863 u32 mss = (mss_and_is_end >> 1);
3864 u32 vlan_tag = 0;
3865
3866 if (is_end)
3867 flags |= TXD_FLAG_END;
3868 if (flags & TXD_FLAG_VLAN) {
3869 vlan_tag = flags >> 16;
3870 flags &= 0xffff;
3871 }
3872 vlan_tag |= (mss << TXD_MSS_SHIFT);
3873
3874 txd->addr_hi = ((u64) mapping >> 32);
3875 txd->addr_lo = ((u64) mapping & 0xffffffff);
3876 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3877 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3878 }
3879
3880 /* hard_start_xmit for devices that don't have any bugs and
3881 * support TG3_FLG2_HW_TSO_2 only.
3882 */
3883 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3884 {
3885 struct tg3 *tp = netdev_priv(dev);
3886 dma_addr_t mapping;
3887 u32 len, entry, base_flags, mss;
3888
3889 len = skb_headlen(skb);
3890
3891 /* We are running in BH disabled context with netif_tx_lock
3892 * and TX reclaim runs via tp->poll inside of a software
3893 * interrupt. Furthermore, IRQ processing runs lockless so we have
3894 * no IRQ context deadlocks to worry about either. Rejoice!
3895 */
3896 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3897 if (!netif_queue_stopped(dev)) {
3898 netif_stop_queue(dev);
3899
3900 /* This is a hard error, log it. */
3901 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3902 "queue awake!\n", dev->name);
3903 }
3904 return NETDEV_TX_BUSY;
3905 }
3906
3907 entry = tp->tx_prod;
3908 base_flags = 0;
3909 mss = 0;
3910 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3911 int tcp_opt_len, ip_tcp_len;
3912
3913 if (skb_header_cloned(skb) &&
3914 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3915 dev_kfree_skb(skb);
3916 goto out_unlock;
3917 }
3918
3919 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3920 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3921 else {
3922 struct iphdr *iph = ip_hdr(skb);
3923
3924 tcp_opt_len = tcp_optlen(skb);
3925 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3926
3927 iph->check = 0;
3928 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3929 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3930 }
3931
3932 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3933 TXD_FLAG_CPU_POST_DMA);
3934
3935 tcp_hdr(skb)->check = 0;
3936
3937 }
3938 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3939 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3940 #if TG3_VLAN_TAG_USED
3941 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3942 base_flags |= (TXD_FLAG_VLAN |
3943 (vlan_tx_tag_get(skb) << 16));
3944 #endif
3945
3946 /* Queue skb data, a.k.a. the main skb fragment. */
3947 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3948
3949 tp->tx_buffers[entry].skb = skb;
3950 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3951
3952 tg3_set_txd(tp, entry, mapping, len, base_flags,
3953 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3954
3955 entry = NEXT_TX(entry);
3956
3957 /* Now loop through additional data fragments, and queue them. */
3958 if (skb_shinfo(skb)->nr_frags > 0) {
3959 unsigned int i, last;
3960
3961 last = skb_shinfo(skb)->nr_frags - 1;
3962 for (i = 0; i <= last; i++) {
3963 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3964
3965 len = frag->size;
3966 mapping = pci_map_page(tp->pdev,
3967 frag->page,
3968 frag->page_offset,
3969 len, PCI_DMA_TODEVICE);
3970
3971 tp->tx_buffers[entry].skb = NULL;
3972 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3973
3974 tg3_set_txd(tp, entry, mapping, len,
3975 base_flags, (i == last) | (mss << 1));
3976
3977 entry = NEXT_TX(entry);
3978 }
3979 }
3980
3981 /* Packets are ready, update Tx producer idx local and on card. */
3982 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3983
3984 tp->tx_prod = entry;
3985 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3986 netif_stop_queue(dev);
3987 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3988 netif_wake_queue(tp->dev);
3989 }
3990
3991 out_unlock:
3992 mmiowb();
3993
3994 dev->trans_start = jiffies;
3995
3996 return NETDEV_TX_OK;
3997 }
3998
3999 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4000
4001 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4002 * TSO header is greater than 80 bytes.
4003 */
4004 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4005 {
4006 struct sk_buff *segs, *nskb;
4007
4008 /* Estimate the number of fragments in the worst case */
4009 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4010 netif_stop_queue(tp->dev);
4011 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4012 return NETDEV_TX_BUSY;
4013
4014 netif_wake_queue(tp->dev);
4015 }
4016
4017 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4018 if (unlikely(IS_ERR(segs)))
4019 goto tg3_tso_bug_end;
4020
4021 do {
4022 nskb = segs;
4023 segs = segs->next;
4024 nskb->next = NULL;
4025 tg3_start_xmit_dma_bug(nskb, tp->dev);
4026 } while (segs);
4027
4028 tg3_tso_bug_end:
4029 dev_kfree_skb(skb);
4030
4031 return NETDEV_TX_OK;
4032 }
4033
4034 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4035 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4036 */
4037 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4038 {
4039 struct tg3 *tp = netdev_priv(dev);
4040 dma_addr_t mapping;
4041 u32 len, entry, base_flags, mss;
4042 int would_hit_hwbug;
4043
4044 len = skb_headlen(skb);
4045
4046 /* We are running in BH disabled context with netif_tx_lock
4047 * and TX reclaim runs via tp->poll inside of a software
4048 * interrupt. Furthermore, IRQ processing runs lockless so we have
4049 * no IRQ context deadlocks to worry about either. Rejoice!
4050 */
4051 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4052 if (!netif_queue_stopped(dev)) {
4053 netif_stop_queue(dev);
4054
4055 /* This is a hard error, log it. */
4056 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4057 "queue awake!\n", dev->name);
4058 }
4059 return NETDEV_TX_BUSY;
4060 }
4061
4062 entry = tp->tx_prod;
4063 base_flags = 0;
4064 if (skb->ip_summed == CHECKSUM_PARTIAL)
4065 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4066 mss = 0;
4067 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4068 struct iphdr *iph;
4069 int tcp_opt_len, ip_tcp_len, hdr_len;
4070
4071 if (skb_header_cloned(skb) &&
4072 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4073 dev_kfree_skb(skb);
4074 goto out_unlock;
4075 }
4076
4077 tcp_opt_len = tcp_optlen(skb);
4078 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4079
4080 hdr_len = ip_tcp_len + tcp_opt_len;
4081 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4082 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4083 return (tg3_tso_bug(tp, skb));
4084
4085 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4086 TXD_FLAG_CPU_POST_DMA);
4087
4088 iph = ip_hdr(skb);
4089 iph->check = 0;
4090 iph->tot_len = htons(mss + hdr_len);
4091 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4092 tcp_hdr(skb)->check = 0;
4093 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4094 } else
4095 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4096 iph->daddr, 0,
4097 IPPROTO_TCP,
4098 0);
4099
4100 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4101 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4102 if (tcp_opt_len || iph->ihl > 5) {
4103 int tsflags;
4104
4105 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4106 mss |= (tsflags << 11);
4107 }
4108 } else {
4109 if (tcp_opt_len || iph->ihl > 5) {
4110 int tsflags;
4111
4112 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4113 base_flags |= tsflags << 12;
4114 }
4115 }
4116 }
4117 #if TG3_VLAN_TAG_USED
4118 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4119 base_flags |= (TXD_FLAG_VLAN |
4120 (vlan_tx_tag_get(skb) << 16));
4121 #endif
4122
4123 /* Queue skb data, a.k.a. the main skb fragment. */
4124 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4125
4126 tp->tx_buffers[entry].skb = skb;
4127 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4128
4129 would_hit_hwbug = 0;
4130
4131 if (tg3_4g_overflow_test(mapping, len))
4132 would_hit_hwbug = 1;
4133
4134 tg3_set_txd(tp, entry, mapping, len, base_flags,
4135 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4136
4137 entry = NEXT_TX(entry);
4138
4139 /* Now loop through additional data fragments, and queue them. */
4140 if (skb_shinfo(skb)->nr_frags > 0) {
4141 unsigned int i, last;
4142
4143 last = skb_shinfo(skb)->nr_frags - 1;
4144 for (i = 0; i <= last; i++) {
4145 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4146
4147 len = frag->size;
4148 mapping = pci_map_page(tp->pdev,
4149 frag->page,
4150 frag->page_offset,
4151 len, PCI_DMA_TODEVICE);
4152
4153 tp->tx_buffers[entry].skb = NULL;
4154 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4155
4156 if (tg3_4g_overflow_test(mapping, len))
4157 would_hit_hwbug = 1;
4158
4159 if (tg3_40bit_overflow_test(tp, mapping, len))
4160 would_hit_hwbug = 1;
4161
4162 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4163 tg3_set_txd(tp, entry, mapping, len,
4164 base_flags, (i == last)|(mss << 1));
4165 else
4166 tg3_set_txd(tp, entry, mapping, len,
4167 base_flags, (i == last));
4168
4169 entry = NEXT_TX(entry);
4170 }
4171 }
4172
4173 if (would_hit_hwbug) {
4174 u32 last_plus_one = entry;
4175 u32 start;
4176
4177 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4178 start &= (TG3_TX_RING_SIZE - 1);
4179
4180 /* If the workaround fails due to memory/mapping
4181 * failure, silently drop this packet.
4182 */
4183 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4184 &start, base_flags, mss))
4185 goto out_unlock;
4186
4187 entry = start;
4188 }
4189
4190 /* Packets are ready, update Tx producer idx local and on card. */
4191 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4192
4193 tp->tx_prod = entry;
4194 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4195 netif_stop_queue(dev);
4196 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4197 netif_wake_queue(tp->dev);
4198 }
4199
4200 out_unlock:
4201 mmiowb();
4202
4203 dev->trans_start = jiffies;
4204
4205 return NETDEV_TX_OK;
4206 }
4207
4208 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4209 int new_mtu)
4210 {
4211 dev->mtu = new_mtu;
4212
4213 if (new_mtu > ETH_DATA_LEN) {
4214 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4215 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4216 ethtool_op_set_tso(dev, 0);
4217 }
4218 else
4219 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4220 } else {
4221 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4222 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4223 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4224 }
4225 }
4226
4227 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4228 {
4229 struct tg3 *tp = netdev_priv(dev);
4230 int err;
4231
4232 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4233 return -EINVAL;
4234
4235 if (!netif_running(dev)) {
4236 /* We'll just catch it later when the
4237 * device is up'd.
4238 */
4239 tg3_set_mtu(dev, tp, new_mtu);
4240 return 0;
4241 }
4242
4243 tg3_netif_stop(tp);
4244
4245 tg3_full_lock(tp, 1);
4246
4247 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4248
4249 tg3_set_mtu(dev, tp, new_mtu);
4250
4251 err = tg3_restart_hw(tp, 0);
4252
4253 if (!err)
4254 tg3_netif_start(tp);
4255
4256 tg3_full_unlock(tp);
4257
4258 return err;
4259 }
4260
4261 /* Free up pending packets in all rx/tx rings.
4262 *
4263 * The chip has been shut down and the driver detached from
4264 * the networking, so no interrupts or new tx packets will
4265 * end up in the driver. tp->{tx,}lock is not held and we are not
4266 * in an interrupt context and thus may sleep.
4267 */
4268 static void tg3_free_rings(struct tg3 *tp)
4269 {
4270 struct ring_info *rxp;
4271 int i;
4272
4273 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4274 rxp = &tp->rx_std_buffers[i];
4275
4276 if (rxp->skb == NULL)
4277 continue;
4278 pci_unmap_single(tp->pdev,
4279 pci_unmap_addr(rxp, mapping),
4280 tp->rx_pkt_buf_sz - tp->rx_offset,
4281 PCI_DMA_FROMDEVICE);
4282 dev_kfree_skb_any(rxp->skb);
4283 rxp->skb = NULL;
4284 }
4285
4286 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4287 rxp = &tp->rx_jumbo_buffers[i];
4288
4289 if (rxp->skb == NULL)
4290 continue;
4291 pci_unmap_single(tp->pdev,
4292 pci_unmap_addr(rxp, mapping),
4293 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4294 PCI_DMA_FROMDEVICE);
4295 dev_kfree_skb_any(rxp->skb);
4296 rxp->skb = NULL;
4297 }
4298
4299 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4300 struct tx_ring_info *txp;
4301 struct sk_buff *skb;
4302 int j;
4303
4304 txp = &tp->tx_buffers[i];
4305 skb = txp->skb;
4306
4307 if (skb == NULL) {
4308 i++;
4309 continue;
4310 }
4311
4312 pci_unmap_single(tp->pdev,
4313 pci_unmap_addr(txp, mapping),
4314 skb_headlen(skb),
4315 PCI_DMA_TODEVICE);
4316 txp->skb = NULL;
4317
4318 i++;
4319
4320 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4321 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4322 pci_unmap_page(tp->pdev,
4323 pci_unmap_addr(txp, mapping),
4324 skb_shinfo(skb)->frags[j].size,
4325 PCI_DMA_TODEVICE);
4326 i++;
4327 }
4328
4329 dev_kfree_skb_any(skb);
4330 }
4331 }
4332
4333 /* Initialize tx/rx rings for packet processing.
4334 *
4335 * The chip has been shut down and the driver detached from
4336 * the networking, so no interrupts or new tx packets will
4337 * end up in the driver. tp->{tx,}lock are held and thus
4338 * we may not sleep.
4339 */
4340 static int tg3_init_rings(struct tg3 *tp)
4341 {
4342 u32 i;
4343
4344 /* Free up all the SKBs. */
4345 tg3_free_rings(tp);
4346
4347 /* Zero out all descriptors. */
4348 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4349 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4350 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4351 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4352
4353 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4354 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4355 (tp->dev->mtu > ETH_DATA_LEN))
4356 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4357
4358 /* Initialize invariants of the rings, we only set this
4359 * stuff once. This works because the card does not
4360 * write into the rx buffer posting rings.
4361 */
4362 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4363 struct tg3_rx_buffer_desc *rxd;
4364
4365 rxd = &tp->rx_std[i];
4366 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4367 << RXD_LEN_SHIFT;
4368 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4369 rxd->opaque = (RXD_OPAQUE_RING_STD |
4370 (i << RXD_OPAQUE_INDEX_SHIFT));
4371 }
4372
4373 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4374 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4375 struct tg3_rx_buffer_desc *rxd;
4376
4377 rxd = &tp->rx_jumbo[i];
4378 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4379 << RXD_LEN_SHIFT;
4380 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4381 RXD_FLAG_JUMBO;
4382 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4383 (i << RXD_OPAQUE_INDEX_SHIFT));
4384 }
4385 }
4386
4387 /* Now allocate fresh SKBs for each rx ring. */
4388 for (i = 0; i < tp->rx_pending; i++) {
4389 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4390 printk(KERN_WARNING PFX
4391 "%s: Using a smaller RX standard ring, "
4392 "only %d out of %d buffers were allocated "
4393 "successfully.\n",
4394 tp->dev->name, i, tp->rx_pending);
4395 if (i == 0)
4396 return -ENOMEM;
4397 tp->rx_pending = i;
4398 break;
4399 }
4400 }
4401
4402 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4403 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4404 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4405 -1, i) < 0) {
4406 printk(KERN_WARNING PFX
4407 "%s: Using a smaller RX jumbo ring, "
4408 "only %d out of %d buffers were "
4409 "allocated successfully.\n",
4410 tp->dev->name, i, tp->rx_jumbo_pending);
4411 if (i == 0) {
4412 tg3_free_rings(tp);
4413 return -ENOMEM;
4414 }
4415 tp->rx_jumbo_pending = i;
4416 break;
4417 }
4418 }
4419 }
4420 return 0;
4421 }
4422
4423 /*
4424 * Must not be invoked with interrupt sources disabled and
4425 * the hardware shutdown down.
4426 */
4427 static void tg3_free_consistent(struct tg3 *tp)
4428 {
4429 kfree(tp->rx_std_buffers);
4430 tp->rx_std_buffers = NULL;
4431 if (tp->rx_std) {
4432 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4433 tp->rx_std, tp->rx_std_mapping);
4434 tp->rx_std = NULL;
4435 }
4436 if (tp->rx_jumbo) {
4437 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4438 tp->rx_jumbo, tp->rx_jumbo_mapping);
4439 tp->rx_jumbo = NULL;
4440 }
4441 if (tp->rx_rcb) {
4442 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4443 tp->rx_rcb, tp->rx_rcb_mapping);
4444 tp->rx_rcb = NULL;
4445 }
4446 if (tp->tx_ring) {
4447 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4448 tp->tx_ring, tp->tx_desc_mapping);
4449 tp->tx_ring = NULL;
4450 }
4451 if (tp->hw_status) {
4452 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4453 tp->hw_status, tp->status_mapping);
4454 tp->hw_status = NULL;
4455 }
4456 if (tp->hw_stats) {
4457 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4458 tp->hw_stats, tp->stats_mapping);
4459 tp->hw_stats = NULL;
4460 }
4461 }
4462
4463 /*
4464 * Must not be invoked with interrupt sources disabled and
4465 * the hardware shutdown down. Can sleep.
4466 */
4467 static int tg3_alloc_consistent(struct tg3 *tp)
4468 {
4469 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4470 (TG3_RX_RING_SIZE +
4471 TG3_RX_JUMBO_RING_SIZE)) +
4472 (sizeof(struct tx_ring_info) *
4473 TG3_TX_RING_SIZE),
4474 GFP_KERNEL);
4475 if (!tp->rx_std_buffers)
4476 return -ENOMEM;
4477
4478 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4479 tp->tx_buffers = (struct tx_ring_info *)
4480 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4481
4482 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4483 &tp->rx_std_mapping);
4484 if (!tp->rx_std)
4485 goto err_out;
4486
4487 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4488 &tp->rx_jumbo_mapping);
4489
4490 if (!tp->rx_jumbo)
4491 goto err_out;
4492
4493 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4494 &tp->rx_rcb_mapping);
4495 if (!tp->rx_rcb)
4496 goto err_out;
4497
4498 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4499 &tp->tx_desc_mapping);
4500 if (!tp->tx_ring)
4501 goto err_out;
4502
4503 tp->hw_status = pci_alloc_consistent(tp->pdev,
4504 TG3_HW_STATUS_SIZE,
4505 &tp->status_mapping);
4506 if (!tp->hw_status)
4507 goto err_out;
4508
4509 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4510 sizeof(struct tg3_hw_stats),
4511 &tp->stats_mapping);
4512 if (!tp->hw_stats)
4513 goto err_out;
4514
4515 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4516 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4517
4518 return 0;
4519
4520 err_out:
4521 tg3_free_consistent(tp);
4522 return -ENOMEM;
4523 }
4524
4525 #define MAX_WAIT_CNT 1000
4526
4527 /* To stop a block, clear the enable bit and poll till it
4528 * clears. tp->lock is held.
4529 */
4530 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4531 {
4532 unsigned int i;
4533 u32 val;
4534
4535 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4536 switch (ofs) {
4537 case RCVLSC_MODE:
4538 case DMAC_MODE:
4539 case MBFREE_MODE:
4540 case BUFMGR_MODE:
4541 case MEMARB_MODE:
4542 /* We can't enable/disable these bits of the
4543 * 5705/5750, just say success.
4544 */
4545 return 0;
4546
4547 default:
4548 break;
4549 };
4550 }
4551
4552 val = tr32(ofs);
4553 val &= ~enable_bit;
4554 tw32_f(ofs, val);
4555
4556 for (i = 0; i < MAX_WAIT_CNT; i++) {
4557 udelay(100);
4558 val = tr32(ofs);
4559 if ((val & enable_bit) == 0)
4560 break;
4561 }
4562
4563 if (i == MAX_WAIT_CNT && !silent) {
4564 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4565 "ofs=%lx enable_bit=%x\n",
4566 ofs, enable_bit);
4567 return -ENODEV;
4568 }
4569
4570 return 0;
4571 }
4572
4573 /* tp->lock is held. */
4574 static int tg3_abort_hw(struct tg3 *tp, int silent)
4575 {
4576 int i, err;
4577
4578 tg3_disable_ints(tp);
4579
4580 tp->rx_mode &= ~RX_MODE_ENABLE;
4581 tw32_f(MAC_RX_MODE, tp->rx_mode);
4582 udelay(10);
4583
4584 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4585 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4586 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4587 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4588 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4589 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4590
4591 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4592 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4593 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4594 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4595 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4596 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4597 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4598
4599 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4600 tw32_f(MAC_MODE, tp->mac_mode);
4601 udelay(40);
4602
4603 tp->tx_mode &= ~TX_MODE_ENABLE;
4604 tw32_f(MAC_TX_MODE, tp->tx_mode);
4605
4606 for (i = 0; i < MAX_WAIT_CNT; i++) {
4607 udelay(100);
4608 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4609 break;
4610 }
4611 if (i >= MAX_WAIT_CNT) {
4612 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4613 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4614 tp->dev->name, tr32(MAC_TX_MODE));
4615 err |= -ENODEV;
4616 }
4617
4618 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4619 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4620 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4621
4622 tw32(FTQ_RESET, 0xffffffff);
4623 tw32(FTQ_RESET, 0x00000000);
4624
4625 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4626 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4627
4628 if (tp->hw_status)
4629 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4630 if (tp->hw_stats)
4631 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4632
4633 return err;
4634 }
4635
4636 /* tp->lock is held. */
4637 static int tg3_nvram_lock(struct tg3 *tp)
4638 {
4639 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4640 int i;
4641
4642 if (tp->nvram_lock_cnt == 0) {
4643 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4644 for (i = 0; i < 8000; i++) {
4645 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4646 break;
4647 udelay(20);
4648 }
4649 if (i == 8000) {
4650 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4651 return -ENODEV;
4652 }
4653 }
4654 tp->nvram_lock_cnt++;
4655 }
4656 return 0;
4657 }
4658
4659 /* tp->lock is held. */
4660 static void tg3_nvram_unlock(struct tg3 *tp)
4661 {
4662 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4663 if (tp->nvram_lock_cnt > 0)
4664 tp->nvram_lock_cnt--;
4665 if (tp->nvram_lock_cnt == 0)
4666 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4667 }
4668 }
4669
4670 /* tp->lock is held. */
4671 static void tg3_enable_nvram_access(struct tg3 *tp)
4672 {
4673 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4674 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4675 u32 nvaccess = tr32(NVRAM_ACCESS);
4676
4677 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4678 }
4679 }
4680
4681 /* tp->lock is held. */
4682 static void tg3_disable_nvram_access(struct tg3 *tp)
4683 {
4684 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4685 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4686 u32 nvaccess = tr32(NVRAM_ACCESS);
4687
4688 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4689 }
4690 }
4691
4692 /* tp->lock is held. */
4693 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4694 {
4695 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4696 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4697
4698 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4699 switch (kind) {
4700 case RESET_KIND_INIT:
4701 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4702 DRV_STATE_START);
4703 break;
4704
4705 case RESET_KIND_SHUTDOWN:
4706 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4707 DRV_STATE_UNLOAD);
4708 break;
4709
4710 case RESET_KIND_SUSPEND:
4711 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4712 DRV_STATE_SUSPEND);
4713 break;
4714
4715 default:
4716 break;
4717 };
4718 }
4719 }
4720
4721 /* tp->lock is held. */
4722 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4723 {
4724 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4725 switch (kind) {
4726 case RESET_KIND_INIT:
4727 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4728 DRV_STATE_START_DONE);
4729 break;
4730
4731 case RESET_KIND_SHUTDOWN:
4732 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4733 DRV_STATE_UNLOAD_DONE);
4734 break;
4735
4736 default:
4737 break;
4738 };
4739 }
4740 }
4741
4742 /* tp->lock is held. */
4743 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4744 {
4745 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4746 switch (kind) {
4747 case RESET_KIND_INIT:
4748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4749 DRV_STATE_START);
4750 break;
4751
4752 case RESET_KIND_SHUTDOWN:
4753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4754 DRV_STATE_UNLOAD);
4755 break;
4756
4757 case RESET_KIND_SUSPEND:
4758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4759 DRV_STATE_SUSPEND);
4760 break;
4761
4762 default:
4763 break;
4764 };
4765 }
4766 }
4767
4768 static int tg3_poll_fw(struct tg3 *tp)
4769 {
4770 int i;
4771 u32 val;
4772
4773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4774 /* Wait up to 20ms for init done. */
4775 for (i = 0; i < 200; i++) {
4776 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4777 return 0;
4778 udelay(100);
4779 }
4780 return -ENODEV;
4781 }
4782
4783 /* Wait for firmware initialization to complete. */
4784 for (i = 0; i < 100000; i++) {
4785 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4786 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4787 break;
4788 udelay(10);
4789 }
4790
4791 /* Chip might not be fitted with firmware. Some Sun onboard
4792 * parts are configured like that. So don't signal the timeout
4793 * of the above loop as an error, but do report the lack of
4794 * running firmware once.
4795 */
4796 if (i >= 100000 &&
4797 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4798 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4799
4800 printk(KERN_INFO PFX "%s: No firmware running.\n",
4801 tp->dev->name);
4802 }
4803
4804 return 0;
4805 }
4806
4807 static void tg3_stop_fw(struct tg3 *);
4808
4809 /* tp->lock is held. */
4810 static int tg3_chip_reset(struct tg3 *tp)
4811 {
4812 u32 val;
4813 void (*write_op)(struct tg3 *, u32, u32);
4814 int err;
4815
4816 tg3_nvram_lock(tp);
4817
4818 /* No matching tg3_nvram_unlock() after this because
4819 * chip reset below will undo the nvram lock.
4820 */
4821 tp->nvram_lock_cnt = 0;
4822
4823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4826 tw32(GRC_FASTBOOT_PC, 0);
4827
4828 /*
4829 * We must avoid the readl() that normally takes place.
4830 * It locks machines, causes machine checks, and other
4831 * fun things. So, temporarily disable the 5701
4832 * hardware workaround, while we do the reset.
4833 */
4834 write_op = tp->write32;
4835 if (write_op == tg3_write_flush_reg32)
4836 tp->write32 = tg3_write32;
4837
4838 /* Prevent the irq handler from reading or writing PCI registers
4839 * during chip reset when the memory enable bit in the PCI command
4840 * register may be cleared. The chip does not generate interrupt
4841 * at this time, but the irq handler may still be called due to irq
4842 * sharing or irqpoll.
4843 */
4844 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4845 if (tp->hw_status) {
4846 tp->hw_status->status = 0;
4847 tp->hw_status->status_tag = 0;
4848 }
4849 tp->last_tag = 0;
4850 smp_mb();
4851 synchronize_irq(tp->pdev->irq);
4852
4853 /* do the reset */
4854 val = GRC_MISC_CFG_CORECLK_RESET;
4855
4856 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4857 if (tr32(0x7e2c) == 0x60) {
4858 tw32(0x7e2c, 0x20);
4859 }
4860 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4861 tw32(GRC_MISC_CFG, (1 << 29));
4862 val |= (1 << 29);
4863 }
4864 }
4865
4866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4867 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4868 tw32(GRC_VCPU_EXT_CTRL,
4869 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4870 }
4871
4872 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4873 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4874 tw32(GRC_MISC_CFG, val);
4875
4876 /* restore 5701 hardware bug workaround write method */
4877 tp->write32 = write_op;
4878
4879 /* Unfortunately, we have to delay before the PCI read back.
4880 * Some 575X chips even will not respond to a PCI cfg access
4881 * when the reset command is given to the chip.
4882 *
4883 * How do these hardware designers expect things to work
4884 * properly if the PCI write is posted for a long period
4885 * of time? It is always necessary to have some method by
4886 * which a register read back can occur to push the write
4887 * out which does the reset.
4888 *
4889 * For most tg3 variants the trick below was working.
4890 * Ho hum...
4891 */
4892 udelay(120);
4893
4894 /* Flush PCI posted writes. The normal MMIO registers
4895 * are inaccessible at this time so this is the only
4896 * way to make this reliably (actually, this is no longer
4897 * the case, see above). I tried to use indirect
4898 * register read/write but this upset some 5701 variants.
4899 */
4900 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4901
4902 udelay(120);
4903
4904 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4905 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4906 int i;
4907 u32 cfg_val;
4908
4909 /* Wait for link training to complete. */
4910 for (i = 0; i < 5000; i++)
4911 udelay(100);
4912
4913 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4914 pci_write_config_dword(tp->pdev, 0xc4,
4915 cfg_val | (1 << 15));
4916 }
4917 /* Set PCIE max payload size and clear error status. */
4918 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4919 }
4920
4921 /* Re-enable indirect register accesses. */
4922 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4923 tp->misc_host_ctrl);
4924
4925 /* Set MAX PCI retry to zero. */
4926 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4927 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4928 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4929 val |= PCISTATE_RETRY_SAME_DMA;
4930 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4931
4932 pci_restore_state(tp->pdev);
4933
4934 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4935
4936 /* Make sure PCI-X relaxed ordering bit is clear. */
4937 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4938 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4939 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4940
4941 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4942 u32 val;
4943
4944 /* Chip reset on 5780 will reset MSI enable bit,
4945 * so need to restore it.
4946 */
4947 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4948 u16 ctrl;
4949
4950 pci_read_config_word(tp->pdev,
4951 tp->msi_cap + PCI_MSI_FLAGS,
4952 &ctrl);
4953 pci_write_config_word(tp->pdev,
4954 tp->msi_cap + PCI_MSI_FLAGS,
4955 ctrl | PCI_MSI_FLAGS_ENABLE);
4956 val = tr32(MSGINT_MODE);
4957 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4958 }
4959
4960 val = tr32(MEMARB_MODE);
4961 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4962
4963 } else
4964 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4965
4966 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4967 tg3_stop_fw(tp);
4968 tw32(0x5000, 0x400);
4969 }
4970
4971 tw32(GRC_MODE, tp->grc_mode);
4972
4973 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4974 u32 val = tr32(0xc4);
4975
4976 tw32(0xc4, val | (1 << 15));
4977 }
4978
4979 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4981 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4982 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4983 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4984 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4985 }
4986
4987 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4988 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4989 tw32_f(MAC_MODE, tp->mac_mode);
4990 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4991 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4992 tw32_f(MAC_MODE, tp->mac_mode);
4993 } else
4994 tw32_f(MAC_MODE, 0);
4995 udelay(40);
4996
4997 err = tg3_poll_fw(tp);
4998 if (err)
4999 return err;
5000
5001 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5002 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5003 u32 val = tr32(0x7c00);
5004
5005 tw32(0x7c00, val | (1 << 25));
5006 }
5007
5008 /* Reprobe ASF enable state. */
5009 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5010 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5011 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5012 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5013 u32 nic_cfg;
5014
5015 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5016 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5017 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5018 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5019 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5020 }
5021 }
5022
5023 return 0;
5024 }
5025
5026 /* tp->lock is held. */
5027 static void tg3_stop_fw(struct tg3 *tp)
5028 {
5029 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5030 u32 val;
5031 int i;
5032
5033 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5034 val = tr32(GRC_RX_CPU_EVENT);
5035 val |= (1 << 14);
5036 tw32(GRC_RX_CPU_EVENT, val);
5037
5038 /* Wait for RX cpu to ACK the event. */
5039 for (i = 0; i < 100; i++) {
5040 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5041 break;
5042 udelay(1);
5043 }
5044 }
5045 }
5046
5047 /* tp->lock is held. */
5048 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5049 {
5050 int err;
5051
5052 tg3_stop_fw(tp);
5053
5054 tg3_write_sig_pre_reset(tp, kind);
5055
5056 tg3_abort_hw(tp, silent);
5057 err = tg3_chip_reset(tp);
5058
5059 tg3_write_sig_legacy(tp, kind);
5060 tg3_write_sig_post_reset(tp, kind);
5061
5062 if (err)
5063 return err;
5064
5065 return 0;
5066 }
5067
5068 #define TG3_FW_RELEASE_MAJOR 0x0
5069 #define TG3_FW_RELASE_MINOR 0x0
5070 #define TG3_FW_RELEASE_FIX 0x0
5071 #define TG3_FW_START_ADDR 0x08000000
5072 #define TG3_FW_TEXT_ADDR 0x08000000
5073 #define TG3_FW_TEXT_LEN 0x9c0
5074 #define TG3_FW_RODATA_ADDR 0x080009c0
5075 #define TG3_FW_RODATA_LEN 0x60
5076 #define TG3_FW_DATA_ADDR 0x08000a40
5077 #define TG3_FW_DATA_LEN 0x20
5078 #define TG3_FW_SBSS_ADDR 0x08000a60
5079 #define TG3_FW_SBSS_LEN 0xc
5080 #define TG3_FW_BSS_ADDR 0x08000a70
5081 #define TG3_FW_BSS_LEN 0x10
5082
5083 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5084 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5085 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5086 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5087 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5088 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5089 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5090 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5091 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5092 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5093 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5094 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5095 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5096 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5097 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5098 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5099 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5100 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5101 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5102 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5103 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5104 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5105 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5106 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5107 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5108 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5109 0, 0, 0, 0, 0, 0,
5110 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5111 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5112 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5113 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5114 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5115 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5116 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5117 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5118 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5119 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5120 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5121 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5122 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5123 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5124 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5125 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5126 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5127 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5128 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5129 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5130 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5131 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5132 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5133 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5134 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5135 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5136 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5137 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5138 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5139 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5140 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5141 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5142 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5143 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5144 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5145 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5146 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5147 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5148 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5149 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5150 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5151 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5152 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5153 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5154 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5155 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5156 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5157 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5158 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5159 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5160 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5161 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5162 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5163 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5164 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5165 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5166 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5167 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5168 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5169 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5170 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5171 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5172 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5173 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5174 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5175 };
5176
5177 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5178 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5179 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5180 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5181 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5182 0x00000000
5183 };
5184
5185 #if 0 /* All zeros, don't eat up space with it. */
5186 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5187 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5188 0x00000000, 0x00000000, 0x00000000, 0x00000000
5189 };
5190 #endif
5191
5192 #define RX_CPU_SCRATCH_BASE 0x30000
5193 #define RX_CPU_SCRATCH_SIZE 0x04000
5194 #define TX_CPU_SCRATCH_BASE 0x34000
5195 #define TX_CPU_SCRATCH_SIZE 0x04000
5196
5197 /* tp->lock is held. */
5198 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5199 {
5200 int i;
5201
5202 BUG_ON(offset == TX_CPU_BASE &&
5203 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5204
5205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5206 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5207
5208 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5209 return 0;
5210 }
5211 if (offset == RX_CPU_BASE) {
5212 for (i = 0; i < 10000; i++) {
5213 tw32(offset + CPU_STATE, 0xffffffff);
5214 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5215 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5216 break;
5217 }
5218
5219 tw32(offset + CPU_STATE, 0xffffffff);
5220 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5221 udelay(10);
5222 } else {
5223 for (i = 0; i < 10000; i++) {
5224 tw32(offset + CPU_STATE, 0xffffffff);
5225 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5226 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5227 break;
5228 }
5229 }
5230
5231 if (i >= 10000) {
5232 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5233 "and %s CPU\n",
5234 tp->dev->name,
5235 (offset == RX_CPU_BASE ? "RX" : "TX"));
5236 return -ENODEV;
5237 }
5238
5239 /* Clear firmware's nvram arbitration. */
5240 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5241 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5242 return 0;
5243 }
5244
5245 struct fw_info {
5246 unsigned int text_base;
5247 unsigned int text_len;
5248 const u32 *text_data;
5249 unsigned int rodata_base;
5250 unsigned int rodata_len;
5251 const u32 *rodata_data;
5252 unsigned int data_base;
5253 unsigned int data_len;
5254 const u32 *data_data;
5255 };
5256
5257 /* tp->lock is held. */
5258 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5259 int cpu_scratch_size, struct fw_info *info)
5260 {
5261 int err, lock_err, i;
5262 void (*write_op)(struct tg3 *, u32, u32);
5263
5264 if (cpu_base == TX_CPU_BASE &&
5265 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5266 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5267 "TX cpu firmware on %s which is 5705.\n",
5268 tp->dev->name);
5269 return -EINVAL;
5270 }
5271
5272 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5273 write_op = tg3_write_mem;
5274 else
5275 write_op = tg3_write_indirect_reg32;
5276
5277 /* It is possible that bootcode is still loading at this point.
5278 * Get the nvram lock first before halting the cpu.
5279 */
5280 lock_err = tg3_nvram_lock(tp);
5281 err = tg3_halt_cpu(tp, cpu_base);
5282 if (!lock_err)
5283 tg3_nvram_unlock(tp);
5284 if (err)
5285 goto out;
5286
5287 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5288 write_op(tp, cpu_scratch_base + i, 0);
5289 tw32(cpu_base + CPU_STATE, 0xffffffff);
5290 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5291 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5292 write_op(tp, (cpu_scratch_base +
5293 (info->text_base & 0xffff) +
5294 (i * sizeof(u32))),
5295 (info->text_data ?
5296 info->text_data[i] : 0));
5297 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5298 write_op(tp, (cpu_scratch_base +
5299 (info->rodata_base & 0xffff) +
5300 (i * sizeof(u32))),
5301 (info->rodata_data ?
5302 info->rodata_data[i] : 0));
5303 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5304 write_op(tp, (cpu_scratch_base +
5305 (info->data_base & 0xffff) +
5306 (i * sizeof(u32))),
5307 (info->data_data ?
5308 info->data_data[i] : 0));
5309
5310 err = 0;
5311
5312 out:
5313 return err;
5314 }
5315
5316 /* tp->lock is held. */
5317 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5318 {
5319 struct fw_info info;
5320 int err, i;
5321
5322 info.text_base = TG3_FW_TEXT_ADDR;
5323 info.text_len = TG3_FW_TEXT_LEN;
5324 info.text_data = &tg3FwText[0];
5325 info.rodata_base = TG3_FW_RODATA_ADDR;
5326 info.rodata_len = TG3_FW_RODATA_LEN;
5327 info.rodata_data = &tg3FwRodata[0];
5328 info.data_base = TG3_FW_DATA_ADDR;
5329 info.data_len = TG3_FW_DATA_LEN;
5330 info.data_data = NULL;
5331
5332 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5333 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5334 &info);
5335 if (err)
5336 return err;
5337
5338 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5339 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5340 &info);
5341 if (err)
5342 return err;
5343
5344 /* Now startup only the RX cpu. */
5345 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5346 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5347
5348 for (i = 0; i < 5; i++) {
5349 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5350 break;
5351 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5352 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5353 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5354 udelay(1000);
5355 }
5356 if (i >= 5) {
5357 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5358 "to set RX CPU PC, is %08x should be %08x\n",
5359 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5360 TG3_FW_TEXT_ADDR);
5361 return -ENODEV;
5362 }
5363 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5364 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5365
5366 return 0;
5367 }
5368
5369
5370 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5371 #define TG3_TSO_FW_RELASE_MINOR 0x6
5372 #define TG3_TSO_FW_RELEASE_FIX 0x0
5373 #define TG3_TSO_FW_START_ADDR 0x08000000
5374 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5375 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5376 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5377 #define TG3_TSO_FW_RODATA_LEN 0x60
5378 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5379 #define TG3_TSO_FW_DATA_LEN 0x30
5380 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5381 #define TG3_TSO_FW_SBSS_LEN 0x2c
5382 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5383 #define TG3_TSO_FW_BSS_LEN 0x894
5384
5385 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5386 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5387 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5388 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5389 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5390 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5391 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5392 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5393 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5394 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5395 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5396 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5397 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5398 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5399 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5400 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5401 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5402 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5403 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5404 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5405 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5406 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5407 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5408 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5409 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5410 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5411 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5412 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5413 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5414 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5415 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5416 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5417 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5418 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5419 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5420 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5421 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5422 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5423 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5424 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5425 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5426 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5427 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5428 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5429 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5430 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5431 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5432 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5433 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5434 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5435 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5436 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5437 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5438 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5439 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5440 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5441 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5442 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5443 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5444 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5445 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5446 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5447 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5448 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5449 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5450 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5451 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5452 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5453 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5454 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5455 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5456 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5457 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5458 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5459 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5460 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5461 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5462 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5463 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5464 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5465 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5466 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5467 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5468 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5469 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5470 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5471 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5472 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5473 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5474 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5475 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5476 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5477 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5478 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5479 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5480 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5481 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5482 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5483 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5484 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5485 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5486 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5487 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5488 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5489 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5490 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5491 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5492 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5493 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5494 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5495 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5496 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5497 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5498 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5499 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5500 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5501 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5502 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5503 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5504 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5505 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5506 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5507 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5508 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5509 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5510 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5511 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5512 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5513 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5514 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5515 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5516 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5517 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5518 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5519 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5520 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5521 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5522 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5523 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5524 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5525 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5526 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5527 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5528 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5529 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5530 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5531 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5532 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5533 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5534 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5535 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5536 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5537 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5538 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5539 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5540 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5541 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5542 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5543 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5544 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5545 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5546 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5547 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5548 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5549 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5550 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5551 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5552 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5553 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5554 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5555 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5556 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5557 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5558 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5559 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5560 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5561 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5562 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5563 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5564 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5565 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5566 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5567 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5568 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5569 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5570 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5571 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5572 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5573 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5574 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5575 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5576 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5577 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5578 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5579 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5580 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5581 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5582 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5583 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5584 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5585 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5586 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5587 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5588 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5589 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5590 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5591 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5592 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5593 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5594 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5595 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5596 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5597 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5598 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5599 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5600 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5601 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5602 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5603 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5604 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5605 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5606 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5607 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5608 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5609 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5610 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5611 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5612 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5613 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5614 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5615 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5616 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5617 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5618 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5619 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5620 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5621 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5622 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5623 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5624 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5625 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5626 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5627 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5628 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5629 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5630 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5631 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5632 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5633 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5634 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5635 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5636 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5637 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5638 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5639 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5640 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5641 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5642 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5643 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5644 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5645 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5646 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5647 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5648 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5649 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5650 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5651 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5652 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5653 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5654 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5655 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5656 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5657 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5658 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5659 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5660 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5661 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5662 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5663 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5664 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5665 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5666 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5667 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5668 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5669 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5670 };
5671
5672 static const u32 tg3TsoFwRodata[] = {
5673 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5674 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5675 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5676 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5677 0x00000000,
5678 };
5679
5680 static const u32 tg3TsoFwData[] = {
5681 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5682 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5683 0x00000000,
5684 };
5685
5686 /* 5705 needs a special version of the TSO firmware. */
5687 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5688 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5689 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5690 #define TG3_TSO5_FW_START_ADDR 0x00010000
5691 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5692 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5693 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5694 #define TG3_TSO5_FW_RODATA_LEN 0x50
5695 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5696 #define TG3_TSO5_FW_DATA_LEN 0x20
5697 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5698 #define TG3_TSO5_FW_SBSS_LEN 0x28
5699 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5700 #define TG3_TSO5_FW_BSS_LEN 0x88
5701
5702 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5703 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5704 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5705 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5706 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5707 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5708 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5709 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5710 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5711 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5712 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5713 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5714 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5715 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5716 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5717 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5718 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5719 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5720 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5721 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5722 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5723 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5724 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5725 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5726 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5727 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5728 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5729 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5730 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5731 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5732 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5733 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5734 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5735 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5736 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5737 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5738 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5739 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5740 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5741 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5742 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5743 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5744 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5745 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5746 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5747 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5748 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5749 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5750 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5751 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5752 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5753 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5754 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5755 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5756 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5757 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5758 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5759 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5760 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5761 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5762 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5763 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5764 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5765 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5766 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5767 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5768 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5769 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5770 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5771 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5772 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5773 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5774 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5775 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5776 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5777 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5778 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5779 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5780 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5781 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5782 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5783 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5784 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5785 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5786 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5787 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5788 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5789 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5790 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5791 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5792 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5793 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5794 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5795 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5796 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5797 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5798 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5799 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5800 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5801 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5802 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5803 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5804 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5805 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5806 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5807 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5808 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5809 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5810 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5811 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5812 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5813 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5814 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5815 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5816 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5817 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5818 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5819 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5820 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5821 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5822 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5823 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5824 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5825 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5826 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5827 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5828 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5829 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5830 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5831 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5832 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5833 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5834 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5835 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5836 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5837 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5838 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5839 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5840 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5841 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5842 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5843 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5844 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5845 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5846 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5847 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5848 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5849 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5850 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5851 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5852 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5853 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5854 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5855 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5856 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5857 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5858 0x00000000, 0x00000000, 0x00000000,
5859 };
5860
5861 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5862 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5863 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5864 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5865 0x00000000, 0x00000000, 0x00000000,
5866 };
5867
5868 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5869 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5870 0x00000000, 0x00000000, 0x00000000,
5871 };
5872
5873 /* tp->lock is held. */
5874 static int tg3_load_tso_firmware(struct tg3 *tp)
5875 {
5876 struct fw_info info;
5877 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5878 int err, i;
5879
5880 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5881 return 0;
5882
5883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5884 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5885 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5886 info.text_data = &tg3Tso5FwText[0];
5887 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5888 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5889 info.rodata_data = &tg3Tso5FwRodata[0];
5890 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5891 info.data_len = TG3_TSO5_FW_DATA_LEN;
5892 info.data_data = &tg3Tso5FwData[0];
5893 cpu_base = RX_CPU_BASE;
5894 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5895 cpu_scratch_size = (info.text_len +
5896 info.rodata_len +
5897 info.data_len +
5898 TG3_TSO5_FW_SBSS_LEN +
5899 TG3_TSO5_FW_BSS_LEN);
5900 } else {
5901 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5902 info.text_len = TG3_TSO_FW_TEXT_LEN;
5903 info.text_data = &tg3TsoFwText[0];
5904 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5905 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5906 info.rodata_data = &tg3TsoFwRodata[0];
5907 info.data_base = TG3_TSO_FW_DATA_ADDR;
5908 info.data_len = TG3_TSO_FW_DATA_LEN;
5909 info.data_data = &tg3TsoFwData[0];
5910 cpu_base = TX_CPU_BASE;
5911 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5912 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5913 }
5914
5915 err = tg3_load_firmware_cpu(tp, cpu_base,
5916 cpu_scratch_base, cpu_scratch_size,
5917 &info);
5918 if (err)
5919 return err;
5920
5921 /* Now startup the cpu. */
5922 tw32(cpu_base + CPU_STATE, 0xffffffff);
5923 tw32_f(cpu_base + CPU_PC, info.text_base);
5924
5925 for (i = 0; i < 5; i++) {
5926 if (tr32(cpu_base + CPU_PC) == info.text_base)
5927 break;
5928 tw32(cpu_base + CPU_STATE, 0xffffffff);
5929 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5930 tw32_f(cpu_base + CPU_PC, info.text_base);
5931 udelay(1000);
5932 }
5933 if (i >= 5) {
5934 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5935 "to set CPU PC, is %08x should be %08x\n",
5936 tp->dev->name, tr32(cpu_base + CPU_PC),
5937 info.text_base);
5938 return -ENODEV;
5939 }
5940 tw32(cpu_base + CPU_STATE, 0xffffffff);
5941 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5942 return 0;
5943 }
5944
5945
5946 /* tp->lock is held. */
5947 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
5948 {
5949 u32 addr_high, addr_low;
5950 int i;
5951
5952 addr_high = ((tp->dev->dev_addr[0] << 8) |
5953 tp->dev->dev_addr[1]);
5954 addr_low = ((tp->dev->dev_addr[2] << 24) |
5955 (tp->dev->dev_addr[3] << 16) |
5956 (tp->dev->dev_addr[4] << 8) |
5957 (tp->dev->dev_addr[5] << 0));
5958 for (i = 0; i < 4; i++) {
5959 if (i == 1 && skip_mac_1)
5960 continue;
5961 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5962 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5963 }
5964
5965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5967 for (i = 0; i < 12; i++) {
5968 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5969 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5970 }
5971 }
5972
5973 addr_high = (tp->dev->dev_addr[0] +
5974 tp->dev->dev_addr[1] +
5975 tp->dev->dev_addr[2] +
5976 tp->dev->dev_addr[3] +
5977 tp->dev->dev_addr[4] +
5978 tp->dev->dev_addr[5]) &
5979 TX_BACKOFF_SEED_MASK;
5980 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5981 }
5982
5983 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5984 {
5985 struct tg3 *tp = netdev_priv(dev);
5986 struct sockaddr *addr = p;
5987 int err = 0, skip_mac_1 = 0;
5988
5989 if (!is_valid_ether_addr(addr->sa_data))
5990 return -EINVAL;
5991
5992 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5993
5994 if (!netif_running(dev))
5995 return 0;
5996
5997 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5998 u32 addr0_high, addr0_low, addr1_high, addr1_low;
5999
6000 addr0_high = tr32(MAC_ADDR_0_HIGH);
6001 addr0_low = tr32(MAC_ADDR_0_LOW);
6002 addr1_high = tr32(MAC_ADDR_1_HIGH);
6003 addr1_low = tr32(MAC_ADDR_1_LOW);
6004
6005 /* Skip MAC addr 1 if ASF is using it. */
6006 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6007 !(addr1_high == 0 && addr1_low == 0))
6008 skip_mac_1 = 1;
6009 }
6010 spin_lock_bh(&tp->lock);
6011 __tg3_set_mac_addr(tp, skip_mac_1);
6012 spin_unlock_bh(&tp->lock);
6013
6014 return err;
6015 }
6016
6017 /* tp->lock is held. */
6018 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6019 dma_addr_t mapping, u32 maxlen_flags,
6020 u32 nic_addr)
6021 {
6022 tg3_write_mem(tp,
6023 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6024 ((u64) mapping >> 32));
6025 tg3_write_mem(tp,
6026 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6027 ((u64) mapping & 0xffffffff));
6028 tg3_write_mem(tp,
6029 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6030 maxlen_flags);
6031
6032 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6033 tg3_write_mem(tp,
6034 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6035 nic_addr);
6036 }
6037
6038 static void __tg3_set_rx_mode(struct net_device *);
6039 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6040 {
6041 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6042 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6043 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6044 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6045 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6046 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6047 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6048 }
6049 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6050 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6051 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6052 u32 val = ec->stats_block_coalesce_usecs;
6053
6054 if (!netif_carrier_ok(tp->dev))
6055 val = 0;
6056
6057 tw32(HOSTCC_STAT_COAL_TICKS, val);
6058 }
6059 }
6060
6061 /* tp->lock is held. */
6062 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6063 {
6064 u32 val, rdmac_mode;
6065 int i, err, limit;
6066
6067 tg3_disable_ints(tp);
6068
6069 tg3_stop_fw(tp);
6070
6071 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6072
6073 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6074 tg3_abort_hw(tp, 1);
6075 }
6076
6077 if (reset_phy)
6078 tg3_phy_reset(tp);
6079
6080 err = tg3_chip_reset(tp);
6081 if (err)
6082 return err;
6083
6084 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6085
6086 /* This works around an issue with Athlon chipsets on
6087 * B3 tigon3 silicon. This bit has no effect on any
6088 * other revision. But do not set this on PCI Express
6089 * chips.
6090 */
6091 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6092 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6093 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6094
6095 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6096 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6097 val = tr32(TG3PCI_PCISTATE);
6098 val |= PCISTATE_RETRY_SAME_DMA;
6099 tw32(TG3PCI_PCISTATE, val);
6100 }
6101
6102 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6103 /* Enable some hw fixes. */
6104 val = tr32(TG3PCI_MSI_DATA);
6105 val |= (1 << 26) | (1 << 28) | (1 << 29);
6106 tw32(TG3PCI_MSI_DATA, val);
6107 }
6108
6109 /* Descriptor ring init may make accesses to the
6110 * NIC SRAM area to setup the TX descriptors, so we
6111 * can only do this after the hardware has been
6112 * successfully reset.
6113 */
6114 err = tg3_init_rings(tp);
6115 if (err)
6116 return err;
6117
6118 /* This value is determined during the probe time DMA
6119 * engine test, tg3_test_dma.
6120 */
6121 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6122
6123 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6124 GRC_MODE_4X_NIC_SEND_RINGS |
6125 GRC_MODE_NO_TX_PHDR_CSUM |
6126 GRC_MODE_NO_RX_PHDR_CSUM);
6127 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6128
6129 /* Pseudo-header checksum is done by hardware logic and not
6130 * the offload processers, so make the chip do the pseudo-
6131 * header checksums on receive. For transmit it is more
6132 * convenient to do the pseudo-header checksum in software
6133 * as Linux does that on transmit for us in all cases.
6134 */
6135 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6136
6137 tw32(GRC_MODE,
6138 tp->grc_mode |
6139 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6140
6141 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6142 val = tr32(GRC_MISC_CFG);
6143 val &= ~0xff;
6144 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6145 tw32(GRC_MISC_CFG, val);
6146
6147 /* Initialize MBUF/DESC pool. */
6148 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6149 /* Do nothing. */
6150 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6151 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6153 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6154 else
6155 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6156 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6157 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6158 }
6159 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6160 int fw_len;
6161
6162 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6163 TG3_TSO5_FW_RODATA_LEN +
6164 TG3_TSO5_FW_DATA_LEN +
6165 TG3_TSO5_FW_SBSS_LEN +
6166 TG3_TSO5_FW_BSS_LEN);
6167 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6168 tw32(BUFMGR_MB_POOL_ADDR,
6169 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6170 tw32(BUFMGR_MB_POOL_SIZE,
6171 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6172 }
6173
6174 if (tp->dev->mtu <= ETH_DATA_LEN) {
6175 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6176 tp->bufmgr_config.mbuf_read_dma_low_water);
6177 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6178 tp->bufmgr_config.mbuf_mac_rx_low_water);
6179 tw32(BUFMGR_MB_HIGH_WATER,
6180 tp->bufmgr_config.mbuf_high_water);
6181 } else {
6182 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6183 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6184 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6185 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6186 tw32(BUFMGR_MB_HIGH_WATER,
6187 tp->bufmgr_config.mbuf_high_water_jumbo);
6188 }
6189 tw32(BUFMGR_DMA_LOW_WATER,
6190 tp->bufmgr_config.dma_low_water);
6191 tw32(BUFMGR_DMA_HIGH_WATER,
6192 tp->bufmgr_config.dma_high_water);
6193
6194 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6195 for (i = 0; i < 2000; i++) {
6196 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6197 break;
6198 udelay(10);
6199 }
6200 if (i >= 2000) {
6201 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6202 tp->dev->name);
6203 return -ENODEV;
6204 }
6205
6206 /* Setup replenish threshold. */
6207 val = tp->rx_pending / 8;
6208 if (val == 0)
6209 val = 1;
6210 else if (val > tp->rx_std_max_post)
6211 val = tp->rx_std_max_post;
6212 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6213 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6214 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6215
6216 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6217 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6218 }
6219
6220 tw32(RCVBDI_STD_THRESH, val);
6221
6222 /* Initialize TG3_BDINFO's at:
6223 * RCVDBDI_STD_BD: standard eth size rx ring
6224 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6225 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6226 *
6227 * like so:
6228 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6229 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6230 * ring attribute flags
6231 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6232 *
6233 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6234 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6235 *
6236 * The size of each ring is fixed in the firmware, but the location is
6237 * configurable.
6238 */
6239 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6240 ((u64) tp->rx_std_mapping >> 32));
6241 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6242 ((u64) tp->rx_std_mapping & 0xffffffff));
6243 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6244 NIC_SRAM_RX_BUFFER_DESC);
6245
6246 /* Don't even try to program the JUMBO/MINI buffer descriptor
6247 * configs on 5705.
6248 */
6249 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6250 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6251 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6252 } else {
6253 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6254 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6255
6256 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6257 BDINFO_FLAGS_DISABLED);
6258
6259 /* Setup replenish threshold. */
6260 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6261
6262 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6263 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6264 ((u64) tp->rx_jumbo_mapping >> 32));
6265 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6266 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6267 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6268 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6269 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6270 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6271 } else {
6272 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6273 BDINFO_FLAGS_DISABLED);
6274 }
6275
6276 }
6277
6278 /* There is only one send ring on 5705/5750, no need to explicitly
6279 * disable the others.
6280 */
6281 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6282 /* Clear out send RCB ring in SRAM. */
6283 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6284 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6285 BDINFO_FLAGS_DISABLED);
6286 }
6287
6288 tp->tx_prod = 0;
6289 tp->tx_cons = 0;
6290 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6291 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6292
6293 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6294 tp->tx_desc_mapping,
6295 (TG3_TX_RING_SIZE <<
6296 BDINFO_FLAGS_MAXLEN_SHIFT),
6297 NIC_SRAM_TX_BUFFER_DESC);
6298
6299 /* There is only one receive return ring on 5705/5750, no need
6300 * to explicitly disable the others.
6301 */
6302 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6303 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6304 i += TG3_BDINFO_SIZE) {
6305 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6306 BDINFO_FLAGS_DISABLED);
6307 }
6308 }
6309
6310 tp->rx_rcb_ptr = 0;
6311 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6312
6313 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6314 tp->rx_rcb_mapping,
6315 (TG3_RX_RCB_RING_SIZE(tp) <<
6316 BDINFO_FLAGS_MAXLEN_SHIFT),
6317 0);
6318
6319 tp->rx_std_ptr = tp->rx_pending;
6320 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6321 tp->rx_std_ptr);
6322
6323 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6324 tp->rx_jumbo_pending : 0;
6325 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6326 tp->rx_jumbo_ptr);
6327
6328 /* Initialize MAC address and backoff seed. */
6329 __tg3_set_mac_addr(tp, 0);
6330
6331 /* MTU + ethernet header + FCS + optional VLAN tag */
6332 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6333
6334 /* The slot time is changed by tg3_setup_phy if we
6335 * run at gigabit with half duplex.
6336 */
6337 tw32(MAC_TX_LENGTHS,
6338 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6339 (6 << TX_LENGTHS_IPG_SHIFT) |
6340 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6341
6342 /* Receive rules. */
6343 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6344 tw32(RCVLPC_CONFIG, 0x0181);
6345
6346 /* Calculate RDMAC_MODE setting early, we need it to determine
6347 * the RCVLPC_STATE_ENABLE mask.
6348 */
6349 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6350 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6351 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6352 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6353 RDMAC_MODE_LNGREAD_ENAB);
6354
6355 /* If statement applies to 5705 and 5750 PCI devices only */
6356 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6357 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6358 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6359 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6360 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6361 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6362 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6363 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6364 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6365 }
6366 }
6367
6368 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6369 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6370
6371 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6372 rdmac_mode |= (1 << 27);
6373
6374 /* Receive/send statistics. */
6375 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6376 val = tr32(RCVLPC_STATS_ENABLE);
6377 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6378 tw32(RCVLPC_STATS_ENABLE, val);
6379 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6380 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6381 val = tr32(RCVLPC_STATS_ENABLE);
6382 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6383 tw32(RCVLPC_STATS_ENABLE, val);
6384 } else {
6385 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6386 }
6387 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6388 tw32(SNDDATAI_STATSENAB, 0xffffff);
6389 tw32(SNDDATAI_STATSCTRL,
6390 (SNDDATAI_SCTRL_ENABLE |
6391 SNDDATAI_SCTRL_FASTUPD));
6392
6393 /* Setup host coalescing engine. */
6394 tw32(HOSTCC_MODE, 0);
6395 for (i = 0; i < 2000; i++) {
6396 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6397 break;
6398 udelay(10);
6399 }
6400
6401 __tg3_set_coalesce(tp, &tp->coal);
6402
6403 /* set status block DMA address */
6404 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6405 ((u64) tp->status_mapping >> 32));
6406 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6407 ((u64) tp->status_mapping & 0xffffffff));
6408
6409 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6410 /* Status/statistics block address. See tg3_timer,
6411 * the tg3_periodic_fetch_stats call there, and
6412 * tg3_get_stats to see how this works for 5705/5750 chips.
6413 */
6414 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6415 ((u64) tp->stats_mapping >> 32));
6416 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6417 ((u64) tp->stats_mapping & 0xffffffff));
6418 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6419 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6420 }
6421
6422 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6423
6424 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6425 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6426 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6427 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6428
6429 /* Clear statistics/status block in chip, and status block in ram. */
6430 for (i = NIC_SRAM_STATS_BLK;
6431 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6432 i += sizeof(u32)) {
6433 tg3_write_mem(tp, i, 0);
6434 udelay(40);
6435 }
6436 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6437
6438 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6439 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6440 /* reset to prevent losing 1st rx packet intermittently */
6441 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6442 udelay(10);
6443 }
6444
6445 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6446 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6447 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6448 udelay(40);
6449
6450 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6451 * If TG3_FLG2_IS_NIC is zero, we should read the
6452 * register to preserve the GPIO settings for LOMs. The GPIOs,
6453 * whether used as inputs or outputs, are set by boot code after
6454 * reset.
6455 */
6456 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6457 u32 gpio_mask;
6458
6459 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6460 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6461 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6462
6463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6464 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6465 GRC_LCLCTRL_GPIO_OUTPUT3;
6466
6467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6468 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6469
6470 tp->grc_local_ctrl &= ~gpio_mask;
6471 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6472
6473 /* GPIO1 must be driven high for eeprom write protect */
6474 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6475 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6476 GRC_LCLCTRL_GPIO_OUTPUT1);
6477 }
6478 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6479 udelay(100);
6480
6481 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6482 tp->last_tag = 0;
6483
6484 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6485 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6486 udelay(40);
6487 }
6488
6489 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6490 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6491 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6492 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6493 WDMAC_MODE_LNGREAD_ENAB);
6494
6495 /* If statement applies to 5705 and 5750 PCI devices only */
6496 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6497 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6499 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6500 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6501 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6502 /* nothing */
6503 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6504 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6505 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6506 val |= WDMAC_MODE_RX_ACCEL;
6507 }
6508 }
6509
6510 /* Enable host coalescing bug fix */
6511 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6512 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6513 val |= (1 << 29);
6514
6515 tw32_f(WDMAC_MODE, val);
6516 udelay(40);
6517
6518 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6519 val = tr32(TG3PCI_X_CAPS);
6520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6521 val &= ~PCIX_CAPS_BURST_MASK;
6522 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6523 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6524 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6525 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6526 }
6527 tw32(TG3PCI_X_CAPS, val);
6528 }
6529
6530 tw32_f(RDMAC_MODE, rdmac_mode);
6531 udelay(40);
6532
6533 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6534 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6535 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6536 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6537 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6538 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6539 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6540 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6541 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6542 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6543 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6544 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6545
6546 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6547 err = tg3_load_5701_a0_firmware_fix(tp);
6548 if (err)
6549 return err;
6550 }
6551
6552 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6553 err = tg3_load_tso_firmware(tp);
6554 if (err)
6555 return err;
6556 }
6557
6558 tp->tx_mode = TX_MODE_ENABLE;
6559 tw32_f(MAC_TX_MODE, tp->tx_mode);
6560 udelay(100);
6561
6562 tp->rx_mode = RX_MODE_ENABLE;
6563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6564 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6565
6566 tw32_f(MAC_RX_MODE, tp->rx_mode);
6567 udelay(10);
6568
6569 if (tp->link_config.phy_is_low_power) {
6570 tp->link_config.phy_is_low_power = 0;
6571 tp->link_config.speed = tp->link_config.orig_speed;
6572 tp->link_config.duplex = tp->link_config.orig_duplex;
6573 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6574 }
6575
6576 tp->mi_mode = MAC_MI_MODE_BASE;
6577 tw32_f(MAC_MI_MODE, tp->mi_mode);
6578 udelay(80);
6579
6580 tw32(MAC_LED_CTRL, tp->led_ctrl);
6581
6582 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6583 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6584 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6585 udelay(10);
6586 }
6587 tw32_f(MAC_RX_MODE, tp->rx_mode);
6588 udelay(10);
6589
6590 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6591 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6592 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6593 /* Set drive transmission level to 1.2V */
6594 /* only if the signal pre-emphasis bit is not set */
6595 val = tr32(MAC_SERDES_CFG);
6596 val &= 0xfffff000;
6597 val |= 0x880;
6598 tw32(MAC_SERDES_CFG, val);
6599 }
6600 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6601 tw32(MAC_SERDES_CFG, 0x616000);
6602 }
6603
6604 /* Prevent chip from dropping frames when flow control
6605 * is enabled.
6606 */
6607 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6608
6609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6610 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6611 /* Use hardware link auto-negotiation */
6612 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6613 }
6614
6615 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6616 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6617 u32 tmp;
6618
6619 tmp = tr32(SERDES_RX_CTRL);
6620 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6621 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6622 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6623 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6624 }
6625
6626 err = tg3_setup_phy(tp, 0);
6627 if (err)
6628 return err;
6629
6630 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6631 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6632 u32 tmp;
6633
6634 /* Clear CRC stats. */
6635 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6636 tg3_writephy(tp, MII_TG3_TEST1,
6637 tmp | MII_TG3_TEST1_CRC_EN);
6638 tg3_readphy(tp, 0x14, &tmp);
6639 }
6640 }
6641
6642 __tg3_set_rx_mode(tp->dev);
6643
6644 /* Initialize receive rules. */
6645 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6646 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6647 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6648 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6649
6650 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6651 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6652 limit = 8;
6653 else
6654 limit = 16;
6655 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6656 limit -= 4;
6657 switch (limit) {
6658 case 16:
6659 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6660 case 15:
6661 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6662 case 14:
6663 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6664 case 13:
6665 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6666 case 12:
6667 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6668 case 11:
6669 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6670 case 10:
6671 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6672 case 9:
6673 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6674 case 8:
6675 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6676 case 7:
6677 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6678 case 6:
6679 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6680 case 5:
6681 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6682 case 4:
6683 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6684 case 3:
6685 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6686 case 2:
6687 case 1:
6688
6689 default:
6690 break;
6691 };
6692
6693 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6694
6695 return 0;
6696 }
6697
6698 /* Called at device open time to get the chip ready for
6699 * packet processing. Invoked with tp->lock held.
6700 */
6701 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6702 {
6703 int err;
6704
6705 /* Force the chip into D0. */
6706 err = tg3_set_power_state(tp, PCI_D0);
6707 if (err)
6708 goto out;
6709
6710 tg3_switch_clocks(tp);
6711
6712 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6713
6714 err = tg3_reset_hw(tp, reset_phy);
6715
6716 out:
6717 return err;
6718 }
6719
6720 #define TG3_STAT_ADD32(PSTAT, REG) \
6721 do { u32 __val = tr32(REG); \
6722 (PSTAT)->low += __val; \
6723 if ((PSTAT)->low < __val) \
6724 (PSTAT)->high += 1; \
6725 } while (0)
6726
6727 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6728 {
6729 struct tg3_hw_stats *sp = tp->hw_stats;
6730
6731 if (!netif_carrier_ok(tp->dev))
6732 return;
6733
6734 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6735 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6736 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6737 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6738 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6739 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6740 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6741 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6742 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6743 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6744 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6745 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6746 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6747
6748 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6749 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6750 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6751 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6752 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6753 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6754 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6755 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6756 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6757 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6758 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6759 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6760 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6761 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6762
6763 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6764 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6765 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6766 }
6767
6768 static void tg3_timer(unsigned long __opaque)
6769 {
6770 struct tg3 *tp = (struct tg3 *) __opaque;
6771
6772 if (tp->irq_sync)
6773 goto restart_timer;
6774
6775 spin_lock(&tp->lock);
6776
6777 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6778 /* All of this garbage is because when using non-tagged
6779 * IRQ status the mailbox/status_block protocol the chip
6780 * uses with the cpu is race prone.
6781 */
6782 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6783 tw32(GRC_LOCAL_CTRL,
6784 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6785 } else {
6786 tw32(HOSTCC_MODE, tp->coalesce_mode |
6787 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6788 }
6789
6790 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6791 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6792 spin_unlock(&tp->lock);
6793 schedule_work(&tp->reset_task);
6794 return;
6795 }
6796 }
6797
6798 /* This part only runs once per second. */
6799 if (!--tp->timer_counter) {
6800 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6801 tg3_periodic_fetch_stats(tp);
6802
6803 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6804 u32 mac_stat;
6805 int phy_event;
6806
6807 mac_stat = tr32(MAC_STATUS);
6808
6809 phy_event = 0;
6810 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6811 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6812 phy_event = 1;
6813 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6814 phy_event = 1;
6815
6816 if (phy_event)
6817 tg3_setup_phy(tp, 0);
6818 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6819 u32 mac_stat = tr32(MAC_STATUS);
6820 int need_setup = 0;
6821
6822 if (netif_carrier_ok(tp->dev) &&
6823 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6824 need_setup = 1;
6825 }
6826 if (! netif_carrier_ok(tp->dev) &&
6827 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6828 MAC_STATUS_SIGNAL_DET))) {
6829 need_setup = 1;
6830 }
6831 if (need_setup) {
6832 if (!tp->serdes_counter) {
6833 tw32_f(MAC_MODE,
6834 (tp->mac_mode &
6835 ~MAC_MODE_PORT_MODE_MASK));
6836 udelay(40);
6837 tw32_f(MAC_MODE, tp->mac_mode);
6838 udelay(40);
6839 }
6840 tg3_setup_phy(tp, 0);
6841 }
6842 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6843 tg3_serdes_parallel_detect(tp);
6844
6845 tp->timer_counter = tp->timer_multiplier;
6846 }
6847
6848 /* Heartbeat is only sent once every 2 seconds.
6849 *
6850 * The heartbeat is to tell the ASF firmware that the host
6851 * driver is still alive. In the event that the OS crashes,
6852 * ASF needs to reset the hardware to free up the FIFO space
6853 * that may be filled with rx packets destined for the host.
6854 * If the FIFO is full, ASF will no longer function properly.
6855 *
6856 * Unintended resets have been reported on real time kernels
6857 * where the timer doesn't run on time. Netpoll will also have
6858 * same problem.
6859 *
6860 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6861 * to check the ring condition when the heartbeat is expiring
6862 * before doing the reset. This will prevent most unintended
6863 * resets.
6864 */
6865 if (!--tp->asf_counter) {
6866 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6867 u32 val;
6868
6869 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6870 FWCMD_NICDRV_ALIVE3);
6871 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6872 /* 5 seconds timeout */
6873 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6874 val = tr32(GRC_RX_CPU_EVENT);
6875 val |= (1 << 14);
6876 tw32(GRC_RX_CPU_EVENT, val);
6877 }
6878 tp->asf_counter = tp->asf_multiplier;
6879 }
6880
6881 spin_unlock(&tp->lock);
6882
6883 restart_timer:
6884 tp->timer.expires = jiffies + tp->timer_offset;
6885 add_timer(&tp->timer);
6886 }
6887
6888 static int tg3_request_irq(struct tg3 *tp)
6889 {
6890 irq_handler_t fn;
6891 unsigned long flags;
6892 struct net_device *dev = tp->dev;
6893
6894 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6895 fn = tg3_msi;
6896 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6897 fn = tg3_msi_1shot;
6898 flags = IRQF_SAMPLE_RANDOM;
6899 } else {
6900 fn = tg3_interrupt;
6901 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6902 fn = tg3_interrupt_tagged;
6903 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6904 }
6905 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6906 }
6907
6908 static int tg3_test_interrupt(struct tg3 *tp)
6909 {
6910 struct net_device *dev = tp->dev;
6911 int err, i, intr_ok = 0;
6912
6913 if (!netif_running(dev))
6914 return -ENODEV;
6915
6916 tg3_disable_ints(tp);
6917
6918 free_irq(tp->pdev->irq, dev);
6919
6920 err = request_irq(tp->pdev->irq, tg3_test_isr,
6921 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6922 if (err)
6923 return err;
6924
6925 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6926 tg3_enable_ints(tp);
6927
6928 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6929 HOSTCC_MODE_NOW);
6930
6931 for (i = 0; i < 5; i++) {
6932 u32 int_mbox, misc_host_ctrl;
6933
6934 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6935 TG3_64BIT_REG_LOW);
6936 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6937
6938 if ((int_mbox != 0) ||
6939 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6940 intr_ok = 1;
6941 break;
6942 }
6943
6944 msleep(10);
6945 }
6946
6947 tg3_disable_ints(tp);
6948
6949 free_irq(tp->pdev->irq, dev);
6950
6951 err = tg3_request_irq(tp);
6952
6953 if (err)
6954 return err;
6955
6956 if (intr_ok)
6957 return 0;
6958
6959 return -EIO;
6960 }
6961
6962 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6963 * successfully restored
6964 */
6965 static int tg3_test_msi(struct tg3 *tp)
6966 {
6967 struct net_device *dev = tp->dev;
6968 int err;
6969 u16 pci_cmd;
6970
6971 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6972 return 0;
6973
6974 /* Turn off SERR reporting in case MSI terminates with Master
6975 * Abort.
6976 */
6977 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6978 pci_write_config_word(tp->pdev, PCI_COMMAND,
6979 pci_cmd & ~PCI_COMMAND_SERR);
6980
6981 err = tg3_test_interrupt(tp);
6982
6983 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6984
6985 if (!err)
6986 return 0;
6987
6988 /* other failures */
6989 if (err != -EIO)
6990 return err;
6991
6992 /* MSI test failed, go back to INTx mode */
6993 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6994 "switching to INTx mode. Please report this failure to "
6995 "the PCI maintainer and include system chipset information.\n",
6996 tp->dev->name);
6997
6998 free_irq(tp->pdev->irq, dev);
6999 pci_disable_msi(tp->pdev);
7000
7001 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7002
7003 err = tg3_request_irq(tp);
7004 if (err)
7005 return err;
7006
7007 /* Need to reset the chip because the MSI cycle may have terminated
7008 * with Master Abort.
7009 */
7010 tg3_full_lock(tp, 1);
7011
7012 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7013 err = tg3_init_hw(tp, 1);
7014
7015 tg3_full_unlock(tp);
7016
7017 if (err)
7018 free_irq(tp->pdev->irq, dev);
7019
7020 return err;
7021 }
7022
7023 static int tg3_open(struct net_device *dev)
7024 {
7025 struct tg3 *tp = netdev_priv(dev);
7026 int err;
7027
7028 netif_carrier_off(tp->dev);
7029
7030 tg3_full_lock(tp, 0);
7031
7032 err = tg3_set_power_state(tp, PCI_D0);
7033 if (err) {
7034 tg3_full_unlock(tp);
7035 return err;
7036 }
7037
7038 tg3_disable_ints(tp);
7039 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7040
7041 tg3_full_unlock(tp);
7042
7043 /* The placement of this call is tied
7044 * to the setup and use of Host TX descriptors.
7045 */
7046 err = tg3_alloc_consistent(tp);
7047 if (err)
7048 return err;
7049
7050 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7051 /* All MSI supporting chips should support tagged
7052 * status. Assert that this is the case.
7053 */
7054 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7055 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7056 "Not using MSI.\n", tp->dev->name);
7057 } else if (pci_enable_msi(tp->pdev) == 0) {
7058 u32 msi_mode;
7059
7060 msi_mode = tr32(MSGINT_MODE);
7061 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7062 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7063 }
7064 }
7065 err = tg3_request_irq(tp);
7066
7067 if (err) {
7068 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7069 pci_disable_msi(tp->pdev);
7070 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7071 }
7072 tg3_free_consistent(tp);
7073 return err;
7074 }
7075
7076 tg3_full_lock(tp, 0);
7077
7078 err = tg3_init_hw(tp, 1);
7079 if (err) {
7080 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7081 tg3_free_rings(tp);
7082 } else {
7083 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7084 tp->timer_offset = HZ;
7085 else
7086 tp->timer_offset = HZ / 10;
7087
7088 BUG_ON(tp->timer_offset > HZ);
7089 tp->timer_counter = tp->timer_multiplier =
7090 (HZ / tp->timer_offset);
7091 tp->asf_counter = tp->asf_multiplier =
7092 ((HZ / tp->timer_offset) * 2);
7093
7094 init_timer(&tp->timer);
7095 tp->timer.expires = jiffies + tp->timer_offset;
7096 tp->timer.data = (unsigned long) tp;
7097 tp->timer.function = tg3_timer;
7098 }
7099
7100 tg3_full_unlock(tp);
7101
7102 if (err) {
7103 free_irq(tp->pdev->irq, dev);
7104 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7105 pci_disable_msi(tp->pdev);
7106 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7107 }
7108 tg3_free_consistent(tp);
7109 return err;
7110 }
7111
7112 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7113 err = tg3_test_msi(tp);
7114
7115 if (err) {
7116 tg3_full_lock(tp, 0);
7117
7118 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7119 pci_disable_msi(tp->pdev);
7120 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7121 }
7122 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7123 tg3_free_rings(tp);
7124 tg3_free_consistent(tp);
7125
7126 tg3_full_unlock(tp);
7127
7128 return err;
7129 }
7130
7131 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7132 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7133 u32 val = tr32(PCIE_TRANSACTION_CFG);
7134
7135 tw32(PCIE_TRANSACTION_CFG,
7136 val | PCIE_TRANS_CFG_1SHOT_MSI);
7137 }
7138 }
7139 }
7140
7141 tg3_full_lock(tp, 0);
7142
7143 add_timer(&tp->timer);
7144 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7145 tg3_enable_ints(tp);
7146
7147 tg3_full_unlock(tp);
7148
7149 netif_start_queue(dev);
7150
7151 return 0;
7152 }
7153
7154 #if 0
7155 /*static*/ void tg3_dump_state(struct tg3 *tp)
7156 {
7157 u32 val32, val32_2, val32_3, val32_4, val32_5;
7158 u16 val16;
7159 int i;
7160
7161 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7162 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7163 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7164 val16, val32);
7165
7166 /* MAC block */
7167 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7168 tr32(MAC_MODE), tr32(MAC_STATUS));
7169 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7170 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7171 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7172 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7173 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7174 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7175
7176 /* Send data initiator control block */
7177 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7178 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7179 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7180 tr32(SNDDATAI_STATSCTRL));
7181
7182 /* Send data completion control block */
7183 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7184
7185 /* Send BD ring selector block */
7186 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7187 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7188
7189 /* Send BD initiator control block */
7190 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7191 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7192
7193 /* Send BD completion control block */
7194 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7195
7196 /* Receive list placement control block */
7197 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7198 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7199 printk(" RCVLPC_STATSCTRL[%08x]\n",
7200 tr32(RCVLPC_STATSCTRL));
7201
7202 /* Receive data and receive BD initiator control block */
7203 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7204 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7205
7206 /* Receive data completion control block */
7207 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7208 tr32(RCVDCC_MODE));
7209
7210 /* Receive BD initiator control block */
7211 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7212 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7213
7214 /* Receive BD completion control block */
7215 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7216 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7217
7218 /* Receive list selector control block */
7219 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7220 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7221
7222 /* Mbuf cluster free block */
7223 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7224 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7225
7226 /* Host coalescing control block */
7227 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7228 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7229 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7230 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7231 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7232 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7233 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7234 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7235 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7236 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7237 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7238 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7239
7240 /* Memory arbiter control block */
7241 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7242 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7243
7244 /* Buffer manager control block */
7245 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7246 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7247 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7248 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7249 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7250 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7251 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7252 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7253
7254 /* Read DMA control block */
7255 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7256 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7257
7258 /* Write DMA control block */
7259 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7260 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7261
7262 /* DMA completion block */
7263 printk("DEBUG: DMAC_MODE[%08x]\n",
7264 tr32(DMAC_MODE));
7265
7266 /* GRC block */
7267 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7268 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7269 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7270 tr32(GRC_LOCAL_CTRL));
7271
7272 /* TG3_BDINFOs */
7273 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7274 tr32(RCVDBDI_JUMBO_BD + 0x0),
7275 tr32(RCVDBDI_JUMBO_BD + 0x4),
7276 tr32(RCVDBDI_JUMBO_BD + 0x8),
7277 tr32(RCVDBDI_JUMBO_BD + 0xc));
7278 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7279 tr32(RCVDBDI_STD_BD + 0x0),
7280 tr32(RCVDBDI_STD_BD + 0x4),
7281 tr32(RCVDBDI_STD_BD + 0x8),
7282 tr32(RCVDBDI_STD_BD + 0xc));
7283 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7284 tr32(RCVDBDI_MINI_BD + 0x0),
7285 tr32(RCVDBDI_MINI_BD + 0x4),
7286 tr32(RCVDBDI_MINI_BD + 0x8),
7287 tr32(RCVDBDI_MINI_BD + 0xc));
7288
7289 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7290 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7291 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7292 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7293 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7294 val32, val32_2, val32_3, val32_4);
7295
7296 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7297 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7298 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7299 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7300 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7301 val32, val32_2, val32_3, val32_4);
7302
7303 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7304 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7305 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7306 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7307 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7308 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7309 val32, val32_2, val32_3, val32_4, val32_5);
7310
7311 /* SW status block */
7312 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7313 tp->hw_status->status,
7314 tp->hw_status->status_tag,
7315 tp->hw_status->rx_jumbo_consumer,
7316 tp->hw_status->rx_consumer,
7317 tp->hw_status->rx_mini_consumer,
7318 tp->hw_status->idx[0].rx_producer,
7319 tp->hw_status->idx[0].tx_consumer);
7320
7321 /* SW statistics block */
7322 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7323 ((u32 *)tp->hw_stats)[0],
7324 ((u32 *)tp->hw_stats)[1],
7325 ((u32 *)tp->hw_stats)[2],
7326 ((u32 *)tp->hw_stats)[3]);
7327
7328 /* Mailboxes */
7329 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7330 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7331 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7332 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7333 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7334
7335 /* NIC side send descriptors. */
7336 for (i = 0; i < 6; i++) {
7337 unsigned long txd;
7338
7339 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7340 + (i * sizeof(struct tg3_tx_buffer_desc));
7341 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7342 i,
7343 readl(txd + 0x0), readl(txd + 0x4),
7344 readl(txd + 0x8), readl(txd + 0xc));
7345 }
7346
7347 /* NIC side RX descriptors. */
7348 for (i = 0; i < 6; i++) {
7349 unsigned long rxd;
7350
7351 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7352 + (i * sizeof(struct tg3_rx_buffer_desc));
7353 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7354 i,
7355 readl(rxd + 0x0), readl(rxd + 0x4),
7356 readl(rxd + 0x8), readl(rxd + 0xc));
7357 rxd += (4 * sizeof(u32));
7358 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7359 i,
7360 readl(rxd + 0x0), readl(rxd + 0x4),
7361 readl(rxd + 0x8), readl(rxd + 0xc));
7362 }
7363
7364 for (i = 0; i < 6; i++) {
7365 unsigned long rxd;
7366
7367 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7368 + (i * sizeof(struct tg3_rx_buffer_desc));
7369 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7370 i,
7371 readl(rxd + 0x0), readl(rxd + 0x4),
7372 readl(rxd + 0x8), readl(rxd + 0xc));
7373 rxd += (4 * sizeof(u32));
7374 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7375 i,
7376 readl(rxd + 0x0), readl(rxd + 0x4),
7377 readl(rxd + 0x8), readl(rxd + 0xc));
7378 }
7379 }
7380 #endif
7381
7382 static struct net_device_stats *tg3_get_stats(struct net_device *);
7383 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7384
7385 static int tg3_close(struct net_device *dev)
7386 {
7387 struct tg3 *tp = netdev_priv(dev);
7388
7389 cancel_work_sync(&tp->reset_task);
7390
7391 netif_stop_queue(dev);
7392
7393 del_timer_sync(&tp->timer);
7394
7395 tg3_full_lock(tp, 1);
7396 #if 0
7397 tg3_dump_state(tp);
7398 #endif
7399
7400 tg3_disable_ints(tp);
7401
7402 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7403 tg3_free_rings(tp);
7404 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7405
7406 tg3_full_unlock(tp);
7407
7408 free_irq(tp->pdev->irq, dev);
7409 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7410 pci_disable_msi(tp->pdev);
7411 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7412 }
7413
7414 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7415 sizeof(tp->net_stats_prev));
7416 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7417 sizeof(tp->estats_prev));
7418
7419 tg3_free_consistent(tp);
7420
7421 tg3_set_power_state(tp, PCI_D3hot);
7422
7423 netif_carrier_off(tp->dev);
7424
7425 return 0;
7426 }
7427
7428 static inline unsigned long get_stat64(tg3_stat64_t *val)
7429 {
7430 unsigned long ret;
7431
7432 #if (BITS_PER_LONG == 32)
7433 ret = val->low;
7434 #else
7435 ret = ((u64)val->high << 32) | ((u64)val->low);
7436 #endif
7437 return ret;
7438 }
7439
7440 static unsigned long calc_crc_errors(struct tg3 *tp)
7441 {
7442 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7443
7444 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7445 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7446 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7447 u32 val;
7448
7449 spin_lock_bh(&tp->lock);
7450 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7451 tg3_writephy(tp, MII_TG3_TEST1,
7452 val | MII_TG3_TEST1_CRC_EN);
7453 tg3_readphy(tp, 0x14, &val);
7454 } else
7455 val = 0;
7456 spin_unlock_bh(&tp->lock);
7457
7458 tp->phy_crc_errors += val;
7459
7460 return tp->phy_crc_errors;
7461 }
7462
7463 return get_stat64(&hw_stats->rx_fcs_errors);
7464 }
7465
7466 #define ESTAT_ADD(member) \
7467 estats->member = old_estats->member + \
7468 get_stat64(&hw_stats->member)
7469
7470 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7471 {
7472 struct tg3_ethtool_stats *estats = &tp->estats;
7473 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7474 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7475
7476 if (!hw_stats)
7477 return old_estats;
7478
7479 ESTAT_ADD(rx_octets);
7480 ESTAT_ADD(rx_fragments);
7481 ESTAT_ADD(rx_ucast_packets);
7482 ESTAT_ADD(rx_mcast_packets);
7483 ESTAT_ADD(rx_bcast_packets);
7484 ESTAT_ADD(rx_fcs_errors);
7485 ESTAT_ADD(rx_align_errors);
7486 ESTAT_ADD(rx_xon_pause_rcvd);
7487 ESTAT_ADD(rx_xoff_pause_rcvd);
7488 ESTAT_ADD(rx_mac_ctrl_rcvd);
7489 ESTAT_ADD(rx_xoff_entered);
7490 ESTAT_ADD(rx_frame_too_long_errors);
7491 ESTAT_ADD(rx_jabbers);
7492 ESTAT_ADD(rx_undersize_packets);
7493 ESTAT_ADD(rx_in_length_errors);
7494 ESTAT_ADD(rx_out_length_errors);
7495 ESTAT_ADD(rx_64_or_less_octet_packets);
7496 ESTAT_ADD(rx_65_to_127_octet_packets);
7497 ESTAT_ADD(rx_128_to_255_octet_packets);
7498 ESTAT_ADD(rx_256_to_511_octet_packets);
7499 ESTAT_ADD(rx_512_to_1023_octet_packets);
7500 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7501 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7502 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7503 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7504 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7505
7506 ESTAT_ADD(tx_octets);
7507 ESTAT_ADD(tx_collisions);
7508 ESTAT_ADD(tx_xon_sent);
7509 ESTAT_ADD(tx_xoff_sent);
7510 ESTAT_ADD(tx_flow_control);
7511 ESTAT_ADD(tx_mac_errors);
7512 ESTAT_ADD(tx_single_collisions);
7513 ESTAT_ADD(tx_mult_collisions);
7514 ESTAT_ADD(tx_deferred);
7515 ESTAT_ADD(tx_excessive_collisions);
7516 ESTAT_ADD(tx_late_collisions);
7517 ESTAT_ADD(tx_collide_2times);
7518 ESTAT_ADD(tx_collide_3times);
7519 ESTAT_ADD(tx_collide_4times);
7520 ESTAT_ADD(tx_collide_5times);
7521 ESTAT_ADD(tx_collide_6times);
7522 ESTAT_ADD(tx_collide_7times);
7523 ESTAT_ADD(tx_collide_8times);
7524 ESTAT_ADD(tx_collide_9times);
7525 ESTAT_ADD(tx_collide_10times);
7526 ESTAT_ADD(tx_collide_11times);
7527 ESTAT_ADD(tx_collide_12times);
7528 ESTAT_ADD(tx_collide_13times);
7529 ESTAT_ADD(tx_collide_14times);
7530 ESTAT_ADD(tx_collide_15times);
7531 ESTAT_ADD(tx_ucast_packets);
7532 ESTAT_ADD(tx_mcast_packets);
7533 ESTAT_ADD(tx_bcast_packets);
7534 ESTAT_ADD(tx_carrier_sense_errors);
7535 ESTAT_ADD(tx_discards);
7536 ESTAT_ADD(tx_errors);
7537
7538 ESTAT_ADD(dma_writeq_full);
7539 ESTAT_ADD(dma_write_prioq_full);
7540 ESTAT_ADD(rxbds_empty);
7541 ESTAT_ADD(rx_discards);
7542 ESTAT_ADD(rx_errors);
7543 ESTAT_ADD(rx_threshold_hit);
7544
7545 ESTAT_ADD(dma_readq_full);
7546 ESTAT_ADD(dma_read_prioq_full);
7547 ESTAT_ADD(tx_comp_queue_full);
7548
7549 ESTAT_ADD(ring_set_send_prod_index);
7550 ESTAT_ADD(ring_status_update);
7551 ESTAT_ADD(nic_irqs);
7552 ESTAT_ADD(nic_avoided_irqs);
7553 ESTAT_ADD(nic_tx_threshold_hit);
7554
7555 return estats;
7556 }
7557
7558 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7559 {
7560 struct tg3 *tp = netdev_priv(dev);
7561 struct net_device_stats *stats = &tp->net_stats;
7562 struct net_device_stats *old_stats = &tp->net_stats_prev;
7563 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7564
7565 if (!hw_stats)
7566 return old_stats;
7567
7568 stats->rx_packets = old_stats->rx_packets +
7569 get_stat64(&hw_stats->rx_ucast_packets) +
7570 get_stat64(&hw_stats->rx_mcast_packets) +
7571 get_stat64(&hw_stats->rx_bcast_packets);
7572
7573 stats->tx_packets = old_stats->tx_packets +
7574 get_stat64(&hw_stats->tx_ucast_packets) +
7575 get_stat64(&hw_stats->tx_mcast_packets) +
7576 get_stat64(&hw_stats->tx_bcast_packets);
7577
7578 stats->rx_bytes = old_stats->rx_bytes +
7579 get_stat64(&hw_stats->rx_octets);
7580 stats->tx_bytes = old_stats->tx_bytes +
7581 get_stat64(&hw_stats->tx_octets);
7582
7583 stats->rx_errors = old_stats->rx_errors +
7584 get_stat64(&hw_stats->rx_errors);
7585 stats->tx_errors = old_stats->tx_errors +
7586 get_stat64(&hw_stats->tx_errors) +
7587 get_stat64(&hw_stats->tx_mac_errors) +
7588 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7589 get_stat64(&hw_stats->tx_discards);
7590
7591 stats->multicast = old_stats->multicast +
7592 get_stat64(&hw_stats->rx_mcast_packets);
7593 stats->collisions = old_stats->collisions +
7594 get_stat64(&hw_stats->tx_collisions);
7595
7596 stats->rx_length_errors = old_stats->rx_length_errors +
7597 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7598 get_stat64(&hw_stats->rx_undersize_packets);
7599
7600 stats->rx_over_errors = old_stats->rx_over_errors +
7601 get_stat64(&hw_stats->rxbds_empty);
7602 stats->rx_frame_errors = old_stats->rx_frame_errors +
7603 get_stat64(&hw_stats->rx_align_errors);
7604 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7605 get_stat64(&hw_stats->tx_discards);
7606 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7607 get_stat64(&hw_stats->tx_carrier_sense_errors);
7608
7609 stats->rx_crc_errors = old_stats->rx_crc_errors +
7610 calc_crc_errors(tp);
7611
7612 stats->rx_missed_errors = old_stats->rx_missed_errors +
7613 get_stat64(&hw_stats->rx_discards);
7614
7615 return stats;
7616 }
7617
7618 static inline u32 calc_crc(unsigned char *buf, int len)
7619 {
7620 u32 reg;
7621 u32 tmp;
7622 int j, k;
7623
7624 reg = 0xffffffff;
7625
7626 for (j = 0; j < len; j++) {
7627 reg ^= buf[j];
7628
7629 for (k = 0; k < 8; k++) {
7630 tmp = reg & 0x01;
7631
7632 reg >>= 1;
7633
7634 if (tmp) {
7635 reg ^= 0xedb88320;
7636 }
7637 }
7638 }
7639
7640 return ~reg;
7641 }
7642
7643 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7644 {
7645 /* accept or reject all multicast frames */
7646 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7647 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7648 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7649 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7650 }
7651
7652 static void __tg3_set_rx_mode(struct net_device *dev)
7653 {
7654 struct tg3 *tp = netdev_priv(dev);
7655 u32 rx_mode;
7656
7657 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7658 RX_MODE_KEEP_VLAN_TAG);
7659
7660 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7661 * flag clear.
7662 */
7663 #if TG3_VLAN_TAG_USED
7664 if (!tp->vlgrp &&
7665 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7666 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7667 #else
7668 /* By definition, VLAN is disabled always in this
7669 * case.
7670 */
7671 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7672 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7673 #endif
7674
7675 if (dev->flags & IFF_PROMISC) {
7676 /* Promiscuous mode. */
7677 rx_mode |= RX_MODE_PROMISC;
7678 } else if (dev->flags & IFF_ALLMULTI) {
7679 /* Accept all multicast. */
7680 tg3_set_multi (tp, 1);
7681 } else if (dev->mc_count < 1) {
7682 /* Reject all multicast. */
7683 tg3_set_multi (tp, 0);
7684 } else {
7685 /* Accept one or more multicast(s). */
7686 struct dev_mc_list *mclist;
7687 unsigned int i;
7688 u32 mc_filter[4] = { 0, };
7689 u32 regidx;
7690 u32 bit;
7691 u32 crc;
7692
7693 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7694 i++, mclist = mclist->next) {
7695
7696 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7697 bit = ~crc & 0x7f;
7698 regidx = (bit & 0x60) >> 5;
7699 bit &= 0x1f;
7700 mc_filter[regidx] |= (1 << bit);
7701 }
7702
7703 tw32(MAC_HASH_REG_0, mc_filter[0]);
7704 tw32(MAC_HASH_REG_1, mc_filter[1]);
7705 tw32(MAC_HASH_REG_2, mc_filter[2]);
7706 tw32(MAC_HASH_REG_3, mc_filter[3]);
7707 }
7708
7709 if (rx_mode != tp->rx_mode) {
7710 tp->rx_mode = rx_mode;
7711 tw32_f(MAC_RX_MODE, rx_mode);
7712 udelay(10);
7713 }
7714 }
7715
7716 static void tg3_set_rx_mode(struct net_device *dev)
7717 {
7718 struct tg3 *tp = netdev_priv(dev);
7719
7720 if (!netif_running(dev))
7721 return;
7722
7723 tg3_full_lock(tp, 0);
7724 __tg3_set_rx_mode(dev);
7725 tg3_full_unlock(tp);
7726 }
7727
7728 #define TG3_REGDUMP_LEN (32 * 1024)
7729
7730 static int tg3_get_regs_len(struct net_device *dev)
7731 {
7732 return TG3_REGDUMP_LEN;
7733 }
7734
7735 static void tg3_get_regs(struct net_device *dev,
7736 struct ethtool_regs *regs, void *_p)
7737 {
7738 u32 *p = _p;
7739 struct tg3 *tp = netdev_priv(dev);
7740 u8 *orig_p = _p;
7741 int i;
7742
7743 regs->version = 0;
7744
7745 memset(p, 0, TG3_REGDUMP_LEN);
7746
7747 if (tp->link_config.phy_is_low_power)
7748 return;
7749
7750 tg3_full_lock(tp, 0);
7751
7752 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7753 #define GET_REG32_LOOP(base,len) \
7754 do { p = (u32 *)(orig_p + (base)); \
7755 for (i = 0; i < len; i += 4) \
7756 __GET_REG32((base) + i); \
7757 } while (0)
7758 #define GET_REG32_1(reg) \
7759 do { p = (u32 *)(orig_p + (reg)); \
7760 __GET_REG32((reg)); \
7761 } while (0)
7762
7763 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7764 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7765 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7766 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7767 GET_REG32_1(SNDDATAC_MODE);
7768 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7769 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7770 GET_REG32_1(SNDBDC_MODE);
7771 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7772 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7773 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7774 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7775 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7776 GET_REG32_1(RCVDCC_MODE);
7777 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7778 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7779 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7780 GET_REG32_1(MBFREE_MODE);
7781 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7782 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7783 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7784 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7785 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7786 GET_REG32_1(RX_CPU_MODE);
7787 GET_REG32_1(RX_CPU_STATE);
7788 GET_REG32_1(RX_CPU_PGMCTR);
7789 GET_REG32_1(RX_CPU_HWBKPT);
7790 GET_REG32_1(TX_CPU_MODE);
7791 GET_REG32_1(TX_CPU_STATE);
7792 GET_REG32_1(TX_CPU_PGMCTR);
7793 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7794 GET_REG32_LOOP(FTQ_RESET, 0x120);
7795 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7796 GET_REG32_1(DMAC_MODE);
7797 GET_REG32_LOOP(GRC_MODE, 0x4c);
7798 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7799 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7800
7801 #undef __GET_REG32
7802 #undef GET_REG32_LOOP
7803 #undef GET_REG32_1
7804
7805 tg3_full_unlock(tp);
7806 }
7807
7808 static int tg3_get_eeprom_len(struct net_device *dev)
7809 {
7810 struct tg3 *tp = netdev_priv(dev);
7811
7812 return tp->nvram_size;
7813 }
7814
7815 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7816 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7817
7818 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7819 {
7820 struct tg3 *tp = netdev_priv(dev);
7821 int ret;
7822 u8 *pd;
7823 u32 i, offset, len, val, b_offset, b_count;
7824
7825 if (tp->link_config.phy_is_low_power)
7826 return -EAGAIN;
7827
7828 offset = eeprom->offset;
7829 len = eeprom->len;
7830 eeprom->len = 0;
7831
7832 eeprom->magic = TG3_EEPROM_MAGIC;
7833
7834 if (offset & 3) {
7835 /* adjustments to start on required 4 byte boundary */
7836 b_offset = offset & 3;
7837 b_count = 4 - b_offset;
7838 if (b_count > len) {
7839 /* i.e. offset=1 len=2 */
7840 b_count = len;
7841 }
7842 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7843 if (ret)
7844 return ret;
7845 val = cpu_to_le32(val);
7846 memcpy(data, ((char*)&val) + b_offset, b_count);
7847 len -= b_count;
7848 offset += b_count;
7849 eeprom->len += b_count;
7850 }
7851
7852 /* read bytes upto the last 4 byte boundary */
7853 pd = &data[eeprom->len];
7854 for (i = 0; i < (len - (len & 3)); i += 4) {
7855 ret = tg3_nvram_read(tp, offset + i, &val);
7856 if (ret) {
7857 eeprom->len += i;
7858 return ret;
7859 }
7860 val = cpu_to_le32(val);
7861 memcpy(pd + i, &val, 4);
7862 }
7863 eeprom->len += i;
7864
7865 if (len & 3) {
7866 /* read last bytes not ending on 4 byte boundary */
7867 pd = &data[eeprom->len];
7868 b_count = len & 3;
7869 b_offset = offset + len - b_count;
7870 ret = tg3_nvram_read(tp, b_offset, &val);
7871 if (ret)
7872 return ret;
7873 val = cpu_to_le32(val);
7874 memcpy(pd, ((char*)&val), b_count);
7875 eeprom->len += b_count;
7876 }
7877 return 0;
7878 }
7879
7880 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7881
7882 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7883 {
7884 struct tg3 *tp = netdev_priv(dev);
7885 int ret;
7886 u32 offset, len, b_offset, odd_len, start, end;
7887 u8 *buf;
7888
7889 if (tp->link_config.phy_is_low_power)
7890 return -EAGAIN;
7891
7892 if (eeprom->magic != TG3_EEPROM_MAGIC)
7893 return -EINVAL;
7894
7895 offset = eeprom->offset;
7896 len = eeprom->len;
7897
7898 if ((b_offset = (offset & 3))) {
7899 /* adjustments to start on required 4 byte boundary */
7900 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7901 if (ret)
7902 return ret;
7903 start = cpu_to_le32(start);
7904 len += b_offset;
7905 offset &= ~3;
7906 if (len < 4)
7907 len = 4;
7908 }
7909
7910 odd_len = 0;
7911 if (len & 3) {
7912 /* adjustments to end on required 4 byte boundary */
7913 odd_len = 1;
7914 len = (len + 3) & ~3;
7915 ret = tg3_nvram_read(tp, offset+len-4, &end);
7916 if (ret)
7917 return ret;
7918 end = cpu_to_le32(end);
7919 }
7920
7921 buf = data;
7922 if (b_offset || odd_len) {
7923 buf = kmalloc(len, GFP_KERNEL);
7924 if (buf == 0)
7925 return -ENOMEM;
7926 if (b_offset)
7927 memcpy(buf, &start, 4);
7928 if (odd_len)
7929 memcpy(buf+len-4, &end, 4);
7930 memcpy(buf + b_offset, data, eeprom->len);
7931 }
7932
7933 ret = tg3_nvram_write_block(tp, offset, len, buf);
7934
7935 if (buf != data)
7936 kfree(buf);
7937
7938 return ret;
7939 }
7940
7941 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7942 {
7943 struct tg3 *tp = netdev_priv(dev);
7944
7945 cmd->supported = (SUPPORTED_Autoneg);
7946
7947 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7948 cmd->supported |= (SUPPORTED_1000baseT_Half |
7949 SUPPORTED_1000baseT_Full);
7950
7951 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7952 cmd->supported |= (SUPPORTED_100baseT_Half |
7953 SUPPORTED_100baseT_Full |
7954 SUPPORTED_10baseT_Half |
7955 SUPPORTED_10baseT_Full |
7956 SUPPORTED_MII);
7957 cmd->port = PORT_TP;
7958 } else {
7959 cmd->supported |= SUPPORTED_FIBRE;
7960 cmd->port = PORT_FIBRE;
7961 }
7962
7963 cmd->advertising = tp->link_config.advertising;
7964 if (netif_running(dev)) {
7965 cmd->speed = tp->link_config.active_speed;
7966 cmd->duplex = tp->link_config.active_duplex;
7967 }
7968 cmd->phy_address = PHY_ADDR;
7969 cmd->transceiver = 0;
7970 cmd->autoneg = tp->link_config.autoneg;
7971 cmd->maxtxpkt = 0;
7972 cmd->maxrxpkt = 0;
7973 return 0;
7974 }
7975
7976 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7977 {
7978 struct tg3 *tp = netdev_priv(dev);
7979
7980 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7981 /* These are the only valid advertisement bits allowed. */
7982 if (cmd->autoneg == AUTONEG_ENABLE &&
7983 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7984 ADVERTISED_1000baseT_Full |
7985 ADVERTISED_Autoneg |
7986 ADVERTISED_FIBRE)))
7987 return -EINVAL;
7988 /* Fiber can only do SPEED_1000. */
7989 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7990 (cmd->speed != SPEED_1000))
7991 return -EINVAL;
7992 /* Copper cannot force SPEED_1000. */
7993 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7994 (cmd->speed == SPEED_1000))
7995 return -EINVAL;
7996 else if ((cmd->speed == SPEED_1000) &&
7997 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7998 return -EINVAL;
7999
8000 tg3_full_lock(tp, 0);
8001
8002 tp->link_config.autoneg = cmd->autoneg;
8003 if (cmd->autoneg == AUTONEG_ENABLE) {
8004 tp->link_config.advertising = cmd->advertising;
8005 tp->link_config.speed = SPEED_INVALID;
8006 tp->link_config.duplex = DUPLEX_INVALID;
8007 } else {
8008 tp->link_config.advertising = 0;
8009 tp->link_config.speed = cmd->speed;
8010 tp->link_config.duplex = cmd->duplex;
8011 }
8012
8013 tp->link_config.orig_speed = tp->link_config.speed;
8014 tp->link_config.orig_duplex = tp->link_config.duplex;
8015 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8016
8017 if (netif_running(dev))
8018 tg3_setup_phy(tp, 1);
8019
8020 tg3_full_unlock(tp);
8021
8022 return 0;
8023 }
8024
8025 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8026 {
8027 struct tg3 *tp = netdev_priv(dev);
8028
8029 strcpy(info->driver, DRV_MODULE_NAME);
8030 strcpy(info->version, DRV_MODULE_VERSION);
8031 strcpy(info->fw_version, tp->fw_ver);
8032 strcpy(info->bus_info, pci_name(tp->pdev));
8033 }
8034
8035 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8036 {
8037 struct tg3 *tp = netdev_priv(dev);
8038
8039 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8040 wol->supported = WAKE_MAGIC;
8041 else
8042 wol->supported = 0;
8043 wol->wolopts = 0;
8044 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8045 wol->wolopts = WAKE_MAGIC;
8046 memset(&wol->sopass, 0, sizeof(wol->sopass));
8047 }
8048
8049 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8050 {
8051 struct tg3 *tp = netdev_priv(dev);
8052
8053 if (wol->wolopts & ~WAKE_MAGIC)
8054 return -EINVAL;
8055 if ((wol->wolopts & WAKE_MAGIC) &&
8056 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8057 return -EINVAL;
8058
8059 spin_lock_bh(&tp->lock);
8060 if (wol->wolopts & WAKE_MAGIC)
8061 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8062 else
8063 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8064 spin_unlock_bh(&tp->lock);
8065
8066 return 0;
8067 }
8068
8069 static u32 tg3_get_msglevel(struct net_device *dev)
8070 {
8071 struct tg3 *tp = netdev_priv(dev);
8072 return tp->msg_enable;
8073 }
8074
8075 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8076 {
8077 struct tg3 *tp = netdev_priv(dev);
8078 tp->msg_enable = value;
8079 }
8080
8081 static int tg3_set_tso(struct net_device *dev, u32 value)
8082 {
8083 struct tg3 *tp = netdev_priv(dev);
8084
8085 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8086 if (value)
8087 return -EINVAL;
8088 return 0;
8089 }
8090 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8091 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8092 if (value)
8093 dev->features |= NETIF_F_TSO6;
8094 else
8095 dev->features &= ~NETIF_F_TSO6;
8096 }
8097 return ethtool_op_set_tso(dev, value);
8098 }
8099
8100 static int tg3_nway_reset(struct net_device *dev)
8101 {
8102 struct tg3 *tp = netdev_priv(dev);
8103 u32 bmcr;
8104 int r;
8105
8106 if (!netif_running(dev))
8107 return -EAGAIN;
8108
8109 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8110 return -EINVAL;
8111
8112 spin_lock_bh(&tp->lock);
8113 r = -EINVAL;
8114 tg3_readphy(tp, MII_BMCR, &bmcr);
8115 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8116 ((bmcr & BMCR_ANENABLE) ||
8117 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8118 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8119 BMCR_ANENABLE);
8120 r = 0;
8121 }
8122 spin_unlock_bh(&tp->lock);
8123
8124 return r;
8125 }
8126
8127 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8128 {
8129 struct tg3 *tp = netdev_priv(dev);
8130
8131 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8132 ering->rx_mini_max_pending = 0;
8133 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8134 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8135 else
8136 ering->rx_jumbo_max_pending = 0;
8137
8138 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8139
8140 ering->rx_pending = tp->rx_pending;
8141 ering->rx_mini_pending = 0;
8142 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8143 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8144 else
8145 ering->rx_jumbo_pending = 0;
8146
8147 ering->tx_pending = tp->tx_pending;
8148 }
8149
8150 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8151 {
8152 struct tg3 *tp = netdev_priv(dev);
8153 int irq_sync = 0, err = 0;
8154
8155 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8156 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8157 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8158 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8159 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8160 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8161 return -EINVAL;
8162
8163 if (netif_running(dev)) {
8164 tg3_netif_stop(tp);
8165 irq_sync = 1;
8166 }
8167
8168 tg3_full_lock(tp, irq_sync);
8169
8170 tp->rx_pending = ering->rx_pending;
8171
8172 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8173 tp->rx_pending > 63)
8174 tp->rx_pending = 63;
8175 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8176 tp->tx_pending = ering->tx_pending;
8177
8178 if (netif_running(dev)) {
8179 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8180 err = tg3_restart_hw(tp, 1);
8181 if (!err)
8182 tg3_netif_start(tp);
8183 }
8184
8185 tg3_full_unlock(tp);
8186
8187 return err;
8188 }
8189
8190 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8191 {
8192 struct tg3 *tp = netdev_priv(dev);
8193
8194 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8195 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8196 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8197 }
8198
8199 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8200 {
8201 struct tg3 *tp = netdev_priv(dev);
8202 int irq_sync = 0, err = 0;
8203
8204 if (netif_running(dev)) {
8205 tg3_netif_stop(tp);
8206 irq_sync = 1;
8207 }
8208
8209 tg3_full_lock(tp, irq_sync);
8210
8211 if (epause->autoneg)
8212 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8213 else
8214 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8215 if (epause->rx_pause)
8216 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8217 else
8218 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8219 if (epause->tx_pause)
8220 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8221 else
8222 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8223
8224 if (netif_running(dev)) {
8225 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8226 err = tg3_restart_hw(tp, 1);
8227 if (!err)
8228 tg3_netif_start(tp);
8229 }
8230
8231 tg3_full_unlock(tp);
8232
8233 return err;
8234 }
8235
8236 static u32 tg3_get_rx_csum(struct net_device *dev)
8237 {
8238 struct tg3 *tp = netdev_priv(dev);
8239 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8240 }
8241
8242 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8243 {
8244 struct tg3 *tp = netdev_priv(dev);
8245
8246 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8247 if (data != 0)
8248 return -EINVAL;
8249 return 0;
8250 }
8251
8252 spin_lock_bh(&tp->lock);
8253 if (data)
8254 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8255 else
8256 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8257 spin_unlock_bh(&tp->lock);
8258
8259 return 0;
8260 }
8261
8262 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8263 {
8264 struct tg3 *tp = netdev_priv(dev);
8265
8266 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8267 if (data != 0)
8268 return -EINVAL;
8269 return 0;
8270 }
8271
8272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8274 ethtool_op_set_tx_hw_csum(dev, data);
8275 else
8276 ethtool_op_set_tx_csum(dev, data);
8277
8278 return 0;
8279 }
8280
8281 static int tg3_get_stats_count (struct net_device *dev)
8282 {
8283 return TG3_NUM_STATS;
8284 }
8285
8286 static int tg3_get_test_count (struct net_device *dev)
8287 {
8288 return TG3_NUM_TEST;
8289 }
8290
8291 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8292 {
8293 switch (stringset) {
8294 case ETH_SS_STATS:
8295 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8296 break;
8297 case ETH_SS_TEST:
8298 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8299 break;
8300 default:
8301 WARN_ON(1); /* we need a WARN() */
8302 break;
8303 }
8304 }
8305
8306 static int tg3_phys_id(struct net_device *dev, u32 data)
8307 {
8308 struct tg3 *tp = netdev_priv(dev);
8309 int i;
8310
8311 if (!netif_running(tp->dev))
8312 return -EAGAIN;
8313
8314 if (data == 0)
8315 data = 2;
8316
8317 for (i = 0; i < (data * 2); i++) {
8318 if ((i % 2) == 0)
8319 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8320 LED_CTRL_1000MBPS_ON |
8321 LED_CTRL_100MBPS_ON |
8322 LED_CTRL_10MBPS_ON |
8323 LED_CTRL_TRAFFIC_OVERRIDE |
8324 LED_CTRL_TRAFFIC_BLINK |
8325 LED_CTRL_TRAFFIC_LED);
8326
8327 else
8328 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8329 LED_CTRL_TRAFFIC_OVERRIDE);
8330
8331 if (msleep_interruptible(500))
8332 break;
8333 }
8334 tw32(MAC_LED_CTRL, tp->led_ctrl);
8335 return 0;
8336 }
8337
8338 static void tg3_get_ethtool_stats (struct net_device *dev,
8339 struct ethtool_stats *estats, u64 *tmp_stats)
8340 {
8341 struct tg3 *tp = netdev_priv(dev);
8342 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8343 }
8344
8345 #define NVRAM_TEST_SIZE 0x100
8346 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8347 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8348 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8349
8350 static int tg3_test_nvram(struct tg3 *tp)
8351 {
8352 u32 *buf, csum, magic;
8353 int i, j, err = 0, size;
8354
8355 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8356 return -EIO;
8357
8358 if (magic == TG3_EEPROM_MAGIC)
8359 size = NVRAM_TEST_SIZE;
8360 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8361 if ((magic & 0xe00000) == 0x200000)
8362 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8363 else
8364 return 0;
8365 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8366 size = NVRAM_SELFBOOT_HW_SIZE;
8367 else
8368 return -EIO;
8369
8370 buf = kmalloc(size, GFP_KERNEL);
8371 if (buf == NULL)
8372 return -ENOMEM;
8373
8374 err = -EIO;
8375 for (i = 0, j = 0; i < size; i += 4, j++) {
8376 u32 val;
8377
8378 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8379 break;
8380 buf[j] = cpu_to_le32(val);
8381 }
8382 if (i < size)
8383 goto out;
8384
8385 /* Selfboot format */
8386 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8387 TG3_EEPROM_MAGIC_FW) {
8388 u8 *buf8 = (u8 *) buf, csum8 = 0;
8389
8390 for (i = 0; i < size; i++)
8391 csum8 += buf8[i];
8392
8393 if (csum8 == 0) {
8394 err = 0;
8395 goto out;
8396 }
8397
8398 err = -EIO;
8399 goto out;
8400 }
8401
8402 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8403 TG3_EEPROM_MAGIC_HW) {
8404 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8405 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8406 u8 *buf8 = (u8 *) buf;
8407 int j, k;
8408
8409 /* Separate the parity bits and the data bytes. */
8410 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8411 if ((i == 0) || (i == 8)) {
8412 int l;
8413 u8 msk;
8414
8415 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8416 parity[k++] = buf8[i] & msk;
8417 i++;
8418 }
8419 else if (i == 16) {
8420 int l;
8421 u8 msk;
8422
8423 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8424 parity[k++] = buf8[i] & msk;
8425 i++;
8426
8427 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8428 parity[k++] = buf8[i] & msk;
8429 i++;
8430 }
8431 data[j++] = buf8[i];
8432 }
8433
8434 err = -EIO;
8435 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8436 u8 hw8 = hweight8(data[i]);
8437
8438 if ((hw8 & 0x1) && parity[i])
8439 goto out;
8440 else if (!(hw8 & 0x1) && !parity[i])
8441 goto out;
8442 }
8443 err = 0;
8444 goto out;
8445 }
8446
8447 /* Bootstrap checksum at offset 0x10 */
8448 csum = calc_crc((unsigned char *) buf, 0x10);
8449 if(csum != cpu_to_le32(buf[0x10/4]))
8450 goto out;
8451
8452 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8453 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8454 if (csum != cpu_to_le32(buf[0xfc/4]))
8455 goto out;
8456
8457 err = 0;
8458
8459 out:
8460 kfree(buf);
8461 return err;
8462 }
8463
8464 #define TG3_SERDES_TIMEOUT_SEC 2
8465 #define TG3_COPPER_TIMEOUT_SEC 6
8466
8467 static int tg3_test_link(struct tg3 *tp)
8468 {
8469 int i, max;
8470
8471 if (!netif_running(tp->dev))
8472 return -ENODEV;
8473
8474 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8475 max = TG3_SERDES_TIMEOUT_SEC;
8476 else
8477 max = TG3_COPPER_TIMEOUT_SEC;
8478
8479 for (i = 0; i < max; i++) {
8480 if (netif_carrier_ok(tp->dev))
8481 return 0;
8482
8483 if (msleep_interruptible(1000))
8484 break;
8485 }
8486
8487 return -EIO;
8488 }
8489
8490 /* Only test the commonly used registers */
8491 static int tg3_test_registers(struct tg3 *tp)
8492 {
8493 int i, is_5705, is_5750;
8494 u32 offset, read_mask, write_mask, val, save_val, read_val;
8495 static struct {
8496 u16 offset;
8497 u16 flags;
8498 #define TG3_FL_5705 0x1
8499 #define TG3_FL_NOT_5705 0x2
8500 #define TG3_FL_NOT_5788 0x4
8501 #define TG3_FL_NOT_5750 0x8
8502 u32 read_mask;
8503 u32 write_mask;
8504 } reg_tbl[] = {
8505 /* MAC Control Registers */
8506 { MAC_MODE, TG3_FL_NOT_5705,
8507 0x00000000, 0x00ef6f8c },
8508 { MAC_MODE, TG3_FL_5705,
8509 0x00000000, 0x01ef6b8c },
8510 { MAC_STATUS, TG3_FL_NOT_5705,
8511 0x03800107, 0x00000000 },
8512 { MAC_STATUS, TG3_FL_5705,
8513 0x03800100, 0x00000000 },
8514 { MAC_ADDR_0_HIGH, 0x0000,
8515 0x00000000, 0x0000ffff },
8516 { MAC_ADDR_0_LOW, 0x0000,
8517 0x00000000, 0xffffffff },
8518 { MAC_RX_MTU_SIZE, 0x0000,
8519 0x00000000, 0x0000ffff },
8520 { MAC_TX_MODE, 0x0000,
8521 0x00000000, 0x00000070 },
8522 { MAC_TX_LENGTHS, 0x0000,
8523 0x00000000, 0x00003fff },
8524 { MAC_RX_MODE, TG3_FL_NOT_5705,
8525 0x00000000, 0x000007fc },
8526 { MAC_RX_MODE, TG3_FL_5705,
8527 0x00000000, 0x000007dc },
8528 { MAC_HASH_REG_0, 0x0000,
8529 0x00000000, 0xffffffff },
8530 { MAC_HASH_REG_1, 0x0000,
8531 0x00000000, 0xffffffff },
8532 { MAC_HASH_REG_2, 0x0000,
8533 0x00000000, 0xffffffff },
8534 { MAC_HASH_REG_3, 0x0000,
8535 0x00000000, 0xffffffff },
8536
8537 /* Receive Data and Receive BD Initiator Control Registers. */
8538 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8539 0x00000000, 0xffffffff },
8540 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8541 0x00000000, 0xffffffff },
8542 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8543 0x00000000, 0x00000003 },
8544 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8545 0x00000000, 0xffffffff },
8546 { RCVDBDI_STD_BD+0, 0x0000,
8547 0x00000000, 0xffffffff },
8548 { RCVDBDI_STD_BD+4, 0x0000,
8549 0x00000000, 0xffffffff },
8550 { RCVDBDI_STD_BD+8, 0x0000,
8551 0x00000000, 0xffff0002 },
8552 { RCVDBDI_STD_BD+0xc, 0x0000,
8553 0x00000000, 0xffffffff },
8554
8555 /* Receive BD Initiator Control Registers. */
8556 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8557 0x00000000, 0xffffffff },
8558 { RCVBDI_STD_THRESH, TG3_FL_5705,
8559 0x00000000, 0x000003ff },
8560 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8561 0x00000000, 0xffffffff },
8562
8563 /* Host Coalescing Control Registers. */
8564 { HOSTCC_MODE, TG3_FL_NOT_5705,
8565 0x00000000, 0x00000004 },
8566 { HOSTCC_MODE, TG3_FL_5705,
8567 0x00000000, 0x000000f6 },
8568 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8569 0x00000000, 0xffffffff },
8570 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8571 0x00000000, 0x000003ff },
8572 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8573 0x00000000, 0xffffffff },
8574 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8575 0x00000000, 0x000003ff },
8576 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8577 0x00000000, 0xffffffff },
8578 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8579 0x00000000, 0x000000ff },
8580 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8581 0x00000000, 0xffffffff },
8582 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8583 0x00000000, 0x000000ff },
8584 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8585 0x00000000, 0xffffffff },
8586 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8587 0x00000000, 0xffffffff },
8588 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8589 0x00000000, 0xffffffff },
8590 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8591 0x00000000, 0x000000ff },
8592 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8593 0x00000000, 0xffffffff },
8594 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8595 0x00000000, 0x000000ff },
8596 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8597 0x00000000, 0xffffffff },
8598 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8599 0x00000000, 0xffffffff },
8600 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8601 0x00000000, 0xffffffff },
8602 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8603 0x00000000, 0xffffffff },
8604 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8605 0x00000000, 0xffffffff },
8606 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8607 0xffffffff, 0x00000000 },
8608 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8609 0xffffffff, 0x00000000 },
8610
8611 /* Buffer Manager Control Registers. */
8612 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8613 0x00000000, 0x007fff80 },
8614 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8615 0x00000000, 0x007fffff },
8616 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8617 0x00000000, 0x0000003f },
8618 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8619 0x00000000, 0x000001ff },
8620 { BUFMGR_MB_HIGH_WATER, 0x0000,
8621 0x00000000, 0x000001ff },
8622 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8623 0xffffffff, 0x00000000 },
8624 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8625 0xffffffff, 0x00000000 },
8626
8627 /* Mailbox Registers */
8628 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8629 0x00000000, 0x000001ff },
8630 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8631 0x00000000, 0x000001ff },
8632 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8633 0x00000000, 0x000007ff },
8634 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8635 0x00000000, 0x000001ff },
8636
8637 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8638 };
8639
8640 is_5705 = is_5750 = 0;
8641 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8642 is_5705 = 1;
8643 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8644 is_5750 = 1;
8645 }
8646
8647 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8648 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8649 continue;
8650
8651 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8652 continue;
8653
8654 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8655 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8656 continue;
8657
8658 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8659 continue;
8660
8661 offset = (u32) reg_tbl[i].offset;
8662 read_mask = reg_tbl[i].read_mask;
8663 write_mask = reg_tbl[i].write_mask;
8664
8665 /* Save the original register content */
8666 save_val = tr32(offset);
8667
8668 /* Determine the read-only value. */
8669 read_val = save_val & read_mask;
8670
8671 /* Write zero to the register, then make sure the read-only bits
8672 * are not changed and the read/write bits are all zeros.
8673 */
8674 tw32(offset, 0);
8675
8676 val = tr32(offset);
8677
8678 /* Test the read-only and read/write bits. */
8679 if (((val & read_mask) != read_val) || (val & write_mask))
8680 goto out;
8681
8682 /* Write ones to all the bits defined by RdMask and WrMask, then
8683 * make sure the read-only bits are not changed and the
8684 * read/write bits are all ones.
8685 */
8686 tw32(offset, read_mask | write_mask);
8687
8688 val = tr32(offset);
8689
8690 /* Test the read-only bits. */
8691 if ((val & read_mask) != read_val)
8692 goto out;
8693
8694 /* Test the read/write bits. */
8695 if ((val & write_mask) != write_mask)
8696 goto out;
8697
8698 tw32(offset, save_val);
8699 }
8700
8701 return 0;
8702
8703 out:
8704 if (netif_msg_hw(tp))
8705 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8706 offset);
8707 tw32(offset, save_val);
8708 return -EIO;
8709 }
8710
8711 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8712 {
8713 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8714 int i;
8715 u32 j;
8716
8717 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8718 for (j = 0; j < len; j += 4) {
8719 u32 val;
8720
8721 tg3_write_mem(tp, offset + j, test_pattern[i]);
8722 tg3_read_mem(tp, offset + j, &val);
8723 if (val != test_pattern[i])
8724 return -EIO;
8725 }
8726 }
8727 return 0;
8728 }
8729
8730 static int tg3_test_memory(struct tg3 *tp)
8731 {
8732 static struct mem_entry {
8733 u32 offset;
8734 u32 len;
8735 } mem_tbl_570x[] = {
8736 { 0x00000000, 0x00b50},
8737 { 0x00002000, 0x1c000},
8738 { 0xffffffff, 0x00000}
8739 }, mem_tbl_5705[] = {
8740 { 0x00000100, 0x0000c},
8741 { 0x00000200, 0x00008},
8742 { 0x00004000, 0x00800},
8743 { 0x00006000, 0x01000},
8744 { 0x00008000, 0x02000},
8745 { 0x00010000, 0x0e000},
8746 { 0xffffffff, 0x00000}
8747 }, mem_tbl_5755[] = {
8748 { 0x00000200, 0x00008},
8749 { 0x00004000, 0x00800},
8750 { 0x00006000, 0x00800},
8751 { 0x00008000, 0x02000},
8752 { 0x00010000, 0x0c000},
8753 { 0xffffffff, 0x00000}
8754 }, mem_tbl_5906[] = {
8755 { 0x00000200, 0x00008},
8756 { 0x00004000, 0x00400},
8757 { 0x00006000, 0x00400},
8758 { 0x00008000, 0x01000},
8759 { 0x00010000, 0x01000},
8760 { 0xffffffff, 0x00000}
8761 };
8762 struct mem_entry *mem_tbl;
8763 int err = 0;
8764 int i;
8765
8766 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8768 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8769 mem_tbl = mem_tbl_5755;
8770 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8771 mem_tbl = mem_tbl_5906;
8772 else
8773 mem_tbl = mem_tbl_5705;
8774 } else
8775 mem_tbl = mem_tbl_570x;
8776
8777 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8778 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8779 mem_tbl[i].len)) != 0)
8780 break;
8781 }
8782
8783 return err;
8784 }
8785
8786 #define TG3_MAC_LOOPBACK 0
8787 #define TG3_PHY_LOOPBACK 1
8788
8789 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8790 {
8791 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8792 u32 desc_idx;
8793 struct sk_buff *skb, *rx_skb;
8794 u8 *tx_data;
8795 dma_addr_t map;
8796 int num_pkts, tx_len, rx_len, i, err;
8797 struct tg3_rx_buffer_desc *desc;
8798
8799 if (loopback_mode == TG3_MAC_LOOPBACK) {
8800 /* HW errata - mac loopback fails in some cases on 5780.
8801 * Normal traffic and PHY loopback are not affected by
8802 * errata.
8803 */
8804 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8805 return 0;
8806
8807 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8808 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8809 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8810 mac_mode |= MAC_MODE_PORT_MODE_MII;
8811 else
8812 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8813 tw32(MAC_MODE, mac_mode);
8814 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8815 u32 val;
8816
8817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8818 u32 phytest;
8819
8820 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8821 u32 phy;
8822
8823 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8824 phytest | MII_TG3_EPHY_SHADOW_EN);
8825 if (!tg3_readphy(tp, 0x1b, &phy))
8826 tg3_writephy(tp, 0x1b, phy & ~0x20);
8827 if (!tg3_readphy(tp, 0x10, &phy))
8828 tg3_writephy(tp, 0x10, phy & ~0x4000);
8829 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8830 }
8831 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8832 } else
8833 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8834
8835 tg3_writephy(tp, MII_BMCR, val);
8836 udelay(40);
8837
8838 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8839 MAC_MODE_LINK_POLARITY;
8840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8841 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8842 mac_mode |= MAC_MODE_PORT_MODE_MII;
8843 } else
8844 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8845
8846 /* reset to prevent losing 1st rx packet intermittently */
8847 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8848 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8849 udelay(10);
8850 tw32_f(MAC_RX_MODE, tp->rx_mode);
8851 }
8852 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8853 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8854 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8855 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8856 }
8857 tw32(MAC_MODE, mac_mode);
8858 }
8859 else
8860 return -EINVAL;
8861
8862 err = -EIO;
8863
8864 tx_len = 1514;
8865 skb = netdev_alloc_skb(tp->dev, tx_len);
8866 if (!skb)
8867 return -ENOMEM;
8868
8869 tx_data = skb_put(skb, tx_len);
8870 memcpy(tx_data, tp->dev->dev_addr, 6);
8871 memset(tx_data + 6, 0x0, 8);
8872
8873 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8874
8875 for (i = 14; i < tx_len; i++)
8876 tx_data[i] = (u8) (i & 0xff);
8877
8878 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8879
8880 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8881 HOSTCC_MODE_NOW);
8882
8883 udelay(10);
8884
8885 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8886
8887 num_pkts = 0;
8888
8889 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8890
8891 tp->tx_prod++;
8892 num_pkts++;
8893
8894 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8895 tp->tx_prod);
8896 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8897
8898 udelay(10);
8899
8900 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8901 for (i = 0; i < 25; i++) {
8902 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8903 HOSTCC_MODE_NOW);
8904
8905 udelay(10);
8906
8907 tx_idx = tp->hw_status->idx[0].tx_consumer;
8908 rx_idx = tp->hw_status->idx[0].rx_producer;
8909 if ((tx_idx == tp->tx_prod) &&
8910 (rx_idx == (rx_start_idx + num_pkts)))
8911 break;
8912 }
8913
8914 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8915 dev_kfree_skb(skb);
8916
8917 if (tx_idx != tp->tx_prod)
8918 goto out;
8919
8920 if (rx_idx != rx_start_idx + num_pkts)
8921 goto out;
8922
8923 desc = &tp->rx_rcb[rx_start_idx];
8924 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8925 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8926 if (opaque_key != RXD_OPAQUE_RING_STD)
8927 goto out;
8928
8929 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8930 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8931 goto out;
8932
8933 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8934 if (rx_len != tx_len)
8935 goto out;
8936
8937 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8938
8939 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8940 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8941
8942 for (i = 14; i < tx_len; i++) {
8943 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8944 goto out;
8945 }
8946 err = 0;
8947
8948 /* tg3_free_rings will unmap and free the rx_skb */
8949 out:
8950 return err;
8951 }
8952
8953 #define TG3_MAC_LOOPBACK_FAILED 1
8954 #define TG3_PHY_LOOPBACK_FAILED 2
8955 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8956 TG3_PHY_LOOPBACK_FAILED)
8957
8958 static int tg3_test_loopback(struct tg3 *tp)
8959 {
8960 int err = 0;
8961
8962 if (!netif_running(tp->dev))
8963 return TG3_LOOPBACK_FAILED;
8964
8965 err = tg3_reset_hw(tp, 1);
8966 if (err)
8967 return TG3_LOOPBACK_FAILED;
8968
8969 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8970 err |= TG3_MAC_LOOPBACK_FAILED;
8971 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8972 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8973 err |= TG3_PHY_LOOPBACK_FAILED;
8974 }
8975
8976 return err;
8977 }
8978
8979 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8980 u64 *data)
8981 {
8982 struct tg3 *tp = netdev_priv(dev);
8983
8984 if (tp->link_config.phy_is_low_power)
8985 tg3_set_power_state(tp, PCI_D0);
8986
8987 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8988
8989 if (tg3_test_nvram(tp) != 0) {
8990 etest->flags |= ETH_TEST_FL_FAILED;
8991 data[0] = 1;
8992 }
8993 if (tg3_test_link(tp) != 0) {
8994 etest->flags |= ETH_TEST_FL_FAILED;
8995 data[1] = 1;
8996 }
8997 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8998 int err, irq_sync = 0;
8999
9000 if (netif_running(dev)) {
9001 tg3_netif_stop(tp);
9002 irq_sync = 1;
9003 }
9004
9005 tg3_full_lock(tp, irq_sync);
9006
9007 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9008 err = tg3_nvram_lock(tp);
9009 tg3_halt_cpu(tp, RX_CPU_BASE);
9010 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9011 tg3_halt_cpu(tp, TX_CPU_BASE);
9012 if (!err)
9013 tg3_nvram_unlock(tp);
9014
9015 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9016 tg3_phy_reset(tp);
9017
9018 if (tg3_test_registers(tp) != 0) {
9019 etest->flags |= ETH_TEST_FL_FAILED;
9020 data[2] = 1;
9021 }
9022 if (tg3_test_memory(tp) != 0) {
9023 etest->flags |= ETH_TEST_FL_FAILED;
9024 data[3] = 1;
9025 }
9026 if ((data[4] = tg3_test_loopback(tp)) != 0)
9027 etest->flags |= ETH_TEST_FL_FAILED;
9028
9029 tg3_full_unlock(tp);
9030
9031 if (tg3_test_interrupt(tp) != 0) {
9032 etest->flags |= ETH_TEST_FL_FAILED;
9033 data[5] = 1;
9034 }
9035
9036 tg3_full_lock(tp, 0);
9037
9038 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9039 if (netif_running(dev)) {
9040 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9041 if (!tg3_restart_hw(tp, 1))
9042 tg3_netif_start(tp);
9043 }
9044
9045 tg3_full_unlock(tp);
9046 }
9047 if (tp->link_config.phy_is_low_power)
9048 tg3_set_power_state(tp, PCI_D3hot);
9049
9050 }
9051
9052 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9053 {
9054 struct mii_ioctl_data *data = if_mii(ifr);
9055 struct tg3 *tp = netdev_priv(dev);
9056 int err;
9057
9058 switch(cmd) {
9059 case SIOCGMIIPHY:
9060 data->phy_id = PHY_ADDR;
9061
9062 /* fallthru */
9063 case SIOCGMIIREG: {
9064 u32 mii_regval;
9065
9066 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9067 break; /* We have no PHY */
9068
9069 if (tp->link_config.phy_is_low_power)
9070 return -EAGAIN;
9071
9072 spin_lock_bh(&tp->lock);
9073 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9074 spin_unlock_bh(&tp->lock);
9075
9076 data->val_out = mii_regval;
9077
9078 return err;
9079 }
9080
9081 case SIOCSMIIREG:
9082 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9083 break; /* We have no PHY */
9084
9085 if (!capable(CAP_NET_ADMIN))
9086 return -EPERM;
9087
9088 if (tp->link_config.phy_is_low_power)
9089 return -EAGAIN;
9090
9091 spin_lock_bh(&tp->lock);
9092 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9093 spin_unlock_bh(&tp->lock);
9094
9095 return err;
9096
9097 default:
9098 /* do nothing */
9099 break;
9100 }
9101 return -EOPNOTSUPP;
9102 }
9103
9104 #if TG3_VLAN_TAG_USED
9105 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9106 {
9107 struct tg3 *tp = netdev_priv(dev);
9108
9109 if (netif_running(dev))
9110 tg3_netif_stop(tp);
9111
9112 tg3_full_lock(tp, 0);
9113
9114 tp->vlgrp = grp;
9115
9116 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9117 __tg3_set_rx_mode(dev);
9118
9119 tg3_full_unlock(tp);
9120
9121 if (netif_running(dev))
9122 tg3_netif_start(tp);
9123 }
9124 #endif
9125
9126 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9127 {
9128 struct tg3 *tp = netdev_priv(dev);
9129
9130 memcpy(ec, &tp->coal, sizeof(*ec));
9131 return 0;
9132 }
9133
9134 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9135 {
9136 struct tg3 *tp = netdev_priv(dev);
9137 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9138 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9139
9140 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9141 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9142 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9143 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9144 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9145 }
9146
9147 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9148 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9149 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9150 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9151 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9152 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9153 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9154 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9155 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9156 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9157 return -EINVAL;
9158
9159 /* No rx interrupts will be generated if both are zero */
9160 if ((ec->rx_coalesce_usecs == 0) &&
9161 (ec->rx_max_coalesced_frames == 0))
9162 return -EINVAL;
9163
9164 /* No tx interrupts will be generated if both are zero */
9165 if ((ec->tx_coalesce_usecs == 0) &&
9166 (ec->tx_max_coalesced_frames == 0))
9167 return -EINVAL;
9168
9169 /* Only copy relevant parameters, ignore all others. */
9170 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9171 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9172 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9173 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9174 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9175 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9176 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9177 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9178 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9179
9180 if (netif_running(dev)) {
9181 tg3_full_lock(tp, 0);
9182 __tg3_set_coalesce(tp, &tp->coal);
9183 tg3_full_unlock(tp);
9184 }
9185 return 0;
9186 }
9187
9188 static const struct ethtool_ops tg3_ethtool_ops = {
9189 .get_settings = tg3_get_settings,
9190 .set_settings = tg3_set_settings,
9191 .get_drvinfo = tg3_get_drvinfo,
9192 .get_regs_len = tg3_get_regs_len,
9193 .get_regs = tg3_get_regs,
9194 .get_wol = tg3_get_wol,
9195 .set_wol = tg3_set_wol,
9196 .get_msglevel = tg3_get_msglevel,
9197 .set_msglevel = tg3_set_msglevel,
9198 .nway_reset = tg3_nway_reset,
9199 .get_link = ethtool_op_get_link,
9200 .get_eeprom_len = tg3_get_eeprom_len,
9201 .get_eeprom = tg3_get_eeprom,
9202 .set_eeprom = tg3_set_eeprom,
9203 .get_ringparam = tg3_get_ringparam,
9204 .set_ringparam = tg3_set_ringparam,
9205 .get_pauseparam = tg3_get_pauseparam,
9206 .set_pauseparam = tg3_set_pauseparam,
9207 .get_rx_csum = tg3_get_rx_csum,
9208 .set_rx_csum = tg3_set_rx_csum,
9209 .get_tx_csum = ethtool_op_get_tx_csum,
9210 .set_tx_csum = tg3_set_tx_csum,
9211 .get_sg = ethtool_op_get_sg,
9212 .set_sg = ethtool_op_set_sg,
9213 .get_tso = ethtool_op_get_tso,
9214 .set_tso = tg3_set_tso,
9215 .self_test_count = tg3_get_test_count,
9216 .self_test = tg3_self_test,
9217 .get_strings = tg3_get_strings,
9218 .phys_id = tg3_phys_id,
9219 .get_stats_count = tg3_get_stats_count,
9220 .get_ethtool_stats = tg3_get_ethtool_stats,
9221 .get_coalesce = tg3_get_coalesce,
9222 .set_coalesce = tg3_set_coalesce,
9223 .get_perm_addr = ethtool_op_get_perm_addr,
9224 };
9225
9226 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9227 {
9228 u32 cursize, val, magic;
9229
9230 tp->nvram_size = EEPROM_CHIP_SIZE;
9231
9232 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9233 return;
9234
9235 if ((magic != TG3_EEPROM_MAGIC) &&
9236 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9237 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9238 return;
9239
9240 /*
9241 * Size the chip by reading offsets at increasing powers of two.
9242 * When we encounter our validation signature, we know the addressing
9243 * has wrapped around, and thus have our chip size.
9244 */
9245 cursize = 0x10;
9246
9247 while (cursize < tp->nvram_size) {
9248 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9249 return;
9250
9251 if (val == magic)
9252 break;
9253
9254 cursize <<= 1;
9255 }
9256
9257 tp->nvram_size = cursize;
9258 }
9259
9260 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9261 {
9262 u32 val;
9263
9264 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9265 return;
9266
9267 /* Selfboot format */
9268 if (val != TG3_EEPROM_MAGIC) {
9269 tg3_get_eeprom_size(tp);
9270 return;
9271 }
9272
9273 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9274 if (val != 0) {
9275 tp->nvram_size = (val >> 16) * 1024;
9276 return;
9277 }
9278 }
9279 tp->nvram_size = 0x80000;
9280 }
9281
9282 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9283 {
9284 u32 nvcfg1;
9285
9286 nvcfg1 = tr32(NVRAM_CFG1);
9287 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9288 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9289 }
9290 else {
9291 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9292 tw32(NVRAM_CFG1, nvcfg1);
9293 }
9294
9295 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9296 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9297 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9298 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9299 tp->nvram_jedecnum = JEDEC_ATMEL;
9300 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9301 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9302 break;
9303 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9304 tp->nvram_jedecnum = JEDEC_ATMEL;
9305 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9306 break;
9307 case FLASH_VENDOR_ATMEL_EEPROM:
9308 tp->nvram_jedecnum = JEDEC_ATMEL;
9309 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9310 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9311 break;
9312 case FLASH_VENDOR_ST:
9313 tp->nvram_jedecnum = JEDEC_ST;
9314 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9315 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9316 break;
9317 case FLASH_VENDOR_SAIFUN:
9318 tp->nvram_jedecnum = JEDEC_SAIFUN;
9319 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9320 break;
9321 case FLASH_VENDOR_SST_SMALL:
9322 case FLASH_VENDOR_SST_LARGE:
9323 tp->nvram_jedecnum = JEDEC_SST;
9324 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9325 break;
9326 }
9327 }
9328 else {
9329 tp->nvram_jedecnum = JEDEC_ATMEL;
9330 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9331 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9332 }
9333 }
9334
9335 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9336 {
9337 u32 nvcfg1;
9338
9339 nvcfg1 = tr32(NVRAM_CFG1);
9340
9341 /* NVRAM protection for TPM */
9342 if (nvcfg1 & (1 << 27))
9343 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9344
9345 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9346 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9347 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9348 tp->nvram_jedecnum = JEDEC_ATMEL;
9349 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9350 break;
9351 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9352 tp->nvram_jedecnum = JEDEC_ATMEL;
9353 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9354 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9355 break;
9356 case FLASH_5752VENDOR_ST_M45PE10:
9357 case FLASH_5752VENDOR_ST_M45PE20:
9358 case FLASH_5752VENDOR_ST_M45PE40:
9359 tp->nvram_jedecnum = JEDEC_ST;
9360 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9361 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9362 break;
9363 }
9364
9365 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9366 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9367 case FLASH_5752PAGE_SIZE_256:
9368 tp->nvram_pagesize = 256;
9369 break;
9370 case FLASH_5752PAGE_SIZE_512:
9371 tp->nvram_pagesize = 512;
9372 break;
9373 case FLASH_5752PAGE_SIZE_1K:
9374 tp->nvram_pagesize = 1024;
9375 break;
9376 case FLASH_5752PAGE_SIZE_2K:
9377 tp->nvram_pagesize = 2048;
9378 break;
9379 case FLASH_5752PAGE_SIZE_4K:
9380 tp->nvram_pagesize = 4096;
9381 break;
9382 case FLASH_5752PAGE_SIZE_264:
9383 tp->nvram_pagesize = 264;
9384 break;
9385 }
9386 }
9387 else {
9388 /* For eeprom, set pagesize to maximum eeprom size */
9389 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9390
9391 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9392 tw32(NVRAM_CFG1, nvcfg1);
9393 }
9394 }
9395
9396 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9397 {
9398 u32 nvcfg1, protect = 0;
9399
9400 nvcfg1 = tr32(NVRAM_CFG1);
9401
9402 /* NVRAM protection for TPM */
9403 if (nvcfg1 & (1 << 27)) {
9404 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9405 protect = 1;
9406 }
9407
9408 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9409 switch (nvcfg1) {
9410 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9411 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9412 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9413 tp->nvram_jedecnum = JEDEC_ATMEL;
9414 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9415 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9416 tp->nvram_pagesize = 264;
9417 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9418 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9419 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9420 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9421 else
9422 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9423 break;
9424 case FLASH_5752VENDOR_ST_M45PE10:
9425 case FLASH_5752VENDOR_ST_M45PE20:
9426 case FLASH_5752VENDOR_ST_M45PE40:
9427 tp->nvram_jedecnum = JEDEC_ST;
9428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9429 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9430 tp->nvram_pagesize = 256;
9431 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9432 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9433 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9434 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9435 else
9436 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9437 break;
9438 }
9439 }
9440
9441 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9442 {
9443 u32 nvcfg1;
9444
9445 nvcfg1 = tr32(NVRAM_CFG1);
9446
9447 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9448 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9449 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9450 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9451 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9452 tp->nvram_jedecnum = JEDEC_ATMEL;
9453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9454 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9455
9456 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9457 tw32(NVRAM_CFG1, nvcfg1);
9458 break;
9459 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9460 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9461 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9462 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9463 tp->nvram_jedecnum = JEDEC_ATMEL;
9464 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9465 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9466 tp->nvram_pagesize = 264;
9467 break;
9468 case FLASH_5752VENDOR_ST_M45PE10:
9469 case FLASH_5752VENDOR_ST_M45PE20:
9470 case FLASH_5752VENDOR_ST_M45PE40:
9471 tp->nvram_jedecnum = JEDEC_ST;
9472 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9473 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9474 tp->nvram_pagesize = 256;
9475 break;
9476 }
9477 }
9478
9479 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9480 {
9481 tp->nvram_jedecnum = JEDEC_ATMEL;
9482 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9483 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9484 }
9485
9486 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9487 static void __devinit tg3_nvram_init(struct tg3 *tp)
9488 {
9489 tw32_f(GRC_EEPROM_ADDR,
9490 (EEPROM_ADDR_FSM_RESET |
9491 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9492 EEPROM_ADDR_CLKPERD_SHIFT)));
9493
9494 msleep(1);
9495
9496 /* Enable seeprom accesses. */
9497 tw32_f(GRC_LOCAL_CTRL,
9498 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9499 udelay(100);
9500
9501 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9502 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9503 tp->tg3_flags |= TG3_FLAG_NVRAM;
9504
9505 if (tg3_nvram_lock(tp)) {
9506 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9507 "tg3_nvram_init failed.\n", tp->dev->name);
9508 return;
9509 }
9510 tg3_enable_nvram_access(tp);
9511
9512 tp->nvram_size = 0;
9513
9514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9515 tg3_get_5752_nvram_info(tp);
9516 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9517 tg3_get_5755_nvram_info(tp);
9518 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9519 tg3_get_5787_nvram_info(tp);
9520 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9521 tg3_get_5906_nvram_info(tp);
9522 else
9523 tg3_get_nvram_info(tp);
9524
9525 if (tp->nvram_size == 0)
9526 tg3_get_nvram_size(tp);
9527
9528 tg3_disable_nvram_access(tp);
9529 tg3_nvram_unlock(tp);
9530
9531 } else {
9532 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9533
9534 tg3_get_eeprom_size(tp);
9535 }
9536 }
9537
9538 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9539 u32 offset, u32 *val)
9540 {
9541 u32 tmp;
9542 int i;
9543
9544 if (offset > EEPROM_ADDR_ADDR_MASK ||
9545 (offset % 4) != 0)
9546 return -EINVAL;
9547
9548 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9549 EEPROM_ADDR_DEVID_MASK |
9550 EEPROM_ADDR_READ);
9551 tw32(GRC_EEPROM_ADDR,
9552 tmp |
9553 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9554 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9555 EEPROM_ADDR_ADDR_MASK) |
9556 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9557
9558 for (i = 0; i < 1000; i++) {
9559 tmp = tr32(GRC_EEPROM_ADDR);
9560
9561 if (tmp & EEPROM_ADDR_COMPLETE)
9562 break;
9563 msleep(1);
9564 }
9565 if (!(tmp & EEPROM_ADDR_COMPLETE))
9566 return -EBUSY;
9567
9568 *val = tr32(GRC_EEPROM_DATA);
9569 return 0;
9570 }
9571
9572 #define NVRAM_CMD_TIMEOUT 10000
9573
9574 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9575 {
9576 int i;
9577
9578 tw32(NVRAM_CMD, nvram_cmd);
9579 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9580 udelay(10);
9581 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9582 udelay(10);
9583 break;
9584 }
9585 }
9586 if (i == NVRAM_CMD_TIMEOUT) {
9587 return -EBUSY;
9588 }
9589 return 0;
9590 }
9591
9592 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9593 {
9594 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9595 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9596 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9597 (tp->nvram_jedecnum == JEDEC_ATMEL))
9598
9599 addr = ((addr / tp->nvram_pagesize) <<
9600 ATMEL_AT45DB0X1B_PAGE_POS) +
9601 (addr % tp->nvram_pagesize);
9602
9603 return addr;
9604 }
9605
9606 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9607 {
9608 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9609 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9610 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9611 (tp->nvram_jedecnum == JEDEC_ATMEL))
9612
9613 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9614 tp->nvram_pagesize) +
9615 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9616
9617 return addr;
9618 }
9619
9620 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9621 {
9622 int ret;
9623
9624 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9625 return tg3_nvram_read_using_eeprom(tp, offset, val);
9626
9627 offset = tg3_nvram_phys_addr(tp, offset);
9628
9629 if (offset > NVRAM_ADDR_MSK)
9630 return -EINVAL;
9631
9632 ret = tg3_nvram_lock(tp);
9633 if (ret)
9634 return ret;
9635
9636 tg3_enable_nvram_access(tp);
9637
9638 tw32(NVRAM_ADDR, offset);
9639 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9640 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9641
9642 if (ret == 0)
9643 *val = swab32(tr32(NVRAM_RDDATA));
9644
9645 tg3_disable_nvram_access(tp);
9646
9647 tg3_nvram_unlock(tp);
9648
9649 return ret;
9650 }
9651
9652 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9653 {
9654 int err;
9655 u32 tmp;
9656
9657 err = tg3_nvram_read(tp, offset, &tmp);
9658 *val = swab32(tmp);
9659 return err;
9660 }
9661
9662 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9663 u32 offset, u32 len, u8 *buf)
9664 {
9665 int i, j, rc = 0;
9666 u32 val;
9667
9668 for (i = 0; i < len; i += 4) {
9669 u32 addr, data;
9670
9671 addr = offset + i;
9672
9673 memcpy(&data, buf + i, 4);
9674
9675 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9676
9677 val = tr32(GRC_EEPROM_ADDR);
9678 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9679
9680 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9681 EEPROM_ADDR_READ);
9682 tw32(GRC_EEPROM_ADDR, val |
9683 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9684 (addr & EEPROM_ADDR_ADDR_MASK) |
9685 EEPROM_ADDR_START |
9686 EEPROM_ADDR_WRITE);
9687
9688 for (j = 0; j < 1000; j++) {
9689 val = tr32(GRC_EEPROM_ADDR);
9690
9691 if (val & EEPROM_ADDR_COMPLETE)
9692 break;
9693 msleep(1);
9694 }
9695 if (!(val & EEPROM_ADDR_COMPLETE)) {
9696 rc = -EBUSY;
9697 break;
9698 }
9699 }
9700
9701 return rc;
9702 }
9703
9704 /* offset and length are dword aligned */
9705 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9706 u8 *buf)
9707 {
9708 int ret = 0;
9709 u32 pagesize = tp->nvram_pagesize;
9710 u32 pagemask = pagesize - 1;
9711 u32 nvram_cmd;
9712 u8 *tmp;
9713
9714 tmp = kmalloc(pagesize, GFP_KERNEL);
9715 if (tmp == NULL)
9716 return -ENOMEM;
9717
9718 while (len) {
9719 int j;
9720 u32 phy_addr, page_off, size;
9721
9722 phy_addr = offset & ~pagemask;
9723
9724 for (j = 0; j < pagesize; j += 4) {
9725 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9726 (u32 *) (tmp + j))))
9727 break;
9728 }
9729 if (ret)
9730 break;
9731
9732 page_off = offset & pagemask;
9733 size = pagesize;
9734 if (len < size)
9735 size = len;
9736
9737 len -= size;
9738
9739 memcpy(tmp + page_off, buf, size);
9740
9741 offset = offset + (pagesize - page_off);
9742
9743 tg3_enable_nvram_access(tp);
9744
9745 /*
9746 * Before we can erase the flash page, we need
9747 * to issue a special "write enable" command.
9748 */
9749 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9750
9751 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9752 break;
9753
9754 /* Erase the target page */
9755 tw32(NVRAM_ADDR, phy_addr);
9756
9757 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9758 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9759
9760 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9761 break;
9762
9763 /* Issue another write enable to start the write. */
9764 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9765
9766 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9767 break;
9768
9769 for (j = 0; j < pagesize; j += 4) {
9770 u32 data;
9771
9772 data = *((u32 *) (tmp + j));
9773 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9774
9775 tw32(NVRAM_ADDR, phy_addr + j);
9776
9777 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9778 NVRAM_CMD_WR;
9779
9780 if (j == 0)
9781 nvram_cmd |= NVRAM_CMD_FIRST;
9782 else if (j == (pagesize - 4))
9783 nvram_cmd |= NVRAM_CMD_LAST;
9784
9785 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9786 break;
9787 }
9788 if (ret)
9789 break;
9790 }
9791
9792 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9793 tg3_nvram_exec_cmd(tp, nvram_cmd);
9794
9795 kfree(tmp);
9796
9797 return ret;
9798 }
9799
9800 /* offset and length are dword aligned */
9801 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9802 u8 *buf)
9803 {
9804 int i, ret = 0;
9805
9806 for (i = 0; i < len; i += 4, offset += 4) {
9807 u32 data, page_off, phy_addr, nvram_cmd;
9808
9809 memcpy(&data, buf + i, 4);
9810 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9811
9812 page_off = offset % tp->nvram_pagesize;
9813
9814 phy_addr = tg3_nvram_phys_addr(tp, offset);
9815
9816 tw32(NVRAM_ADDR, phy_addr);
9817
9818 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9819
9820 if ((page_off == 0) || (i == 0))
9821 nvram_cmd |= NVRAM_CMD_FIRST;
9822 if (page_off == (tp->nvram_pagesize - 4))
9823 nvram_cmd |= NVRAM_CMD_LAST;
9824
9825 if (i == (len - 4))
9826 nvram_cmd |= NVRAM_CMD_LAST;
9827
9828 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9829 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9830 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9831 (tp->nvram_jedecnum == JEDEC_ST) &&
9832 (nvram_cmd & NVRAM_CMD_FIRST)) {
9833
9834 if ((ret = tg3_nvram_exec_cmd(tp,
9835 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9836 NVRAM_CMD_DONE)))
9837
9838 break;
9839 }
9840 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9841 /* We always do complete word writes to eeprom. */
9842 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9843 }
9844
9845 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9846 break;
9847 }
9848 return ret;
9849 }
9850
9851 /* offset and length are dword aligned */
9852 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9853 {
9854 int ret;
9855
9856 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9857 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9858 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9859 udelay(40);
9860 }
9861
9862 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9863 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9864 }
9865 else {
9866 u32 grc_mode;
9867
9868 ret = tg3_nvram_lock(tp);
9869 if (ret)
9870 return ret;
9871
9872 tg3_enable_nvram_access(tp);
9873 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9874 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9875 tw32(NVRAM_WRITE1, 0x406);
9876
9877 grc_mode = tr32(GRC_MODE);
9878 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9879
9880 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9881 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9882
9883 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9884 buf);
9885 }
9886 else {
9887 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9888 buf);
9889 }
9890
9891 grc_mode = tr32(GRC_MODE);
9892 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9893
9894 tg3_disable_nvram_access(tp);
9895 tg3_nvram_unlock(tp);
9896 }
9897
9898 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9899 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9900 udelay(40);
9901 }
9902
9903 return ret;
9904 }
9905
9906 struct subsys_tbl_ent {
9907 u16 subsys_vendor, subsys_devid;
9908 u32 phy_id;
9909 };
9910
9911 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9912 /* Broadcom boards. */
9913 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9914 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9915 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9916 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9917 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9918 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9919 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9920 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9921 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9922 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9923 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9924
9925 /* 3com boards. */
9926 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9927 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9928 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9929 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9930 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9931
9932 /* DELL boards. */
9933 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9934 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9935 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9936 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9937
9938 /* Compaq boards. */
9939 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9940 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9941 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9942 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9943 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9944
9945 /* IBM boards. */
9946 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9947 };
9948
9949 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9950 {
9951 int i;
9952
9953 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9954 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9955 tp->pdev->subsystem_vendor) &&
9956 (subsys_id_to_phy_id[i].subsys_devid ==
9957 tp->pdev->subsystem_device))
9958 return &subsys_id_to_phy_id[i];
9959 }
9960 return NULL;
9961 }
9962
9963 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9964 {
9965 u32 val;
9966 u16 pmcsr;
9967
9968 /* On some early chips the SRAM cannot be accessed in D3hot state,
9969 * so need make sure we're in D0.
9970 */
9971 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9972 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9973 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9974 msleep(1);
9975
9976 /* Make sure register accesses (indirect or otherwise)
9977 * will function correctly.
9978 */
9979 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9980 tp->misc_host_ctrl);
9981
9982 /* The memory arbiter has to be enabled in order for SRAM accesses
9983 * to succeed. Normally on powerup the tg3 chip firmware will make
9984 * sure it is enabled, but other entities such as system netboot
9985 * code might disable it.
9986 */
9987 val = tr32(MEMARB_MODE);
9988 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9989
9990 tp->phy_id = PHY_ID_INVALID;
9991 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9992
9993 /* Assume an onboard device and WOL capable by default. */
9994 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
9995
9996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9997 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9998 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9999 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10000 }
10001 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10002 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10003 return;
10004 }
10005
10006 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10007 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10008 u32 nic_cfg, led_cfg;
10009 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10010 int eeprom_phy_serdes = 0;
10011
10012 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10013 tp->nic_sram_data_cfg = nic_cfg;
10014
10015 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10016 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10017 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10018 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10019 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10020 (ver > 0) && (ver < 0x100))
10021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10022
10023 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10024 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10025 eeprom_phy_serdes = 1;
10026
10027 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10028 if (nic_phy_id != 0) {
10029 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10030 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10031
10032 eeprom_phy_id = (id1 >> 16) << 10;
10033 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10034 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10035 } else
10036 eeprom_phy_id = 0;
10037
10038 tp->phy_id = eeprom_phy_id;
10039 if (eeprom_phy_serdes) {
10040 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10041 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10042 else
10043 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10044 }
10045
10046 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10047 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10048 SHASTA_EXT_LED_MODE_MASK);
10049 else
10050 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10051
10052 switch (led_cfg) {
10053 default:
10054 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10055 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10056 break;
10057
10058 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10059 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10060 break;
10061
10062 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10063 tp->led_ctrl = LED_CTRL_MODE_MAC;
10064
10065 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10066 * read on some older 5700/5701 bootcode.
10067 */
10068 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10069 ASIC_REV_5700 ||
10070 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10071 ASIC_REV_5701)
10072 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10073
10074 break;
10075
10076 case SHASTA_EXT_LED_SHARED:
10077 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10078 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10079 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10080 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10081 LED_CTRL_MODE_PHY_2);
10082 break;
10083
10084 case SHASTA_EXT_LED_MAC:
10085 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10086 break;
10087
10088 case SHASTA_EXT_LED_COMBO:
10089 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10090 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10091 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10092 LED_CTRL_MODE_PHY_2);
10093 break;
10094
10095 };
10096
10097 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10099 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10100 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10101
10102 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10103 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10104 if ((tp->pdev->subsystem_vendor ==
10105 PCI_VENDOR_ID_ARIMA) &&
10106 (tp->pdev->subsystem_device == 0x205a ||
10107 tp->pdev->subsystem_device == 0x2063))
10108 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10109 } else {
10110 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10111 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10112 }
10113
10114 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10115 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10116 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10117 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10118 }
10119 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10120 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10121 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10122
10123 if (cfg2 & (1 << 17))
10124 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10125
10126 /* serdes signal pre-emphasis in register 0x590 set by */
10127 /* bootcode if bit 18 is set */
10128 if (cfg2 & (1 << 18))
10129 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10130
10131 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10132 u32 cfg3;
10133
10134 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10135 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10136 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10137 }
10138 }
10139 }
10140
10141 static int __devinit tg3_phy_probe(struct tg3 *tp)
10142 {
10143 u32 hw_phy_id_1, hw_phy_id_2;
10144 u32 hw_phy_id, hw_phy_id_masked;
10145 int err;
10146
10147 /* Reading the PHY ID register can conflict with ASF
10148 * firwmare access to the PHY hardware.
10149 */
10150 err = 0;
10151 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10152 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10153 } else {
10154 /* Now read the physical PHY_ID from the chip and verify
10155 * that it is sane. If it doesn't look good, we fall back
10156 * to either the hard-coded table based PHY_ID and failing
10157 * that the value found in the eeprom area.
10158 */
10159 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10160 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10161
10162 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10163 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10164 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10165
10166 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10167 }
10168
10169 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10170 tp->phy_id = hw_phy_id;
10171 if (hw_phy_id_masked == PHY_ID_BCM8002)
10172 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10173 else
10174 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10175 } else {
10176 if (tp->phy_id != PHY_ID_INVALID) {
10177 /* Do nothing, phy ID already set up in
10178 * tg3_get_eeprom_hw_cfg().
10179 */
10180 } else {
10181 struct subsys_tbl_ent *p;
10182
10183 /* No eeprom signature? Try the hardcoded
10184 * subsys device table.
10185 */
10186 p = lookup_by_subsys(tp);
10187 if (!p)
10188 return -ENODEV;
10189
10190 tp->phy_id = p->phy_id;
10191 if (!tp->phy_id ||
10192 tp->phy_id == PHY_ID_BCM8002)
10193 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10194 }
10195 }
10196
10197 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10198 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10199 u32 bmsr, adv_reg, tg3_ctrl, mask;
10200
10201 tg3_readphy(tp, MII_BMSR, &bmsr);
10202 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10203 (bmsr & BMSR_LSTATUS))
10204 goto skip_phy_reset;
10205
10206 err = tg3_phy_reset(tp);
10207 if (err)
10208 return err;
10209
10210 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10211 ADVERTISE_100HALF | ADVERTISE_100FULL |
10212 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10213 tg3_ctrl = 0;
10214 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10215 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10216 MII_TG3_CTRL_ADV_1000_FULL);
10217 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10218 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10219 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10220 MII_TG3_CTRL_ENABLE_AS_MASTER);
10221 }
10222
10223 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10224 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10225 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10226 if (!tg3_copper_is_advertising_all(tp, mask)) {
10227 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10228
10229 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10230 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10231
10232 tg3_writephy(tp, MII_BMCR,
10233 BMCR_ANENABLE | BMCR_ANRESTART);
10234 }
10235 tg3_phy_set_wirespeed(tp);
10236
10237 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10238 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10239 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10240 }
10241
10242 skip_phy_reset:
10243 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10244 err = tg3_init_5401phy_dsp(tp);
10245 if (err)
10246 return err;
10247 }
10248
10249 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10250 err = tg3_init_5401phy_dsp(tp);
10251 }
10252
10253 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10254 tp->link_config.advertising =
10255 (ADVERTISED_1000baseT_Half |
10256 ADVERTISED_1000baseT_Full |
10257 ADVERTISED_Autoneg |
10258 ADVERTISED_FIBRE);
10259 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10260 tp->link_config.advertising &=
10261 ~(ADVERTISED_1000baseT_Half |
10262 ADVERTISED_1000baseT_Full);
10263
10264 return err;
10265 }
10266
10267 static void __devinit tg3_read_partno(struct tg3 *tp)
10268 {
10269 unsigned char vpd_data[256];
10270 unsigned int i;
10271 u32 magic;
10272
10273 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10274 goto out_not_found;
10275
10276 if (magic == TG3_EEPROM_MAGIC) {
10277 for (i = 0; i < 256; i += 4) {
10278 u32 tmp;
10279
10280 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10281 goto out_not_found;
10282
10283 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10284 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10285 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10286 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10287 }
10288 } else {
10289 int vpd_cap;
10290
10291 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10292 for (i = 0; i < 256; i += 4) {
10293 u32 tmp, j = 0;
10294 u16 tmp16;
10295
10296 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10297 i);
10298 while (j++ < 100) {
10299 pci_read_config_word(tp->pdev, vpd_cap +
10300 PCI_VPD_ADDR, &tmp16);
10301 if (tmp16 & 0x8000)
10302 break;
10303 msleep(1);
10304 }
10305 if (!(tmp16 & 0x8000))
10306 goto out_not_found;
10307
10308 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10309 &tmp);
10310 tmp = cpu_to_le32(tmp);
10311 memcpy(&vpd_data[i], &tmp, 4);
10312 }
10313 }
10314
10315 /* Now parse and find the part number. */
10316 for (i = 0; i < 254; ) {
10317 unsigned char val = vpd_data[i];
10318 unsigned int block_end;
10319
10320 if (val == 0x82 || val == 0x91) {
10321 i = (i + 3 +
10322 (vpd_data[i + 1] +
10323 (vpd_data[i + 2] << 8)));
10324 continue;
10325 }
10326
10327 if (val != 0x90)
10328 goto out_not_found;
10329
10330 block_end = (i + 3 +
10331 (vpd_data[i + 1] +
10332 (vpd_data[i + 2] << 8)));
10333 i += 3;
10334
10335 if (block_end > 256)
10336 goto out_not_found;
10337
10338 while (i < (block_end - 2)) {
10339 if (vpd_data[i + 0] == 'P' &&
10340 vpd_data[i + 1] == 'N') {
10341 int partno_len = vpd_data[i + 2];
10342
10343 i += 3;
10344 if (partno_len > 24 || (partno_len + i) > 256)
10345 goto out_not_found;
10346
10347 memcpy(tp->board_part_number,
10348 &vpd_data[i], partno_len);
10349
10350 /* Success. */
10351 return;
10352 }
10353 i += 3 + vpd_data[i + 2];
10354 }
10355
10356 /* Part number not found. */
10357 goto out_not_found;
10358 }
10359
10360 out_not_found:
10361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10362 strcpy(tp->board_part_number, "BCM95906");
10363 else
10364 strcpy(tp->board_part_number, "none");
10365 }
10366
10367 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10368 {
10369 u32 val, offset, start;
10370
10371 if (tg3_nvram_read_swab(tp, 0, &val))
10372 return;
10373
10374 if (val != TG3_EEPROM_MAGIC)
10375 return;
10376
10377 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10378 tg3_nvram_read_swab(tp, 0x4, &start))
10379 return;
10380
10381 offset = tg3_nvram_logical_addr(tp, offset);
10382 if (tg3_nvram_read_swab(tp, offset, &val))
10383 return;
10384
10385 if ((val & 0xfc000000) == 0x0c000000) {
10386 u32 ver_offset, addr;
10387 int i;
10388
10389 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10390 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10391 return;
10392
10393 if (val != 0)
10394 return;
10395
10396 addr = offset + ver_offset - start;
10397 for (i = 0; i < 16; i += 4) {
10398 if (tg3_nvram_read(tp, addr + i, &val))
10399 return;
10400
10401 val = cpu_to_le32(val);
10402 memcpy(tp->fw_ver + i, &val, 4);
10403 }
10404 }
10405 }
10406
10407 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10408
10409 static int __devinit tg3_get_invariants(struct tg3 *tp)
10410 {
10411 static struct pci_device_id write_reorder_chipsets[] = {
10412 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10413 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10414 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10415 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10416 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10417 PCI_DEVICE_ID_VIA_8385_0) },
10418 { },
10419 };
10420 u32 misc_ctrl_reg;
10421 u32 cacheline_sz_reg;
10422 u32 pci_state_reg, grc_misc_cfg;
10423 u32 val;
10424 u16 pci_cmd;
10425 int err, pcie_cap;
10426
10427 /* Force memory write invalidate off. If we leave it on,
10428 * then on 5700_BX chips we have to enable a workaround.
10429 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10430 * to match the cacheline size. The Broadcom driver have this
10431 * workaround but turns MWI off all the times so never uses
10432 * it. This seems to suggest that the workaround is insufficient.
10433 */
10434 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10435 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10436 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10437
10438 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10439 * has the register indirect write enable bit set before
10440 * we try to access any of the MMIO registers. It is also
10441 * critical that the PCI-X hw workaround situation is decided
10442 * before that as well.
10443 */
10444 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10445 &misc_ctrl_reg);
10446
10447 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10448 MISC_HOST_CTRL_CHIPREV_SHIFT);
10449
10450 /* Wrong chip ID in 5752 A0. This code can be removed later
10451 * as A0 is not in production.
10452 */
10453 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10454 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10455
10456 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10457 * we need to disable memory and use config. cycles
10458 * only to access all registers. The 5702/03 chips
10459 * can mistakenly decode the special cycles from the
10460 * ICH chipsets as memory write cycles, causing corruption
10461 * of register and memory space. Only certain ICH bridges
10462 * will drive special cycles with non-zero data during the
10463 * address phase which can fall within the 5703's address
10464 * range. This is not an ICH bug as the PCI spec allows
10465 * non-zero address during special cycles. However, only
10466 * these ICH bridges are known to drive non-zero addresses
10467 * during special cycles.
10468 *
10469 * Since special cycles do not cross PCI bridges, we only
10470 * enable this workaround if the 5703 is on the secondary
10471 * bus of these ICH bridges.
10472 */
10473 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10474 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10475 static struct tg3_dev_id {
10476 u32 vendor;
10477 u32 device;
10478 u32 rev;
10479 } ich_chipsets[] = {
10480 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10481 PCI_ANY_ID },
10482 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10483 PCI_ANY_ID },
10484 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10485 0xa },
10486 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10487 PCI_ANY_ID },
10488 { },
10489 };
10490 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10491 struct pci_dev *bridge = NULL;
10492
10493 while (pci_id->vendor != 0) {
10494 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10495 bridge);
10496 if (!bridge) {
10497 pci_id++;
10498 continue;
10499 }
10500 if (pci_id->rev != PCI_ANY_ID) {
10501 u8 rev;
10502
10503 pci_read_config_byte(bridge, PCI_REVISION_ID,
10504 &rev);
10505 if (rev > pci_id->rev)
10506 continue;
10507 }
10508 if (bridge->subordinate &&
10509 (bridge->subordinate->number ==
10510 tp->pdev->bus->number)) {
10511
10512 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10513 pci_dev_put(bridge);
10514 break;
10515 }
10516 }
10517 }
10518
10519 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10520 * DMA addresses > 40-bit. This bridge may have other additional
10521 * 57xx devices behind it in some 4-port NIC designs for example.
10522 * Any tg3 device found behind the bridge will also need the 40-bit
10523 * DMA workaround.
10524 */
10525 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10527 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10528 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10529 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10530 }
10531 else {
10532 struct pci_dev *bridge = NULL;
10533
10534 do {
10535 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10536 PCI_DEVICE_ID_SERVERWORKS_EPB,
10537 bridge);
10538 if (bridge && bridge->subordinate &&
10539 (bridge->subordinate->number <=
10540 tp->pdev->bus->number) &&
10541 (bridge->subordinate->subordinate >=
10542 tp->pdev->bus->number)) {
10543 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10544 pci_dev_put(bridge);
10545 break;
10546 }
10547 } while (bridge);
10548 }
10549
10550 /* Initialize misc host control in PCI block. */
10551 tp->misc_host_ctrl |= (misc_ctrl_reg &
10552 MISC_HOST_CTRL_CHIPREV);
10553 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10554 tp->misc_host_ctrl);
10555
10556 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10557 &cacheline_sz_reg);
10558
10559 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10560 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10561 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10562 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10563
10564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10565 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10566 tp->pdev_peer = tg3_find_peer(tp);
10567
10568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10573 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10574 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10575
10576 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10577 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10578 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10579
10580 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10581 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10582 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10583 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10584 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10585 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10586 tp->pdev_peer == tp->pdev))
10587 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10588
10589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10591 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10592 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10593 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10594 } else {
10595 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10596 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10597 ASIC_REV_5750 &&
10598 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10599 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10600 }
10601 }
10602
10603 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10604 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10605 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10606 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10607 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10608 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10609 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10610
10611 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10612 if (pcie_cap != 0) {
10613 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10615 u16 lnkctl;
10616
10617 pci_read_config_word(tp->pdev,
10618 pcie_cap + PCI_EXP_LNKCTL,
10619 &lnkctl);
10620 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10621 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10622 }
10623 }
10624
10625 /* If we have an AMD 762 or VIA K8T800 chipset, write
10626 * reordering to the mailbox registers done by the host
10627 * controller can cause major troubles. We read back from
10628 * every mailbox register write to force the writes to be
10629 * posted to the chip in order.
10630 */
10631 if (pci_dev_present(write_reorder_chipsets) &&
10632 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10633 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10634
10635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10636 tp->pci_lat_timer < 64) {
10637 tp->pci_lat_timer = 64;
10638
10639 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10640 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10641 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10642 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10643
10644 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10645 cacheline_sz_reg);
10646 }
10647
10648 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10649 &pci_state_reg);
10650
10651 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10652 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10653
10654 /* If this is a 5700 BX chipset, and we are in PCI-X
10655 * mode, enable register write workaround.
10656 *
10657 * The workaround is to use indirect register accesses
10658 * for all chip writes not to mailbox registers.
10659 */
10660 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10661 u32 pm_reg;
10662 u16 pci_cmd;
10663
10664 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10665
10666 /* The chip can have it's power management PCI config
10667 * space registers clobbered due to this bug.
10668 * So explicitly force the chip into D0 here.
10669 */
10670 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10671 &pm_reg);
10672 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10673 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10674 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10675 pm_reg);
10676
10677 /* Also, force SERR#/PERR# in PCI command. */
10678 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10679 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10680 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10681 }
10682 }
10683
10684 /* 5700 BX chips need to have their TX producer index mailboxes
10685 * written twice to workaround a bug.
10686 */
10687 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10688 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10689
10690 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10691 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10692 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10693 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10694
10695 /* Chip-specific fixup from Broadcom driver */
10696 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10697 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10698 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10699 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10700 }
10701
10702 /* Default fast path register access methods */
10703 tp->read32 = tg3_read32;
10704 tp->write32 = tg3_write32;
10705 tp->read32_mbox = tg3_read32;
10706 tp->write32_mbox = tg3_write32;
10707 tp->write32_tx_mbox = tg3_write32;
10708 tp->write32_rx_mbox = tg3_write32;
10709
10710 /* Various workaround register access methods */
10711 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10712 tp->write32 = tg3_write_indirect_reg32;
10713 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10714 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10715 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10716 /*
10717 * Back to back register writes can cause problems on these
10718 * chips, the workaround is to read back all reg writes
10719 * except those to mailbox regs.
10720 *
10721 * See tg3_write_indirect_reg32().
10722 */
10723 tp->write32 = tg3_write_flush_reg32;
10724 }
10725
10726
10727 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10728 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10729 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10730 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10731 tp->write32_rx_mbox = tg3_write_flush_reg32;
10732 }
10733
10734 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10735 tp->read32 = tg3_read_indirect_reg32;
10736 tp->write32 = tg3_write_indirect_reg32;
10737 tp->read32_mbox = tg3_read_indirect_mbox;
10738 tp->write32_mbox = tg3_write_indirect_mbox;
10739 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10740 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10741
10742 iounmap(tp->regs);
10743 tp->regs = NULL;
10744
10745 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10746 pci_cmd &= ~PCI_COMMAND_MEMORY;
10747 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10748 }
10749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10750 tp->read32_mbox = tg3_read32_mbox_5906;
10751 tp->write32_mbox = tg3_write32_mbox_5906;
10752 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10753 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10754 }
10755
10756 if (tp->write32 == tg3_write_indirect_reg32 ||
10757 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10758 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10759 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10760 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10761
10762 /* Get eeprom hw config before calling tg3_set_power_state().
10763 * In particular, the TG3_FLG2_IS_NIC flag must be
10764 * determined before calling tg3_set_power_state() so that
10765 * we know whether or not to switch out of Vaux power.
10766 * When the flag is set, it means that GPIO1 is used for eeprom
10767 * write protect and also implies that it is a LOM where GPIOs
10768 * are not used to switch power.
10769 */
10770 tg3_get_eeprom_hw_cfg(tp);
10771
10772 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10773 * GPIO1 driven high will bring 5700's external PHY out of reset.
10774 * It is also used as eeprom write protect on LOMs.
10775 */
10776 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10777 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10778 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10779 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10780 GRC_LCLCTRL_GPIO_OUTPUT1);
10781 /* Unused GPIO3 must be driven as output on 5752 because there
10782 * are no pull-up resistors on unused GPIO pins.
10783 */
10784 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10785 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10786
10787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10788 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10789
10790 /* Force the chip into D0. */
10791 err = tg3_set_power_state(tp, PCI_D0);
10792 if (err) {
10793 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10794 pci_name(tp->pdev));
10795 return err;
10796 }
10797
10798 /* 5700 B0 chips do not support checksumming correctly due
10799 * to hardware bugs.
10800 */
10801 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10802 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10803
10804 /* Derive initial jumbo mode from MTU assigned in
10805 * ether_setup() via the alloc_etherdev() call
10806 */
10807 if (tp->dev->mtu > ETH_DATA_LEN &&
10808 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10809 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10810
10811 /* Determine WakeOnLan speed to use. */
10812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10813 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10814 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10815 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10816 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10817 } else {
10818 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10819 }
10820
10821 /* A few boards don't want Ethernet@WireSpeed phy feature */
10822 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10823 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10824 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10825 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10826 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10827 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10828 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10829
10830 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10831 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10832 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10833 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10834 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10835
10836 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10839 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10840 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10841 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10842 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10843 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10844 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10845 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10846 }
10847
10848 tp->coalesce_mode = 0;
10849 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10850 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10851 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10852
10853 /* Initialize MAC MI mode, polling disabled. */
10854 tw32_f(MAC_MI_MODE, tp->mi_mode);
10855 udelay(80);
10856
10857 /* Initialize data/descriptor byte/word swapping. */
10858 val = tr32(GRC_MODE);
10859 val &= GRC_MODE_HOST_STACKUP;
10860 tw32(GRC_MODE, val | tp->grc_mode);
10861
10862 tg3_switch_clocks(tp);
10863
10864 /* Clear this out for sanity. */
10865 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10866
10867 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10868 &pci_state_reg);
10869 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10870 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10871 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10872
10873 if (chiprevid == CHIPREV_ID_5701_A0 ||
10874 chiprevid == CHIPREV_ID_5701_B0 ||
10875 chiprevid == CHIPREV_ID_5701_B2 ||
10876 chiprevid == CHIPREV_ID_5701_B5) {
10877 void __iomem *sram_base;
10878
10879 /* Write some dummy words into the SRAM status block
10880 * area, see if it reads back correctly. If the return
10881 * value is bad, force enable the PCIX workaround.
10882 */
10883 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10884
10885 writel(0x00000000, sram_base);
10886 writel(0x00000000, sram_base + 4);
10887 writel(0xffffffff, sram_base + 4);
10888 if (readl(sram_base) != 0x00000000)
10889 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10890 }
10891 }
10892
10893 udelay(50);
10894 tg3_nvram_init(tp);
10895
10896 grc_misc_cfg = tr32(GRC_MISC_CFG);
10897 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10898
10899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10900 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10901 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10902 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10903
10904 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10905 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10906 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10907 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10908 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10909 HOSTCC_MODE_CLRTICK_TXBD);
10910
10911 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10912 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10913 tp->misc_host_ctrl);
10914 }
10915
10916 /* these are limited to 10/100 only */
10917 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10918 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10919 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10920 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10921 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10922 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10923 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10924 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10925 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10926 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10927 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10929 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10930
10931 err = tg3_phy_probe(tp);
10932 if (err) {
10933 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10934 pci_name(tp->pdev), err);
10935 /* ... but do not return immediately ... */
10936 }
10937
10938 tg3_read_partno(tp);
10939 tg3_read_fw_ver(tp);
10940
10941 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10942 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10943 } else {
10944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10945 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10946 else
10947 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10948 }
10949
10950 /* 5700 {AX,BX} chips have a broken status block link
10951 * change bit implementation, so we must use the
10952 * status register in those cases.
10953 */
10954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10955 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10956 else
10957 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10958
10959 /* The led_ctrl is set during tg3_phy_probe, here we might
10960 * have to force the link status polling mechanism based
10961 * upon subsystem IDs.
10962 */
10963 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10965 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10966 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10967 TG3_FLAG_USE_LINKCHG_REG);
10968 }
10969
10970 /* For all SERDES we poll the MAC status register. */
10971 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10972 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10973 else
10974 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10975
10976 /* All chips before 5787 can get confused if TX buffers
10977 * straddle the 4GB address boundary in some cases.
10978 */
10979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10982 tp->dev->hard_start_xmit = tg3_start_xmit;
10983 else
10984 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10985
10986 tp->rx_offset = 2;
10987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10988 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10989 tp->rx_offset = 0;
10990
10991 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10992
10993 /* Increment the rx prod index on the rx std ring by at most
10994 * 8 for these chips to workaround hw errata.
10995 */
10996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10999 tp->rx_std_max_post = 8;
11000
11001 /* By default, disable wake-on-lan. User can change this
11002 * using ETHTOOL_SWOL.
11003 */
11004 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11005
11006 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11007 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11008 PCIE_PWR_MGMT_L1_THRESH_MSK;
11009
11010 return err;
11011 }
11012
11013 #ifdef CONFIG_SPARC
11014 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11015 {
11016 struct net_device *dev = tp->dev;
11017 struct pci_dev *pdev = tp->pdev;
11018 struct device_node *dp = pci_device_to_OF_node(pdev);
11019 const unsigned char *addr;
11020 int len;
11021
11022 addr = of_get_property(dp, "local-mac-address", &len);
11023 if (addr && len == 6) {
11024 memcpy(dev->dev_addr, addr, 6);
11025 memcpy(dev->perm_addr, dev->dev_addr, 6);
11026 return 0;
11027 }
11028 return -ENODEV;
11029 }
11030
11031 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11032 {
11033 struct net_device *dev = tp->dev;
11034
11035 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11036 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11037 return 0;
11038 }
11039 #endif
11040
11041 static int __devinit tg3_get_device_address(struct tg3 *tp)
11042 {
11043 struct net_device *dev = tp->dev;
11044 u32 hi, lo, mac_offset;
11045 int addr_ok = 0;
11046
11047 #ifdef CONFIG_SPARC
11048 if (!tg3_get_macaddr_sparc(tp))
11049 return 0;
11050 #endif
11051
11052 mac_offset = 0x7c;
11053 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11054 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11055 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11056 mac_offset = 0xcc;
11057 if (tg3_nvram_lock(tp))
11058 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11059 else
11060 tg3_nvram_unlock(tp);
11061 }
11062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11063 mac_offset = 0x10;
11064
11065 /* First try to get it from MAC address mailbox. */
11066 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11067 if ((hi >> 16) == 0x484b) {
11068 dev->dev_addr[0] = (hi >> 8) & 0xff;
11069 dev->dev_addr[1] = (hi >> 0) & 0xff;
11070
11071 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11072 dev->dev_addr[2] = (lo >> 24) & 0xff;
11073 dev->dev_addr[3] = (lo >> 16) & 0xff;
11074 dev->dev_addr[4] = (lo >> 8) & 0xff;
11075 dev->dev_addr[5] = (lo >> 0) & 0xff;
11076
11077 /* Some old bootcode may report a 0 MAC address in SRAM */
11078 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11079 }
11080 if (!addr_ok) {
11081 /* Next, try NVRAM. */
11082 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11083 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11084 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11085 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11086 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11087 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11088 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11089 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11090 }
11091 /* Finally just fetch it out of the MAC control regs. */
11092 else {
11093 hi = tr32(MAC_ADDR_0_HIGH);
11094 lo = tr32(MAC_ADDR_0_LOW);
11095
11096 dev->dev_addr[5] = lo & 0xff;
11097 dev->dev_addr[4] = (lo >> 8) & 0xff;
11098 dev->dev_addr[3] = (lo >> 16) & 0xff;
11099 dev->dev_addr[2] = (lo >> 24) & 0xff;
11100 dev->dev_addr[1] = hi & 0xff;
11101 dev->dev_addr[0] = (hi >> 8) & 0xff;
11102 }
11103 }
11104
11105 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11106 #ifdef CONFIG_SPARC64
11107 if (!tg3_get_default_macaddr_sparc(tp))
11108 return 0;
11109 #endif
11110 return -EINVAL;
11111 }
11112 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11113 return 0;
11114 }
11115
11116 #define BOUNDARY_SINGLE_CACHELINE 1
11117 #define BOUNDARY_MULTI_CACHELINE 2
11118
11119 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11120 {
11121 int cacheline_size;
11122 u8 byte;
11123 int goal;
11124
11125 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11126 if (byte == 0)
11127 cacheline_size = 1024;
11128 else
11129 cacheline_size = (int) byte * 4;
11130
11131 /* On 5703 and later chips, the boundary bits have no
11132 * effect.
11133 */
11134 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11135 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11136 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11137 goto out;
11138
11139 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11140 goal = BOUNDARY_MULTI_CACHELINE;
11141 #else
11142 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11143 goal = BOUNDARY_SINGLE_CACHELINE;
11144 #else
11145 goal = 0;
11146 #endif
11147 #endif
11148
11149 if (!goal)
11150 goto out;
11151
11152 /* PCI controllers on most RISC systems tend to disconnect
11153 * when a device tries to burst across a cache-line boundary.
11154 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11155 *
11156 * Unfortunately, for PCI-E there are only limited
11157 * write-side controls for this, and thus for reads
11158 * we will still get the disconnects. We'll also waste
11159 * these PCI cycles for both read and write for chips
11160 * other than 5700 and 5701 which do not implement the
11161 * boundary bits.
11162 */
11163 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11164 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11165 switch (cacheline_size) {
11166 case 16:
11167 case 32:
11168 case 64:
11169 case 128:
11170 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11171 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11172 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11173 } else {
11174 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11175 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11176 }
11177 break;
11178
11179 case 256:
11180 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11181 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11182 break;
11183
11184 default:
11185 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11186 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11187 break;
11188 };
11189 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11190 switch (cacheline_size) {
11191 case 16:
11192 case 32:
11193 case 64:
11194 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11195 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11196 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11197 break;
11198 }
11199 /* fallthrough */
11200 case 128:
11201 default:
11202 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11203 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11204 break;
11205 };
11206 } else {
11207 switch (cacheline_size) {
11208 case 16:
11209 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11210 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11211 DMA_RWCTRL_WRITE_BNDRY_16);
11212 break;
11213 }
11214 /* fallthrough */
11215 case 32:
11216 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11217 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11218 DMA_RWCTRL_WRITE_BNDRY_32);
11219 break;
11220 }
11221 /* fallthrough */
11222 case 64:
11223 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11224 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11225 DMA_RWCTRL_WRITE_BNDRY_64);
11226 break;
11227 }
11228 /* fallthrough */
11229 case 128:
11230 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11231 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11232 DMA_RWCTRL_WRITE_BNDRY_128);
11233 break;
11234 }
11235 /* fallthrough */
11236 case 256:
11237 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11238 DMA_RWCTRL_WRITE_BNDRY_256);
11239 break;
11240 case 512:
11241 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11242 DMA_RWCTRL_WRITE_BNDRY_512);
11243 break;
11244 case 1024:
11245 default:
11246 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11247 DMA_RWCTRL_WRITE_BNDRY_1024);
11248 break;
11249 };
11250 }
11251
11252 out:
11253 return val;
11254 }
11255
11256 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11257 {
11258 struct tg3_internal_buffer_desc test_desc;
11259 u32 sram_dma_descs;
11260 int i, ret;
11261
11262 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11263
11264 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11265 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11266 tw32(RDMAC_STATUS, 0);
11267 tw32(WDMAC_STATUS, 0);
11268
11269 tw32(BUFMGR_MODE, 0);
11270 tw32(FTQ_RESET, 0);
11271
11272 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11273 test_desc.addr_lo = buf_dma & 0xffffffff;
11274 test_desc.nic_mbuf = 0x00002100;
11275 test_desc.len = size;
11276
11277 /*
11278 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11279 * the *second* time the tg3 driver was getting loaded after an
11280 * initial scan.
11281 *
11282 * Broadcom tells me:
11283 * ...the DMA engine is connected to the GRC block and a DMA
11284 * reset may affect the GRC block in some unpredictable way...
11285 * The behavior of resets to individual blocks has not been tested.
11286 *
11287 * Broadcom noted the GRC reset will also reset all sub-components.
11288 */
11289 if (to_device) {
11290 test_desc.cqid_sqid = (13 << 8) | 2;
11291
11292 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11293 udelay(40);
11294 } else {
11295 test_desc.cqid_sqid = (16 << 8) | 7;
11296
11297 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11298 udelay(40);
11299 }
11300 test_desc.flags = 0x00000005;
11301
11302 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11303 u32 val;
11304
11305 val = *(((u32 *)&test_desc) + i);
11306 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11307 sram_dma_descs + (i * sizeof(u32)));
11308 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11309 }
11310 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11311
11312 if (to_device) {
11313 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11314 } else {
11315 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11316 }
11317
11318 ret = -ENODEV;
11319 for (i = 0; i < 40; i++) {
11320 u32 val;
11321
11322 if (to_device)
11323 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11324 else
11325 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11326 if ((val & 0xffff) == sram_dma_descs) {
11327 ret = 0;
11328 break;
11329 }
11330
11331 udelay(100);
11332 }
11333
11334 return ret;
11335 }
11336
11337 #define TEST_BUFFER_SIZE 0x2000
11338
11339 static int __devinit tg3_test_dma(struct tg3 *tp)
11340 {
11341 dma_addr_t buf_dma;
11342 u32 *buf, saved_dma_rwctrl;
11343 int ret;
11344
11345 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11346 if (!buf) {
11347 ret = -ENOMEM;
11348 goto out_nofree;
11349 }
11350
11351 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11352 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11353
11354 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11355
11356 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11357 /* DMA read watermark not used on PCIE */
11358 tp->dma_rwctrl |= 0x00180000;
11359 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11361 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11362 tp->dma_rwctrl |= 0x003f0000;
11363 else
11364 tp->dma_rwctrl |= 0x003f000f;
11365 } else {
11366 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11368 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11369 u32 read_water = 0x7;
11370
11371 /* If the 5704 is behind the EPB bridge, we can
11372 * do the less restrictive ONE_DMA workaround for
11373 * better performance.
11374 */
11375 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11377 tp->dma_rwctrl |= 0x8000;
11378 else if (ccval == 0x6 || ccval == 0x7)
11379 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11380
11381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11382 read_water = 4;
11383 /* Set bit 23 to enable PCIX hw bug fix */
11384 tp->dma_rwctrl |=
11385 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11386 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11387 (1 << 23);
11388 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11389 /* 5780 always in PCIX mode */
11390 tp->dma_rwctrl |= 0x00144000;
11391 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11392 /* 5714 always in PCIX mode */
11393 tp->dma_rwctrl |= 0x00148000;
11394 } else {
11395 tp->dma_rwctrl |= 0x001b000f;
11396 }
11397 }
11398
11399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11400 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11401 tp->dma_rwctrl &= 0xfffffff0;
11402
11403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11405 /* Remove this if it causes problems for some boards. */
11406 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11407
11408 /* On 5700/5701 chips, we need to set this bit.
11409 * Otherwise the chip will issue cacheline transactions
11410 * to streamable DMA memory with not all the byte
11411 * enables turned on. This is an error on several
11412 * RISC PCI controllers, in particular sparc64.
11413 *
11414 * On 5703/5704 chips, this bit has been reassigned
11415 * a different meaning. In particular, it is used
11416 * on those chips to enable a PCI-X workaround.
11417 */
11418 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11419 }
11420
11421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11422
11423 #if 0
11424 /* Unneeded, already done by tg3_get_invariants. */
11425 tg3_switch_clocks(tp);
11426 #endif
11427
11428 ret = 0;
11429 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11430 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11431 goto out;
11432
11433 /* It is best to perform DMA test with maximum write burst size
11434 * to expose the 5700/5701 write DMA bug.
11435 */
11436 saved_dma_rwctrl = tp->dma_rwctrl;
11437 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11438 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11439
11440 while (1) {
11441 u32 *p = buf, i;
11442
11443 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11444 p[i] = i;
11445
11446 /* Send the buffer to the chip. */
11447 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11448 if (ret) {
11449 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11450 break;
11451 }
11452
11453 #if 0
11454 /* validate data reached card RAM correctly. */
11455 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11456 u32 val;
11457 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11458 if (le32_to_cpu(val) != p[i]) {
11459 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11460 /* ret = -ENODEV here? */
11461 }
11462 p[i] = 0;
11463 }
11464 #endif
11465 /* Now read it back. */
11466 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11467 if (ret) {
11468 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11469
11470 break;
11471 }
11472
11473 /* Verify it. */
11474 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11475 if (p[i] == i)
11476 continue;
11477
11478 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11479 DMA_RWCTRL_WRITE_BNDRY_16) {
11480 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11481 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11482 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11483 break;
11484 } else {
11485 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11486 ret = -ENODEV;
11487 goto out;
11488 }
11489 }
11490
11491 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11492 /* Success. */
11493 ret = 0;
11494 break;
11495 }
11496 }
11497 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11498 DMA_RWCTRL_WRITE_BNDRY_16) {
11499 static struct pci_device_id dma_wait_state_chipsets[] = {
11500 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11501 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11502 { },
11503 };
11504
11505 /* DMA test passed without adjusting DMA boundary,
11506 * now look for chipsets that are known to expose the
11507 * DMA bug without failing the test.
11508 */
11509 if (pci_dev_present(dma_wait_state_chipsets)) {
11510 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11511 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11512 }
11513 else
11514 /* Safe to use the calculated DMA boundary. */
11515 tp->dma_rwctrl = saved_dma_rwctrl;
11516
11517 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11518 }
11519
11520 out:
11521 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11522 out_nofree:
11523 return ret;
11524 }
11525
11526 static void __devinit tg3_init_link_config(struct tg3 *tp)
11527 {
11528 tp->link_config.advertising =
11529 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11530 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11531 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11532 ADVERTISED_Autoneg | ADVERTISED_MII);
11533 tp->link_config.speed = SPEED_INVALID;
11534 tp->link_config.duplex = DUPLEX_INVALID;
11535 tp->link_config.autoneg = AUTONEG_ENABLE;
11536 tp->link_config.active_speed = SPEED_INVALID;
11537 tp->link_config.active_duplex = DUPLEX_INVALID;
11538 tp->link_config.phy_is_low_power = 0;
11539 tp->link_config.orig_speed = SPEED_INVALID;
11540 tp->link_config.orig_duplex = DUPLEX_INVALID;
11541 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11542 }
11543
11544 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11545 {
11546 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11547 tp->bufmgr_config.mbuf_read_dma_low_water =
11548 DEFAULT_MB_RDMA_LOW_WATER_5705;
11549 tp->bufmgr_config.mbuf_mac_rx_low_water =
11550 DEFAULT_MB_MACRX_LOW_WATER_5705;
11551 tp->bufmgr_config.mbuf_high_water =
11552 DEFAULT_MB_HIGH_WATER_5705;
11553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11554 tp->bufmgr_config.mbuf_mac_rx_low_water =
11555 DEFAULT_MB_MACRX_LOW_WATER_5906;
11556 tp->bufmgr_config.mbuf_high_water =
11557 DEFAULT_MB_HIGH_WATER_5906;
11558 }
11559
11560 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11561 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11562 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11563 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11564 tp->bufmgr_config.mbuf_high_water_jumbo =
11565 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11566 } else {
11567 tp->bufmgr_config.mbuf_read_dma_low_water =
11568 DEFAULT_MB_RDMA_LOW_WATER;
11569 tp->bufmgr_config.mbuf_mac_rx_low_water =
11570 DEFAULT_MB_MACRX_LOW_WATER;
11571 tp->bufmgr_config.mbuf_high_water =
11572 DEFAULT_MB_HIGH_WATER;
11573
11574 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11575 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11576 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11577 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11578 tp->bufmgr_config.mbuf_high_water_jumbo =
11579 DEFAULT_MB_HIGH_WATER_JUMBO;
11580 }
11581
11582 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11583 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11584 }
11585
11586 static char * __devinit tg3_phy_string(struct tg3 *tp)
11587 {
11588 switch (tp->phy_id & PHY_ID_MASK) {
11589 case PHY_ID_BCM5400: return "5400";
11590 case PHY_ID_BCM5401: return "5401";
11591 case PHY_ID_BCM5411: return "5411";
11592 case PHY_ID_BCM5701: return "5701";
11593 case PHY_ID_BCM5703: return "5703";
11594 case PHY_ID_BCM5704: return "5704";
11595 case PHY_ID_BCM5705: return "5705";
11596 case PHY_ID_BCM5750: return "5750";
11597 case PHY_ID_BCM5752: return "5752";
11598 case PHY_ID_BCM5714: return "5714";
11599 case PHY_ID_BCM5780: return "5780";
11600 case PHY_ID_BCM5755: return "5755";
11601 case PHY_ID_BCM5787: return "5787";
11602 case PHY_ID_BCM5756: return "5722/5756";
11603 case PHY_ID_BCM5906: return "5906";
11604 case PHY_ID_BCM8002: return "8002/serdes";
11605 case 0: return "serdes";
11606 default: return "unknown";
11607 };
11608 }
11609
11610 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11611 {
11612 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11613 strcpy(str, "PCI Express");
11614 return str;
11615 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11616 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11617
11618 strcpy(str, "PCIX:");
11619
11620 if ((clock_ctrl == 7) ||
11621 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11622 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11623 strcat(str, "133MHz");
11624 else if (clock_ctrl == 0)
11625 strcat(str, "33MHz");
11626 else if (clock_ctrl == 2)
11627 strcat(str, "50MHz");
11628 else if (clock_ctrl == 4)
11629 strcat(str, "66MHz");
11630 else if (clock_ctrl == 6)
11631 strcat(str, "100MHz");
11632 } else {
11633 strcpy(str, "PCI:");
11634 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11635 strcat(str, "66MHz");
11636 else
11637 strcat(str, "33MHz");
11638 }
11639 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11640 strcat(str, ":32-bit");
11641 else
11642 strcat(str, ":64-bit");
11643 return str;
11644 }
11645
11646 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11647 {
11648 struct pci_dev *peer;
11649 unsigned int func, devnr = tp->pdev->devfn & ~7;
11650
11651 for (func = 0; func < 8; func++) {
11652 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11653 if (peer && peer != tp->pdev)
11654 break;
11655 pci_dev_put(peer);
11656 }
11657 /* 5704 can be configured in single-port mode, set peer to
11658 * tp->pdev in that case.
11659 */
11660 if (!peer) {
11661 peer = tp->pdev;
11662 return peer;
11663 }
11664
11665 /*
11666 * We don't need to keep the refcount elevated; there's no way
11667 * to remove one half of this device without removing the other
11668 */
11669 pci_dev_put(peer);
11670
11671 return peer;
11672 }
11673
11674 static void __devinit tg3_init_coal(struct tg3 *tp)
11675 {
11676 struct ethtool_coalesce *ec = &tp->coal;
11677
11678 memset(ec, 0, sizeof(*ec));
11679 ec->cmd = ETHTOOL_GCOALESCE;
11680 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11681 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11682 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11683 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11684 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11685 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11686 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11687 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11688 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11689
11690 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11691 HOSTCC_MODE_CLRTICK_TXBD)) {
11692 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11693 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11694 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11695 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11696 }
11697
11698 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11699 ec->rx_coalesce_usecs_irq = 0;
11700 ec->tx_coalesce_usecs_irq = 0;
11701 ec->stats_block_coalesce_usecs = 0;
11702 }
11703 }
11704
11705 static int __devinit tg3_init_one(struct pci_dev *pdev,
11706 const struct pci_device_id *ent)
11707 {
11708 static int tg3_version_printed = 0;
11709 unsigned long tg3reg_base, tg3reg_len;
11710 struct net_device *dev;
11711 struct tg3 *tp;
11712 int i, err, pm_cap;
11713 char str[40];
11714 u64 dma_mask, persist_dma_mask;
11715
11716 if (tg3_version_printed++ == 0)
11717 printk(KERN_INFO "%s", version);
11718
11719 err = pci_enable_device(pdev);
11720 if (err) {
11721 printk(KERN_ERR PFX "Cannot enable PCI device, "
11722 "aborting.\n");
11723 return err;
11724 }
11725
11726 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11727 printk(KERN_ERR PFX "Cannot find proper PCI device "
11728 "base address, aborting.\n");
11729 err = -ENODEV;
11730 goto err_out_disable_pdev;
11731 }
11732
11733 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11734 if (err) {
11735 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11736 "aborting.\n");
11737 goto err_out_disable_pdev;
11738 }
11739
11740 pci_set_master(pdev);
11741
11742 /* Find power-management capability. */
11743 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11744 if (pm_cap == 0) {
11745 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11746 "aborting.\n");
11747 err = -EIO;
11748 goto err_out_free_res;
11749 }
11750
11751 tg3reg_base = pci_resource_start(pdev, 0);
11752 tg3reg_len = pci_resource_len(pdev, 0);
11753
11754 dev = alloc_etherdev(sizeof(*tp));
11755 if (!dev) {
11756 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11757 err = -ENOMEM;
11758 goto err_out_free_res;
11759 }
11760
11761 SET_MODULE_OWNER(dev);
11762 SET_NETDEV_DEV(dev, &pdev->dev);
11763
11764 #if TG3_VLAN_TAG_USED
11765 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11766 dev->vlan_rx_register = tg3_vlan_rx_register;
11767 #endif
11768
11769 tp = netdev_priv(dev);
11770 tp->pdev = pdev;
11771 tp->dev = dev;
11772 tp->pm_cap = pm_cap;
11773 tp->mac_mode = TG3_DEF_MAC_MODE;
11774 tp->rx_mode = TG3_DEF_RX_MODE;
11775 tp->tx_mode = TG3_DEF_TX_MODE;
11776 tp->mi_mode = MAC_MI_MODE_BASE;
11777 if (tg3_debug > 0)
11778 tp->msg_enable = tg3_debug;
11779 else
11780 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11781
11782 /* The word/byte swap controls here control register access byte
11783 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11784 * setting below.
11785 */
11786 tp->misc_host_ctrl =
11787 MISC_HOST_CTRL_MASK_PCI_INT |
11788 MISC_HOST_CTRL_WORD_SWAP |
11789 MISC_HOST_CTRL_INDIR_ACCESS |
11790 MISC_HOST_CTRL_PCISTATE_RW;
11791
11792 /* The NONFRM (non-frame) byte/word swap controls take effect
11793 * on descriptor entries, anything which isn't packet data.
11794 *
11795 * The StrongARM chips on the board (one for tx, one for rx)
11796 * are running in big-endian mode.
11797 */
11798 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11799 GRC_MODE_WSWAP_NONFRM_DATA);
11800 #ifdef __BIG_ENDIAN
11801 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11802 #endif
11803 spin_lock_init(&tp->lock);
11804 spin_lock_init(&tp->indirect_lock);
11805 INIT_WORK(&tp->reset_task, tg3_reset_task);
11806
11807 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11808 if (tp->regs == 0UL) {
11809 printk(KERN_ERR PFX "Cannot map device registers, "
11810 "aborting.\n");
11811 err = -ENOMEM;
11812 goto err_out_free_dev;
11813 }
11814
11815 tg3_init_link_config(tp);
11816
11817 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11818 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11819 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11820
11821 dev->open = tg3_open;
11822 dev->stop = tg3_close;
11823 dev->get_stats = tg3_get_stats;
11824 dev->set_multicast_list = tg3_set_rx_mode;
11825 dev->set_mac_address = tg3_set_mac_addr;
11826 dev->do_ioctl = tg3_ioctl;
11827 dev->tx_timeout = tg3_tx_timeout;
11828 dev->poll = tg3_poll;
11829 dev->ethtool_ops = &tg3_ethtool_ops;
11830 dev->weight = 64;
11831 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11832 dev->change_mtu = tg3_change_mtu;
11833 dev->irq = pdev->irq;
11834 #ifdef CONFIG_NET_POLL_CONTROLLER
11835 dev->poll_controller = tg3_poll_controller;
11836 #endif
11837
11838 err = tg3_get_invariants(tp);
11839 if (err) {
11840 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11841 "aborting.\n");
11842 goto err_out_iounmap;
11843 }
11844
11845 /* The EPB bridge inside 5714, 5715, and 5780 and any
11846 * device behind the EPB cannot support DMA addresses > 40-bit.
11847 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11848 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11849 * do DMA address check in tg3_start_xmit().
11850 */
11851 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11852 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11853 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11854 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11855 #ifdef CONFIG_HIGHMEM
11856 dma_mask = DMA_64BIT_MASK;
11857 #endif
11858 } else
11859 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11860
11861 /* Configure DMA attributes. */
11862 if (dma_mask > DMA_32BIT_MASK) {
11863 err = pci_set_dma_mask(pdev, dma_mask);
11864 if (!err) {
11865 dev->features |= NETIF_F_HIGHDMA;
11866 err = pci_set_consistent_dma_mask(pdev,
11867 persist_dma_mask);
11868 if (err < 0) {
11869 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11870 "DMA for consistent allocations\n");
11871 goto err_out_iounmap;
11872 }
11873 }
11874 }
11875 if (err || dma_mask == DMA_32BIT_MASK) {
11876 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11877 if (err) {
11878 printk(KERN_ERR PFX "No usable DMA configuration, "
11879 "aborting.\n");
11880 goto err_out_iounmap;
11881 }
11882 }
11883
11884 tg3_init_bufmgr_config(tp);
11885
11886 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11887 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11888 }
11889 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11891 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11893 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11894 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11895 } else {
11896 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11897 }
11898
11899 /* TSO is on by default on chips that support hardware TSO.
11900 * Firmware TSO on older chips gives lower performance, so it
11901 * is off by default, but can be enabled using ethtool.
11902 */
11903 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11904 dev->features |= NETIF_F_TSO;
11905 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11906 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11907 dev->features |= NETIF_F_TSO6;
11908 }
11909
11910
11911 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11912 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11914 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11915 tp->rx_pending = 63;
11916 }
11917
11918 err = tg3_get_device_address(tp);
11919 if (err) {
11920 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11921 "aborting.\n");
11922 goto err_out_iounmap;
11923 }
11924
11925 /*
11926 * Reset chip in case UNDI or EFI driver did not shutdown
11927 * DMA self test will enable WDMAC and we'll see (spurious)
11928 * pending DMA on the PCI bus at that point.
11929 */
11930 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11931 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11932 pci_save_state(tp->pdev);
11933 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11934 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11935 }
11936
11937 err = tg3_test_dma(tp);
11938 if (err) {
11939 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11940 goto err_out_iounmap;
11941 }
11942
11943 /* Tigon3 can do ipv4 only... and some chips have buggy
11944 * checksumming.
11945 */
11946 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11949 dev->features |= NETIF_F_HW_CSUM;
11950 else
11951 dev->features |= NETIF_F_IP_CSUM;
11952 dev->features |= NETIF_F_SG;
11953 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11954 } else
11955 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11956
11957 /* flow control autonegotiation is default behavior */
11958 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11959
11960 tg3_init_coal(tp);
11961
11962 /* Now that we have fully setup the chip, save away a snapshot
11963 * of the PCI config space. We need to restore this after
11964 * GRC_MISC_CFG core clock resets and some resume events.
11965 */
11966 pci_save_state(tp->pdev);
11967
11968 pci_set_drvdata(pdev, dev);
11969
11970 err = register_netdev(dev);
11971 if (err) {
11972 printk(KERN_ERR PFX "Cannot register net device, "
11973 "aborting.\n");
11974 goto err_out_iounmap;
11975 }
11976
11977 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11978 dev->name,
11979 tp->board_part_number,
11980 tp->pci_chip_rev_id,
11981 tg3_phy_string(tp),
11982 tg3_bus_string(tp, str),
11983 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11984 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11985 "10/100/1000Base-T")));
11986
11987 for (i = 0; i < 6; i++)
11988 printk("%2.2x%c", dev->dev_addr[i],
11989 i == 5 ? '\n' : ':');
11990
11991 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11992 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11993 dev->name,
11994 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11995 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11996 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11997 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11998 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11999 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12000 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12001 dev->name, tp->dma_rwctrl,
12002 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12003 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12004
12005 return 0;
12006
12007 err_out_iounmap:
12008 if (tp->regs) {
12009 iounmap(tp->regs);
12010 tp->regs = NULL;
12011 }
12012
12013 err_out_free_dev:
12014 free_netdev(dev);
12015
12016 err_out_free_res:
12017 pci_release_regions(pdev);
12018
12019 err_out_disable_pdev:
12020 pci_disable_device(pdev);
12021 pci_set_drvdata(pdev, NULL);
12022 return err;
12023 }
12024
12025 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12026 {
12027 struct net_device *dev = pci_get_drvdata(pdev);
12028
12029 if (dev) {
12030 struct tg3 *tp = netdev_priv(dev);
12031
12032 flush_scheduled_work();
12033 unregister_netdev(dev);
12034 if (tp->regs) {
12035 iounmap(tp->regs);
12036 tp->regs = NULL;
12037 }
12038 free_netdev(dev);
12039 pci_release_regions(pdev);
12040 pci_disable_device(pdev);
12041 pci_set_drvdata(pdev, NULL);
12042 }
12043 }
12044
12045 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12046 {
12047 struct net_device *dev = pci_get_drvdata(pdev);
12048 struct tg3 *tp = netdev_priv(dev);
12049 int err;
12050
12051 if (!netif_running(dev))
12052 return 0;
12053
12054 flush_scheduled_work();
12055 tg3_netif_stop(tp);
12056
12057 del_timer_sync(&tp->timer);
12058
12059 tg3_full_lock(tp, 1);
12060 tg3_disable_ints(tp);
12061 tg3_full_unlock(tp);
12062
12063 netif_device_detach(dev);
12064
12065 tg3_full_lock(tp, 0);
12066 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12067 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12068 tg3_full_unlock(tp);
12069
12070 /* Save MSI address and data for resume. */
12071 pci_save_state(pdev);
12072
12073 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12074 if (err) {
12075 tg3_full_lock(tp, 0);
12076
12077 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12078 if (tg3_restart_hw(tp, 1))
12079 goto out;
12080
12081 tp->timer.expires = jiffies + tp->timer_offset;
12082 add_timer(&tp->timer);
12083
12084 netif_device_attach(dev);
12085 tg3_netif_start(tp);
12086
12087 out:
12088 tg3_full_unlock(tp);
12089 }
12090
12091 return err;
12092 }
12093
12094 static int tg3_resume(struct pci_dev *pdev)
12095 {
12096 struct net_device *dev = pci_get_drvdata(pdev);
12097 struct tg3 *tp = netdev_priv(dev);
12098 int err;
12099
12100 if (!netif_running(dev))
12101 return 0;
12102
12103 pci_restore_state(tp->pdev);
12104
12105 err = tg3_set_power_state(tp, PCI_D0);
12106 if (err)
12107 return err;
12108
12109 netif_device_attach(dev);
12110
12111 tg3_full_lock(tp, 0);
12112
12113 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12114 err = tg3_restart_hw(tp, 1);
12115 if (err)
12116 goto out;
12117
12118 tp->timer.expires = jiffies + tp->timer_offset;
12119 add_timer(&tp->timer);
12120
12121 tg3_netif_start(tp);
12122
12123 out:
12124 tg3_full_unlock(tp);
12125
12126 return err;
12127 }
12128
12129 static struct pci_driver tg3_driver = {
12130 .name = DRV_MODULE_NAME,
12131 .id_table = tg3_pci_tbl,
12132 .probe = tg3_init_one,
12133 .remove = __devexit_p(tg3_remove_one),
12134 .suspend = tg3_suspend,
12135 .resume = tg3_resume
12136 };
12137
12138 static int __init tg3_init(void)
12139 {
12140 return pci_register_driver(&tg3_driver);
12141 }
12142
12143 static void __exit tg3_cleanup(void)
12144 {
12145 pci_unregister_driver(&tg3_driver);
12146 }
12147
12148 module_init(tg3_init);
12149 module_exit(tg3_cleanup);
Tomato firmware and modifications.