release/src-rt-6.x/linux/linux-2.6/drivers/net/spider_net.h

   1 /*
   2  * Network device driver for Cell Processor-Based Blade and Celleb platform
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  * (C) Copyright 2006 TOSHIBA CORPORATION
   6  *
   7  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
   8  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2, or (at your option)
  13  * any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #ifndef _SPIDER_NET_H
  26 #define _SPIDER_NET_H
  27
  28 #define VERSION "2.0 B"
  29
  30 #include "sungem_phy.h"
  31
  32 extern int spider_net_stop(struct net_device *netdev);
  33 extern int spider_net_open(struct net_device *netdev);
  34
  35 extern const struct ethtool_ops spider_net_ethtool_ops;
  36
  37 extern char spider_net_driver_name[];
  38
  39 #define SPIDER_NET_MAX_FRAME                    2312
  40 #define SPIDER_NET_MAX_MTU                      2294
  41 #define SPIDER_NET_MIN_MTU                      64
  42
  43 #define SPIDER_NET_RXBUF_ALIGN                  128
  44
  45 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT       256
  46 #define SPIDER_NET_RX_DESCRIPTORS_MIN           16
  47 #define SPIDER_NET_RX_DESCRIPTORS_MAX           512
  48
  49 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT       256
  50 #define SPIDER_NET_TX_DESCRIPTORS_MIN           16
  51 #define SPIDER_NET_TX_DESCRIPTORS_MAX           512
  52
  53 #define SPIDER_NET_TX_TIMER                     (HZ/5)
  54 #define SPIDER_NET_ANEG_TIMER                   (HZ)
  55 #define SPIDER_NET_ANEG_TIMEOUT                 2
  56
  57 #define SPIDER_NET_RX_CSUM_DEFAULT              1
  58
  59 #define SPIDER_NET_WATCHDOG_TIMEOUT             50*HZ
  60 #define SPIDER_NET_NAPI_WEIGHT                  64
  61
  62 #define SPIDER_NET_FIRMWARE_SEQS        6
  63 #define SPIDER_NET_FIRMWARE_SEQWORDS    1024
  64 #define SPIDER_NET_FIRMWARE_LEN         (SPIDER_NET_FIRMWARE_SEQS * \
  65                                          SPIDER_NET_FIRMWARE_SEQWORDS * \
  66                                          sizeof(u32))
  67 #define SPIDER_NET_FIRMWARE_NAME        "spider_fw.bin"
  68
  69 /** spider_net SMMIO registers */
  70 #define SPIDER_NET_GHIINT0STS           0x00000000
  71 #define SPIDER_NET_GHIINT1STS           0x00000004
  72 #define SPIDER_NET_GHIINT2STS           0x00000008
  73 #define SPIDER_NET_GHIINT0MSK           0x00000010
  74 #define SPIDER_NET_GHIINT1MSK           0x00000014
  75 #define SPIDER_NET_GHIINT2MSK           0x00000018
  76
  77 #define SPIDER_NET_GRESUMINTNUM         0x00000020
  78 #define SPIDER_NET_GREINTNUM            0x00000024
  79
  80 #define SPIDER_NET_GFFRMNUM             0x00000028
  81 #define SPIDER_NET_GFAFRMNUM            0x0000002c
  82 #define SPIDER_NET_GFBFRMNUM            0x00000030
  83 #define SPIDER_NET_GFCFRMNUM            0x00000034
  84 #define SPIDER_NET_GFDFRMNUM            0x00000038
  85
  86 /* clear them (don't use it) */
  87 #define SPIDER_NET_GFREECNNUM           0x0000003c
  88 #define SPIDER_NET_GONETIMENUM          0x00000040
  89
  90 #define SPIDER_NET_GTOUTFRMNUM          0x00000044
  91
  92 #define SPIDER_NET_GTXMDSET             0x00000050
  93 #define SPIDER_NET_GPCCTRL              0x00000054
  94 #define SPIDER_NET_GRXMDSET             0x00000058
  95 #define SPIDER_NET_GIPSECINIT           0x0000005c
  96 #define SPIDER_NET_GFTRESTRT            0x00000060
  97 #define SPIDER_NET_GRXDMAEN             0x00000064
  98 #define SPIDER_NET_GMRWOLCTRL           0x00000068
  99 #define SPIDER_NET_GPCWOPCMD            0x0000006c
 100 #define SPIDER_NET_GPCROPCMD            0x00000070
 101 #define SPIDER_NET_GTTFRMCNT            0x00000078
 102 #define SPIDER_NET_GTESTMD              0x0000007c
 103
 104 #define SPIDER_NET_GSINIT               0x00000080
 105 #define SPIDER_NET_GSnPRGADR            0x00000084
 106 #define SPIDER_NET_GSnPRGDAT            0x00000088
 107
 108 #define SPIDER_NET_GMACOPEMD            0x00000100
 109 #define SPIDER_NET_GMACLENLMT           0x00000108
 110 #define SPIDER_NET_GMACST               0x00000110
 111 #define SPIDER_NET_GMACINTEN            0x00000118
 112 #define SPIDER_NET_GMACPHYCTRL          0x00000120
 113
 114 #define SPIDER_NET_GMACAPAUSE           0x00000154
 115 #define SPIDER_NET_GMACTXPAUSE          0x00000164
 116
 117 #define SPIDER_NET_GMACMODE             0x000001b0
 118 #define SPIDER_NET_GMACBSTLMT           0x000001b4
 119
 120 #define SPIDER_NET_GMACUNIMACU          0x000001c0
 121 #define SPIDER_NET_GMACUNIMACL          0x000001c8
 122
 123 #define SPIDER_NET_GMRMHFILnR           0x00000400
 124 #define SPIDER_NET_MULTICAST_HASHES     256
 125
 126 #define SPIDER_NET_GMRUAFILnR           0x00000500
 127 #define SPIDER_NET_GMRUA0FIL15R         0x00000578
 128
 129 #define SPIDER_NET_GTTQMSK              0x00000934
 130
 131 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 132  * 0x00000b.. for DMA controller B, etc. */
 133 #define SPIDER_NET_GDADCHA              0x00000a00
 134 #define SPIDER_NET_GDADMACCNTR          0x00000a04
 135 #define SPIDER_NET_GDACTDPA             0x00000a08
 136 #define SPIDER_NET_GDACTDCNT            0x00000a0c
 137 #define SPIDER_NET_GDACDBADDR           0x00000a20
 138 #define SPIDER_NET_GDACDBSIZE           0x00000a24
 139 #define SPIDER_NET_GDACNEXTDA           0x00000a28
 140 #define SPIDER_NET_GDACCOMST            0x00000a2c
 141 #define SPIDER_NET_GDAWBCOMST           0x00000a30
 142 #define SPIDER_NET_GDAWBRSIZE           0x00000a34
 143 #define SPIDER_NET_GDAWBVSIZE           0x00000a38
 144 #define SPIDER_NET_GDAWBTRST            0x00000a3c
 145 #define SPIDER_NET_GDAWBTRERR           0x00000a40
 146
 147 /* TX DMA controller registers */
 148 #define SPIDER_NET_GDTDCHA              0x00000e00
 149 #define SPIDER_NET_GDTDMACCNTR          0x00000e04
 150 #define SPIDER_NET_GDTCDPA              0x00000e08
 151 #define SPIDER_NET_GDTDMASEL            0x00000e14
 152
 153 #define SPIDER_NET_ECMODE               0x00000f00
 154 /* clock and reset control register */
 155 #define SPIDER_NET_CKRCTRL              0x00000ff0
 156
 157 /** SCONFIG registers */
 158 #define SPIDER_NET_SCONFIG_IOACTE       0x00002810
 159
 160 /** interrupt mask registers */
 161 #define SPIDER_NET_INT0_MASK_VALUE      0x3f7fe2c7
 162 #define SPIDER_NET_INT1_MASK_VALUE      0xffff7ff7
 163 /* no MAC aborts -> auto retransmission */
 164 #define SPIDER_NET_INT2_MASK_VALUE      0xffef7ff1
 165
 166 /* we rely on flagged descriptor interrupts */
 167 #define SPIDER_NET_FRAMENUM_VALUE       0x00000000
 168 /* set this first, then the FRAMENUM_VALUE */
 169 #define SPIDER_NET_GFXFRAMES_VALUE      0x00000000
 170
 171 #define SPIDER_NET_STOP_SEQ_VALUE       0x00000000
 172 #define SPIDER_NET_RUN_SEQ_VALUE        0x0000007e
 173
 174 #define SPIDER_NET_PHY_CTRL_VALUE       0x00040040
 175 /* #define SPIDER_NET_PHY_CTRL_VALUE    0x01070080*/
 176 #define SPIDER_NET_RXMODE_VALUE         0x00000011
 177 /* auto retransmission in case of MAC aborts */
 178 #define SPIDER_NET_TXMODE_VALUE         0x00010000
 179 #define SPIDER_NET_RESTART_VALUE        0x00000000
 180 #define SPIDER_NET_WOL_VALUE            0x00001111
 181 #if 0
 182 #define SPIDER_NET_WOL_VALUE            0x00000000
 183 #endif
 184 #define SPIDER_NET_IPSECINIT_VALUE      0x6f716f71
 185
 186 /* pause frames: automatic, no upper retransmission count */
 187 /* outside loopback mode: ETOMOD signal dont matter, not connected */
 188 /* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
 189 #define SPIDER_NET_OPMODE_VALUE         0x00000067
 190 /*#define SPIDER_NET_OPMODE_VALUE               0x001b0062*/
 191 #define SPIDER_NET_LENLMT_VALUE         0x00000908
 192
 193 #define SPIDER_NET_MACAPAUSE_VALUE      0x00000800 /* about 1 ms */
 194 #define SPIDER_NET_TXPAUSE_VALUE        0x00000000
 195
 196 #define SPIDER_NET_MACMODE_VALUE        0x00000001
 197 #define SPIDER_NET_BURSTLMT_VALUE       0x00000200 /* about 16 us */
 198
 199 /* DMAC control register GDMACCNTR
 200  *
 201  * 1(0)                         enable r/tx dma
 202  *  0000000                             fixed to 0
 203  *
 204  *         000000                       fixed to 0
 205  *               0(1)                   en/disable descr writeback on force end
 206  *                0(1)                  force end
 207  *
 208  *                 000000               fixed to 0
 209  *                       00             burst alignment: 128 bytes
 210  *                       11             burst alignment: 1024 bytes
 211  *
 212  *                         00000        fixed to 0
 213  *                              0       descr writeback size 32 bytes
 214  *                               0(1)   descr chain end interrupt enable
 215  *                                0(1)  descr status writeback enable */
 216
 217 /* to set RX_DMA_EN */
 218 #define SPIDER_NET_DMA_RX_VALUE         0x80000000
 219 #define SPIDER_NET_DMA_RX_FEND_VALUE    0x00030003
 220 /* to set TX_DMA_EN */
 221 #define SPIDER_NET_TX_DMA_EN           0x80000000
 222 #define SPIDER_NET_GDTBSTA             0x00000300
 223 #define SPIDER_NET_GDTDCEIDIS          0x00000002
 224 #define SPIDER_NET_DMA_TX_VALUE        SPIDER_NET_TX_DMA_EN | \
 225                                        SPIDER_NET_GDTDCEIDIS | \
 226                                        SPIDER_NET_GDTBSTA
 227
 228 #define SPIDER_NET_DMA_TX_FEND_VALUE    0x00030003
 229
 230 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
 231 #define SPIDER_NET_UA_DESCR_VALUE       0x00080000
 232 #define SPIDER_NET_PROMISC_VALUE        0x00080000
 233 #define SPIDER_NET_NONPROMISC_VALUE     0x00000000
 234
 235 #define SPIDER_NET_DMASEL_VALUE         0x00000001
 236
 237 #define SPIDER_NET_ECMODE_VALUE         0x00000000
 238
 239 #define SPIDER_NET_CKRCTRL_RUN_VALUE    0x1fff010f
 240 #define SPIDER_NET_CKRCTRL_STOP_VALUE   0x0000010f
 241
 242 #define SPIDER_NET_SBIMSTATE_VALUE      0x00000000
 243 #define SPIDER_NET_SBTMSTATE_VALUE      0x00000000
 244
 245 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 246  * with 1 << SPIDER_NET_... */
 247 enum spider_net_int0_status {
 248         SPIDER_NET_GPHYINT = 0,
 249         SPIDER_NET_GMAC2INT,
 250         SPIDER_NET_GMAC1INT,
 251         SPIDER_NET_GIPSINT,
 252         SPIDER_NET_GFIFOINT,
 253         SPIDER_NET_GDMACINT,
 254         SPIDER_NET_GSYSINT,
 255         SPIDER_NET_GPWOPCMPINT,
 256         SPIDER_NET_GPROPCMPINT,
 257         SPIDER_NET_GPWFFINT,
 258         SPIDER_NET_GRMDADRINT,
 259         SPIDER_NET_GRMARPINT,
 260         SPIDER_NET_GRMMPINT,
 261         SPIDER_NET_GDTDEN0INT,
 262         SPIDER_NET_GDDDEN0INT,
 263         SPIDER_NET_GDCDEN0INT,
 264         SPIDER_NET_GDBDEN0INT,
 265         SPIDER_NET_GDADEN0INT,
 266         SPIDER_NET_GDTFDCINT,
 267         SPIDER_NET_GDDFDCINT,
 268         SPIDER_NET_GDCFDCINT,
 269         SPIDER_NET_GDBFDCINT,
 270         SPIDER_NET_GDAFDCINT,
 271         SPIDER_NET_GTTEDINT,
 272         SPIDER_NET_GDTDCEINT,
 273         SPIDER_NET_GRFDNMINT,
 274         SPIDER_NET_GRFCNMINT,
 275         SPIDER_NET_GRFBNMINT,
 276         SPIDER_NET_GRFANMINT,
 277         SPIDER_NET_GRFNMINT,
 278         SPIDER_NET_G1TMCNTINT,
 279         SPIDER_NET_GFREECNTINT
 280 };
 281 /* GHIINT1STS bits */
 282 enum spider_net_int1_status {
 283         SPIDER_NET_GTMFLLINT = 0,
 284         SPIDER_NET_GRMFLLINT,
 285         SPIDER_NET_GTMSHTINT,
 286         SPIDER_NET_GDTINVDINT,
 287         SPIDER_NET_GRFDFLLINT,
 288         SPIDER_NET_GDDDCEINT,
 289         SPIDER_NET_GDDINVDINT,
 290         SPIDER_NET_GRFCFLLINT,
 291         SPIDER_NET_GDCDCEINT,
 292         SPIDER_NET_GDCINVDINT,
 293         SPIDER_NET_GRFBFLLINT,
 294         SPIDER_NET_GDBDCEINT,
 295         SPIDER_NET_GDBINVDINT,
 296         SPIDER_NET_GRFAFLLINT,
 297         SPIDER_NET_GDADCEINT,
 298         SPIDER_NET_GDAINVDINT,
 299         SPIDER_NET_GDTRSERINT,
 300         SPIDER_NET_GDDRSERINT,
 301         SPIDER_NET_GDCRSERINT,
 302         SPIDER_NET_GDBRSERINT,
 303         SPIDER_NET_GDARSERINT,
 304         SPIDER_NET_GDSERINT,
 305         SPIDER_NET_GDTPTERINT,
 306         SPIDER_NET_GDDPTERINT,
 307         SPIDER_NET_GDCPTERINT,
 308         SPIDER_NET_GDBPTERINT,
 309         SPIDER_NET_GDAPTERINT
 310 };
 311 /* GHIINT2STS bits */
 312 enum spider_net_int2_status {
 313         SPIDER_NET_GPROPERINT = 0,
 314         SPIDER_NET_GMCTCRSNGINT,
 315         SPIDER_NET_GMCTLCOLINT,
 316         SPIDER_NET_GMCTTMOTINT,
 317         SPIDER_NET_GMCRCAERINT,
 318         SPIDER_NET_GMCRCALERINT,
 319         SPIDER_NET_GMCRALNERINT,
 320         SPIDER_NET_GMCROVRINT,
 321         SPIDER_NET_GMCRRNTINT,
 322         SPIDER_NET_GMCRRXERINT,
 323         SPIDER_NET_GTITCSERINT,
 324         SPIDER_NET_GTIFMTERINT,
 325         SPIDER_NET_GTIPKTRVKINT,
 326         SPIDER_NET_GTISPINGINT,
 327         SPIDER_NET_GTISADNGINT,
 328         SPIDER_NET_GTISPDNGINT,
 329         SPIDER_NET_GRIFMTERINT,
 330         SPIDER_NET_GRIPKTRVKINT,
 331         SPIDER_NET_GRISPINGINT,
 332         SPIDER_NET_GRISADNGINT,
 333         SPIDER_NET_GRISPDNGINT
 334 };
 335
 336 #define SPIDER_NET_TXINT        (1 << SPIDER_NET_GDTFDCINT)
 337
 338 /* We rely on flagged descriptor interrupts */
 339 #define SPIDER_NET_RXINT        ( (1 << SPIDER_NET_GDAFDCINT) )
 340
 341 #define SPIDER_NET_LINKINT      ( 1 << SPIDER_NET_GMAC2INT )
 342
 343 #define SPIDER_NET_ERRINT       ( 0xffffffff & \
 344                                   (~SPIDER_NET_TXINT) & \
 345                                   (~SPIDER_NET_RXINT) & \
 346                                   (~SPIDER_NET_LINKINT) )
 347
 348 #define SPIDER_NET_GPREXEC                      0x80000000
 349 #define SPIDER_NET_GPRDAT_MASK                  0x0000ffff
 350
 351 #define SPIDER_NET_DMAC_NOINTR_COMPLETE         0x00800000
 352 #define SPIDER_NET_DMAC_NOCS                    0x00040000
 353 #define SPIDER_NET_DMAC_TCP                     0x00020000
 354 #define SPIDER_NET_DMAC_UDP                     0x00030000
 355 #define SPIDER_NET_TXDCEST                      0x08000000
 356
 357 #define SPIDER_NET_DESCR_IND_PROC_MASK          0xF0000000
 358 #define SPIDER_NET_DESCR_COMPLETE               0x00000000 /* used in rx and tx */
 359 #define SPIDER_NET_DESCR_RESPONSE_ERROR         0x10000000 /* used in rx and tx */
 360 #define SPIDER_NET_DESCR_PROTECTION_ERROR       0x20000000 /* used in rx and tx */
 361 #define SPIDER_NET_DESCR_FRAME_END              0x40000000 /* used in rx */
 362 #define SPIDER_NET_DESCR_FORCE_END              0x50000000 /* used in rx and tx */
 363 #define SPIDER_NET_DESCR_CARDOWNED              0xA0000000 /* used in rx and tx */
 364 #define SPIDER_NET_DESCR_NOT_IN_USE             0xF0000000
 365 #define SPIDER_NET_DESCR_TXDESFLG               0x00800000
 366
 367 /* Descriptor, as defined by the hardware */
 368 struct spider_net_hw_descr {
 369         u32 buf_addr;
 370         u32 buf_size;
 371         u32 next_descr_addr;
 372         u32 dmac_cmd_status;
 373         u32 result_size;
 374         u32 valid_size; /* all zeroes for tx */
 375         u32 data_status;
 376         u32 data_error; /* all zeroes for tx */
 377 } __attribute__((aligned(32)));
 378
 379 struct spider_net_descr {
 380         struct spider_net_hw_descr *hwdescr;
 381         struct sk_buff *skb;
 382         u32 bus_addr;
 383         struct spider_net_descr *next;
 384         struct spider_net_descr *prev;
 385 };
 386
 387 struct spider_net_descr_chain {
 388         spinlock_t lock;
 389         struct spider_net_descr *head;
 390         struct spider_net_descr *tail;
 391         struct spider_net_descr *ring;
 392         int num_desc;
 393         struct spider_net_hw_descr *hwring;
 394         dma_addr_t dma_addr;
 395 };
 396
 397 /* descriptor data_status bits */
 398 #define SPIDER_NET_RX_IPCHK             29
 399 #define SPIDER_NET_RX_TCPCHK            28
 400 #define SPIDER_NET_VLAN_PACKET          21
 401 #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
 402                                           (1 << SPIDER_NET_RX_TCPCHK) )
 403
 404 /* descriptor data_error bits */
 405 #define SPIDER_NET_RX_IPCHKERR          27
 406 #define SPIDER_NET_RX_RXTCPCHKERR       28
 407
 408 #define SPIDER_NET_DATA_ERR_CKSUM_MASK  (1 << SPIDER_NET_RX_IPCHKERR)
 409
 410 /* the cases we don't pass the packet to the stack.
 411  * 701b8000 would be correct, but every packets gets that flag */
 412 #define SPIDER_NET_DESTROY_RX_FLAGS     0x700b8000
 413
 414 /* this will be bigger some time */
 415 struct spider_net_options {
 416         int rx_csum; /* for rx: if 0 ip_summed=NONE,
 417                         if 1 and hw has verified, ip_summed=UNNECESSARY */
 418 };
 419
 420 #define SPIDER_NET_DEFAULT_MSG          ( NETIF_MSG_DRV | \
 421                                           NETIF_MSG_PROBE | \
 422                                           NETIF_MSG_LINK | \
 423                                           NETIF_MSG_TIMER | \
 424                                           NETIF_MSG_IFDOWN | \
 425                                           NETIF_MSG_IFUP | \
 426                                           NETIF_MSG_RX_ERR | \
 427                                           NETIF_MSG_TX_ERR | \
 428                                           NETIF_MSG_TX_QUEUED | \
 429                                           NETIF_MSG_INTR | \
 430                                           NETIF_MSG_TX_DONE | \
 431                                           NETIF_MSG_RX_STATUS | \
 432                                           NETIF_MSG_PKTDATA | \
 433                                           NETIF_MSG_HW | \
 434                                           NETIF_MSG_WOL )
 435
 436 struct spider_net_extra_stats {
 437         unsigned long rx_desc_error;
 438         unsigned long tx_timeouts;
 439         unsigned long alloc_rx_skb_error;
 440         unsigned long rx_iommu_map_error;
 441         unsigned long tx_iommu_map_error;
 442         unsigned long rx_desc_unk_state;
 443 };
 444
 445 struct spider_net_card {
 446         struct net_device *netdev;
 447         struct pci_dev *pdev;
 448         struct mii_phy phy;
 449
 450         int medium;
 451
 452         void __iomem *regs;
 453
 454         struct spider_net_descr_chain tx_chain;
 455         struct spider_net_descr_chain rx_chain;
 456         struct spider_net_descr *low_watermark;
 457
 458         int aneg_count;
 459         struct timer_list aneg_timer;
 460         struct timer_list tx_timer;
 461         struct work_struct tx_timeout_task;
 462         atomic_t tx_timeout_task_counter;
 463         wait_queue_head_t waitq;
 464         int num_rx_ints;
 465         int ignore_rx_ramfull;
 466
 467         /* for ethtool */
 468         int msg_enable;
 469         struct net_device_stats netdev_stats;
 470         struct spider_net_extra_stats spider_stats;
 471         struct spider_net_options options;
 472
 473         /* Must be last item in struct */
 474         struct spider_net_descr darray[0];
 475 };
 476
 477 #define pr_err(fmt,arg...) \
 478         printk(KERN_ERR fmt ,##arg)
 479
 480 #endif