2 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/dma-mapping.h>
38 #include <linux/mlx4/cmd.h>
44 MLX4_NUM_ASYNC_EQE
= 0x100,
45 MLX4_NUM_SPARE_EQE
= 0x80,
46 MLX4_EQ_ENTRY_SIZE
= 0x20
50 * Must be packed because start is 64 bits but only aligned to 32 bits.
52 struct mlx4_eq_context
{
66 __be32 mtt_base_addr_l
;
68 __be32 consumer_index
;
69 __be32 producer_index
;
73 #define MLX4_EQ_STATUS_OK ( 0 << 28)
74 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
75 #define MLX4_EQ_OWNER_SW ( 0 << 24)
76 #define MLX4_EQ_OWNER_HW ( 1 << 24)
77 #define MLX4_EQ_FLAG_EC ( 1 << 18)
78 #define MLX4_EQ_FLAG_OI ( 1 << 17)
79 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
80 #define MLX4_EQ_STATE_FIRED (10 << 8)
81 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
83 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
84 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
85 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
86 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
87 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
88 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
89 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
90 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
91 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
93 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
94 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
95 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
96 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
97 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
98 (1ull << MLX4_EVENT_TYPE_CMD))
99 #define MLX4_CATAS_EVENT_MASK (1ull << MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR)
110 } __attribute__((packed
)) comp
;
118 } __attribute__((packed
)) cmd
;
121 } __attribute__((packed
)) qp
;
124 } __attribute__((packed
)) srq
;
130 } __attribute__((packed
)) cq_err
;
134 } __attribute__((packed
)) port_change
;
138 } __attribute__((packed
));
140 static void eq_set_ci(struct mlx4_eq
*eq
, int req_not
)
142 __raw_writel((__force u32
) cpu_to_be32((eq
->cons_index
& 0xffffff) |
145 /* We still want ordering, just not swabbing, so add a barrier */
149 static struct mlx4_eqe
*get_eqe(struct mlx4_eq
*eq
, u32 entry
)
151 unsigned long off
= (entry
& (eq
->nent
- 1)) * MLX4_EQ_ENTRY_SIZE
;
152 return eq
->page_list
[off
/ PAGE_SIZE
].buf
+ off
% PAGE_SIZE
;
155 static struct mlx4_eqe
*next_eqe_sw(struct mlx4_eq
*eq
)
157 struct mlx4_eqe
*eqe
= get_eqe(eq
, eq
->cons_index
);
158 return !!(eqe
->owner
& 0x80) ^ !!(eq
->cons_index
& eq
->nent
) ? NULL
: eqe
;
161 static int mlx4_eq_int(struct mlx4_dev
*dev
, struct mlx4_eq
*eq
)
163 struct mlx4_eqe
*eqe
;
168 while ((eqe
= next_eqe_sw(eq
))) {
170 * Make sure we read EQ entry contents after we've
171 * checked the ownership bit.
176 case MLX4_EVENT_TYPE_COMP
:
177 cqn
= be32_to_cpu(eqe
->event
.comp
.cqn
) & 0xffffff;
178 mlx4_cq_completion(dev
, cqn
);
181 case MLX4_EVENT_TYPE_PATH_MIG
:
182 case MLX4_EVENT_TYPE_COMM_EST
:
183 case MLX4_EVENT_TYPE_SQ_DRAINED
:
184 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
:
185 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR
:
186 case MLX4_EVENT_TYPE_PATH_MIG_FAILED
:
187 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
188 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
:
189 mlx4_qp_event(dev
, be32_to_cpu(eqe
->event
.qp
.qpn
) & 0xffffff,
193 case MLX4_EVENT_TYPE_SRQ_LIMIT
:
194 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
:
195 mlx4_srq_event(dev
, be32_to_cpu(eqe
->event
.srq
.srqn
) & 0xffffff,
199 case MLX4_EVENT_TYPE_CMD
:
201 be16_to_cpu(eqe
->event
.cmd
.token
),
202 eqe
->event
.cmd
.status
,
203 be64_to_cpu(eqe
->event
.cmd
.out_param
));
206 case MLX4_EVENT_TYPE_PORT_CHANGE
:
207 mlx4_dispatch_event(dev
, eqe
->type
, eqe
->subtype
,
208 be32_to_cpu(eqe
->event
.port_change
.port
) >> 28);
211 case MLX4_EVENT_TYPE_CQ_ERROR
:
212 mlx4_warn(dev
, "CQ %s on CQN %06x\n",
213 eqe
->event
.cq_err
.syndrome
== 1 ?
214 "overrun" : "access violation",
215 be32_to_cpu(eqe
->event
.cq_err
.cqn
) & 0xffffff);
216 mlx4_cq_event(dev
, be32_to_cpu(eqe
->event
.cq_err
.cqn
),
220 case MLX4_EVENT_TYPE_EQ_OVERFLOW
:
221 mlx4_warn(dev
, "EQ overrun on EQN %d\n", eq
->eqn
);
224 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR
:
225 case MLX4_EVENT_TYPE_ECC_DETECT
:
227 mlx4_warn(dev
, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
228 eqe
->type
, eqe
->subtype
, eq
->eqn
, eq
->cons_index
);
237 * The HCA will think the queue has overflowed if we
238 * don't tell it we've been processing events. We
239 * create our EQs with MLX4_NUM_SPARE_EQE extra
240 * entries, so we must update our consumer index at
243 if (unlikely(set_ci
>= MLX4_NUM_SPARE_EQE
)) {
245 * Conditional on hca_type is OK here because
246 * this is a rare case, not the fast path.
258 static irqreturn_t
mlx4_interrupt(int irq
, void *dev_ptr
)
260 struct mlx4_dev
*dev
= dev_ptr
;
261 struct mlx4_priv
*priv
= mlx4_priv(dev
);
265 writel(priv
->eq_table
.clr_mask
, priv
->eq_table
.clr_int
);
267 for (i
= 0; i
< MLX4_EQ_CATAS
; ++i
)
268 work
|= mlx4_eq_int(dev
, &priv
->eq_table
.eq
[i
]);
270 return IRQ_RETVAL(work
);
273 static irqreturn_t
mlx4_msi_x_interrupt(int irq
, void *eq_ptr
)
275 struct mlx4_eq
*eq
= eq_ptr
;
276 struct mlx4_dev
*dev
= eq
->dev
;
278 mlx4_eq_int(dev
, eq
);
280 /* MSI-X vectors always belong to us */
284 static irqreturn_t
mlx4_catas_interrupt(int irq
, void *dev_ptr
)
286 mlx4_handle_catas_err(dev_ptr
);
288 /* MSI-X vectors always belong to us */
292 static int mlx4_MAP_EQ(struct mlx4_dev
*dev
, u64 event_mask
, int unmap
,
295 return mlx4_cmd(dev
, event_mask
, (unmap
<< 31) | eq_num
,
296 0, MLX4_CMD_MAP_EQ
, MLX4_CMD_TIME_CLASS_B
);
299 static int mlx4_SW2HW_EQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
302 return mlx4_cmd(dev
, mailbox
->dma
, eq_num
, 0, MLX4_CMD_SW2HW_EQ
,
303 MLX4_CMD_TIME_CLASS_A
);
306 static int mlx4_HW2SW_EQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
309 return mlx4_cmd_box(dev
, 0, mailbox
->dma
, eq_num
, 0, MLX4_CMD_HW2SW_EQ
,
310 MLX4_CMD_TIME_CLASS_A
);
313 static void __devinit __iomem
*mlx4_get_eq_uar(struct mlx4_dev
*dev
,
316 struct mlx4_priv
*priv
= mlx4_priv(dev
);
319 index
= eq
->eqn
/ 4 - dev
->caps
.reserved_eqs
/ 4;
321 if (!priv
->eq_table
.uar_map
[index
]) {
322 priv
->eq_table
.uar_map
[index
] =
323 ioremap(pci_resource_start(dev
->pdev
, 2) +
324 ((eq
->eqn
/ 4) << PAGE_SHIFT
),
326 if (!priv
->eq_table
.uar_map
[index
]) {
327 mlx4_err(dev
, "Couldn't map EQ doorbell for EQN 0x%06x\n",
333 return priv
->eq_table
.uar_map
[index
] + 0x800 + 8 * (eq
->eqn
% 4);
336 static int __devinit
mlx4_create_eq(struct mlx4_dev
*dev
, int nent
,
337 u8 intr
, struct mlx4_eq
*eq
)
339 struct mlx4_priv
*priv
= mlx4_priv(dev
);
340 struct mlx4_cmd_mailbox
*mailbox
;
341 struct mlx4_eq_context
*eq_context
;
343 u64
*dma_list
= NULL
;
350 eq
->nent
= roundup_pow_of_two(max(nent
, 2));
351 npages
= PAGE_ALIGN(eq
->nent
* MLX4_EQ_ENTRY_SIZE
) / PAGE_SIZE
;
353 eq
->page_list
= kmalloc(npages
* sizeof *eq
->page_list
,
358 for (i
= 0; i
< npages
; ++i
)
359 eq
->page_list
[i
].buf
= NULL
;
361 dma_list
= kmalloc(npages
* sizeof *dma_list
, GFP_KERNEL
);
365 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
368 eq_context
= mailbox
->buf
;
370 for (i
= 0; i
< npages
; ++i
) {
371 eq
->page_list
[i
].buf
= dma_alloc_coherent(&dev
->pdev
->dev
,
372 PAGE_SIZE
, &t
, GFP_KERNEL
);
373 if (!eq
->page_list
[i
].buf
)
374 goto err_out_free_pages
;
377 eq
->page_list
[i
].map
= t
;
379 memset(eq
->page_list
[i
].buf
, 0, PAGE_SIZE
);
382 eq
->eqn
= mlx4_bitmap_alloc(&priv
->eq_table
.bitmap
);
384 goto err_out_free_pages
;
386 eq
->doorbell
= mlx4_get_eq_uar(dev
, eq
);
389 goto err_out_free_eq
;
392 err
= mlx4_mtt_init(dev
, npages
, PAGE_SHIFT
, &eq
->mtt
);
394 goto err_out_free_eq
;
396 err
= mlx4_write_mtt(dev
, &eq
->mtt
, 0, npages
, dma_list
);
398 goto err_out_free_mtt
;
400 memset(eq_context
, 0, sizeof *eq_context
);
401 eq_context
->flags
= cpu_to_be32(MLX4_EQ_STATUS_OK
|
402 MLX4_EQ_STATE_ARMED
);
403 eq_context
->log_eq_size
= ilog2(eq
->nent
);
404 eq_context
->intr
= intr
;
405 eq_context
->log_page_size
= PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
;
407 mtt_addr
= mlx4_mtt_addr(dev
, &eq
->mtt
);
408 eq_context
->mtt_base_addr_h
= mtt_addr
>> 32;
409 eq_context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
411 err
= mlx4_SW2HW_EQ(dev
, mailbox
, eq
->eqn
);
413 mlx4_warn(dev
, "SW2HW_EQ failed (%d)\n", err
);
414 goto err_out_free_mtt
;
418 mlx4_free_cmd_mailbox(dev
, mailbox
);
425 mlx4_mtt_cleanup(dev
, &eq
->mtt
);
428 mlx4_bitmap_free(&priv
->eq_table
.bitmap
, eq
->eqn
);
431 for (i
= 0; i
< npages
; ++i
)
432 if (eq
->page_list
[i
].buf
)
433 dma_free_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
434 eq
->page_list
[i
].buf
,
435 eq
->page_list
[i
].map
);
437 mlx4_free_cmd_mailbox(dev
, mailbox
);
440 kfree(eq
->page_list
);
447 static void mlx4_free_eq(struct mlx4_dev
*dev
,
450 struct mlx4_priv
*priv
= mlx4_priv(dev
);
451 struct mlx4_cmd_mailbox
*mailbox
;
453 int npages
= PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE
* eq
->nent
) / PAGE_SIZE
;
456 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
460 err
= mlx4_HW2SW_EQ(dev
, mailbox
, eq
->eqn
);
462 mlx4_warn(dev
, "HW2SW_EQ failed (%d)\n", err
);
465 mlx4_dbg(dev
, "Dumping EQ context %02x:\n", eq
->eqn
);
466 for (i
= 0; i
< sizeof (struct mlx4_eq_context
) / 4; ++i
) {
468 printk("[%02x] ", i
* 4);
469 printk(" %08x", be32_to_cpup(mailbox
->buf
+ i
* 4));
470 if ((i
+ 1) % 4 == 0)
475 mlx4_mtt_cleanup(dev
, &eq
->mtt
);
476 for (i
= 0; i
< npages
; ++i
)
477 pci_free_consistent(dev
->pdev
, PAGE_SIZE
,
478 eq
->page_list
[i
].buf
,
479 eq
->page_list
[i
].map
);
481 kfree(eq
->page_list
);
482 mlx4_bitmap_free(&priv
->eq_table
.bitmap
, eq
->eqn
);
483 mlx4_free_cmd_mailbox(dev
, mailbox
);
486 static void mlx4_free_irqs(struct mlx4_dev
*dev
)
488 struct mlx4_eq_table
*eq_table
= &mlx4_priv(dev
)->eq_table
;
491 if (eq_table
->have_irq
)
492 free_irq(dev
->pdev
->irq
, dev
);
493 for (i
= 0; i
< MLX4_EQ_CATAS
; ++i
)
494 if (eq_table
->eq
[i
].have_irq
)
495 free_irq(eq_table
->eq
[i
].irq
, eq_table
->eq
+ i
);
496 if (eq_table
->eq
[MLX4_EQ_CATAS
].have_irq
)
497 free_irq(eq_table
->eq
[MLX4_EQ_CATAS
].irq
, dev
);
500 static int __devinit
mlx4_map_clr_int(struct mlx4_dev
*dev
)
502 struct mlx4_priv
*priv
= mlx4_priv(dev
);
504 priv
->clr_base
= ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clr_int_bar
) +
505 priv
->fw
.clr_int_base
, MLX4_CLR_INT_SIZE
);
506 if (!priv
->clr_base
) {
507 mlx4_err(dev
, "Couldn't map interrupt clear register, aborting.\n");
514 static void mlx4_unmap_clr_int(struct mlx4_dev
*dev
)
516 struct mlx4_priv
*priv
= mlx4_priv(dev
);
518 iounmap(priv
->clr_base
);
521 int __devinit
mlx4_map_eq_icm(struct mlx4_dev
*dev
, u64 icm_virt
)
523 struct mlx4_priv
*priv
= mlx4_priv(dev
);
527 * We assume that mapping one page is enough for the whole EQ
528 * context table. This is fine with all current HCAs, because
529 * we only use 32 EQs and each EQ uses 64 bytes of context
530 * memory, or 1 KB total.
532 priv
->eq_table
.icm_virt
= icm_virt
;
533 priv
->eq_table
.icm_page
= alloc_page(GFP_HIGHUSER
);
534 if (!priv
->eq_table
.icm_page
)
536 priv
->eq_table
.icm_dma
= pci_map_page(dev
->pdev
, priv
->eq_table
.icm_page
, 0,
537 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
538 if (pci_dma_mapping_error(priv
->eq_table
.icm_dma
)) {
539 __free_page(priv
->eq_table
.icm_page
);
543 ret
= mlx4_MAP_ICM_page(dev
, priv
->eq_table
.icm_dma
, icm_virt
);
545 pci_unmap_page(dev
->pdev
, priv
->eq_table
.icm_dma
, PAGE_SIZE
,
546 PCI_DMA_BIDIRECTIONAL
);
547 __free_page(priv
->eq_table
.icm_page
);
553 void mlx4_unmap_eq_icm(struct mlx4_dev
*dev
)
555 struct mlx4_priv
*priv
= mlx4_priv(dev
);
557 mlx4_UNMAP_ICM(dev
, priv
->eq_table
.icm_virt
, 1);
558 pci_unmap_page(dev
->pdev
, priv
->eq_table
.icm_dma
, PAGE_SIZE
,
559 PCI_DMA_BIDIRECTIONAL
);
560 __free_page(priv
->eq_table
.icm_page
);
563 int __devinit
mlx4_init_eq_table(struct mlx4_dev
*dev
)
565 struct mlx4_priv
*priv
= mlx4_priv(dev
);
569 err
= mlx4_bitmap_init(&priv
->eq_table
.bitmap
, dev
->caps
.num_eqs
,
570 dev
->caps
.num_eqs
- 1, dev
->caps
.reserved_eqs
);
574 for (i
= 0; i
< ARRAY_SIZE(priv
->eq_table
.uar_map
); ++i
)
575 priv
->eq_table
.uar_map
[i
] = NULL
;
577 err
= mlx4_map_clr_int(dev
);
581 priv
->eq_table
.clr_mask
=
582 swab32(1 << (priv
->eq_table
.inta_pin
& 31));
583 priv
->eq_table
.clr_int
= priv
->clr_base
+
584 (priv
->eq_table
.inta_pin
< 32 ? 4 : 0);
586 err
= mlx4_create_eq(dev
, dev
->caps
.num_cqs
+ MLX4_NUM_SPARE_EQE
,
587 (dev
->flags
& MLX4_FLAG_MSI_X
) ? MLX4_EQ_COMP
: 0,
588 &priv
->eq_table
.eq
[MLX4_EQ_COMP
]);
592 err
= mlx4_create_eq(dev
, MLX4_NUM_ASYNC_EQE
+ MLX4_NUM_SPARE_EQE
,
593 (dev
->flags
& MLX4_FLAG_MSI_X
) ? MLX4_EQ_ASYNC
: 0,
594 &priv
->eq_table
.eq
[MLX4_EQ_ASYNC
]);
598 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
599 static const char *eq_name
[] = {
600 [MLX4_EQ_COMP
] = DRV_NAME
" (comp)",
601 [MLX4_EQ_ASYNC
] = DRV_NAME
" (async)",
602 [MLX4_EQ_CATAS
] = DRV_NAME
" (catas)"
605 err
= mlx4_create_eq(dev
, 1, MLX4_EQ_CATAS
,
606 &priv
->eq_table
.eq
[MLX4_EQ_CATAS
]);
610 for (i
= 0; i
< MLX4_EQ_CATAS
; ++i
) {
611 err
= request_irq(priv
->eq_table
.eq
[i
].irq
,
612 mlx4_msi_x_interrupt
,
613 0, eq_name
[i
], priv
->eq_table
.eq
+ i
);
617 priv
->eq_table
.eq
[i
].have_irq
= 1;
620 err
= request_irq(priv
->eq_table
.eq
[MLX4_EQ_CATAS
].irq
,
621 mlx4_catas_interrupt
, 0,
622 eq_name
[MLX4_EQ_CATAS
], dev
);
626 priv
->eq_table
.eq
[MLX4_EQ_CATAS
].have_irq
= 1;
628 err
= request_irq(dev
->pdev
->irq
, mlx4_interrupt
,
629 IRQF_SHARED
, DRV_NAME
, dev
);
633 priv
->eq_table
.have_irq
= 1;
636 err
= mlx4_MAP_EQ(dev
, MLX4_ASYNC_EVENT_MASK
, 0,
637 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].eqn
);
639 mlx4_warn(dev
, "MAP_EQ for async EQ %d failed (%d)\n",
640 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].eqn
, err
);
642 for (i
= 0; i
< MLX4_EQ_CATAS
; ++i
)
643 eq_set_ci(&priv
->eq_table
.eq
[i
], 1);
645 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
646 err
= mlx4_MAP_EQ(dev
, MLX4_CATAS_EVENT_MASK
, 0,
647 priv
->eq_table
.eq
[MLX4_EQ_CATAS
].eqn
);
649 mlx4_warn(dev
, "MAP_EQ for catas EQ %d failed (%d)\n",
650 priv
->eq_table
.eq
[MLX4_EQ_CATAS
].eqn
, err
);
656 mlx4_free_eq(dev
, &priv
->eq_table
.eq
[MLX4_EQ_CATAS
]);
659 mlx4_free_eq(dev
, &priv
->eq_table
.eq
[MLX4_EQ_ASYNC
]);
662 mlx4_free_eq(dev
, &priv
->eq_table
.eq
[MLX4_EQ_COMP
]);
665 mlx4_unmap_clr_int(dev
);
669 mlx4_bitmap_cleanup(&priv
->eq_table
.bitmap
);
673 void mlx4_cleanup_eq_table(struct mlx4_dev
*dev
)
675 struct mlx4_priv
*priv
= mlx4_priv(dev
);
678 if (dev
->flags
& MLX4_FLAG_MSI_X
)
679 mlx4_MAP_EQ(dev
, MLX4_CATAS_EVENT_MASK
, 1,
680 priv
->eq_table
.eq
[MLX4_EQ_CATAS
].eqn
);
682 mlx4_MAP_EQ(dev
, MLX4_ASYNC_EVENT_MASK
, 1,
683 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].eqn
);
687 for (i
= 0; i
< MLX4_EQ_CATAS
; ++i
)
688 mlx4_free_eq(dev
, &priv
->eq_table
.eq
[i
]);
689 if (dev
->flags
& MLX4_FLAG_MSI_X
)
690 mlx4_free_eq(dev
, &priv
->eq_table
.eq
[MLX4_EQ_CATAS
]);
692 mlx4_unmap_clr_int(dev
);
694 for (i
= 0; i
< ARRAY_SIZE(priv
->eq_table
.uar_map
); ++i
)
695 if (priv
->eq_table
.uar_map
[i
])
696 iounmap(priv
->eq_table
.uar_map
[i
]);
698 mlx4_bitmap_cleanup(&priv
->eq_table
.bitmap
);