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RT-AC66 3.0.0.4.374.130 core
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / mtd / nand / cafe_nand.c
blob6f32a35eb1069142ade478b2860d2c0297568827
1 /*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * Copyright © 2006 Red Hat, Inc.
5 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
6 */
7
8 #define DEBUG
9
10 #include <linux/device.h>
11 #undef DEBUG
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/nand.h>
14 #include <linux/rslib.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <asm/io.h>
20
21 #define CAFE_NAND_CTRL1 0x00
22 #define CAFE_NAND_CTRL2 0x04
23 #define CAFE_NAND_CTRL3 0x08
24 #define CAFE_NAND_STATUS 0x0c
25 #define CAFE_NAND_IRQ 0x10
26 #define CAFE_NAND_IRQ_MASK 0x14
27 #define CAFE_NAND_DATA_LEN 0x18
28 #define CAFE_NAND_ADDR1 0x1c
29 #define CAFE_NAND_ADDR2 0x20
30 #define CAFE_NAND_TIMING1 0x24
31 #define CAFE_NAND_TIMING2 0x28
32 #define CAFE_NAND_TIMING3 0x2c
33 #define CAFE_NAND_NONMEM 0x30
34 #define CAFE_NAND_ECC_RESULT 0x3C
35 #define CAFE_NAND_DMA_CTRL 0x40
36 #define CAFE_NAND_DMA_ADDR0 0x44
37 #define CAFE_NAND_DMA_ADDR1 0x48
38 #define CAFE_NAND_ECC_SYN01 0x50
39 #define CAFE_NAND_ECC_SYN23 0x54
40 #define CAFE_NAND_ECC_SYN45 0x58
41 #define CAFE_NAND_ECC_SYN67 0x5c
42 #define CAFE_NAND_READ_DATA 0x1000
43 #define CAFE_NAND_WRITE_DATA 0x2000
44
45 #define CAFE_GLOBAL_CTRL 0x3004
46 #define CAFE_GLOBAL_IRQ 0x3008
47 #define CAFE_GLOBAL_IRQ_MASK 0x300c
48 #define CAFE_NAND_RESET 0x3034
49
50 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
51 #define CTRL1_CHIPSELECT (1<<19)
52
53 struct cafe_priv {
54 struct nand_chip nand;
55 struct pci_dev *pdev;
56 void __iomem *mmio;
57 struct rs_control *rs;
58 uint32_t ctl1;
59 uint32_t ctl2;
60 int datalen;
61 int nr_data;
62 int data_pos;
63 int page_addr;
64 dma_addr_t dmaaddr;
65 unsigned char *dmabuf;
66 };
67
68 static int usedma = 1;
69 module_param(usedma, int, 0644);
70
71 static int skipbbt = 0;
72 module_param(skipbbt, int, 0644);
73
74 static int debug = 0;
75 module_param(debug, int, 0644);
76
77 static int regdebug = 0;
78 module_param(regdebug, int, 0644);
79
80 static int checkecc = 1;
81 module_param(checkecc, int, 0644);
82
83 static int numtimings;
84 static int timing[3];
85 module_param_array(timing, int, &numtimings, 0644);
86
87 /* Hrm. Why isn't this already conditional on something in the struct device? */
88 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
89
90 /* Make it easier to switch to PIO if we need to */
91 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
92 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
93
94 static int cafe_device_ready(struct mtd_info *mtd)
95 {
96 struct cafe_priv *cafe = mtd->priv;
97 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
98 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
99
100 cafe_writel(cafe, irqs, NAND_IRQ);
101
102 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
103 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
104 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
105
106 return result;
107 }
108
109
110 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
111 {
112 struct cafe_priv *cafe = mtd->priv;
113
114 if (usedma)
115 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
116 else
117 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
118
119 cafe->datalen += len;
120
121 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
122 len, cafe->datalen);
123 }
124
125 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
126 {
127 struct cafe_priv *cafe = mtd->priv;
128
129 if (usedma)
130 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
131 else
132 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
133
134 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
135 len, cafe->datalen);
136 cafe->datalen += len;
137 }
138
139 static uint8_t cafe_read_byte(struct mtd_info *mtd)
140 {
141 struct cafe_priv *cafe = mtd->priv;
142 uint8_t d;
143
144 cafe_read_buf(mtd, &d, 1);
145 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
146
147 return d;
148 }
149
150 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
151 int column, int page_addr)
152 {
153 struct cafe_priv *cafe = mtd->priv;
154 int adrbytes = 0;
155 uint32_t ctl1;
156 uint32_t doneint = 0x80000000;
157
158 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
159 command, column, page_addr);
160
161 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
162 /* Second half of a command we already calculated */
163 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
164 ctl1 = cafe->ctl1;
165 cafe->ctl2 &= ~(1<<30);
166 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
167 cafe->ctl1, cafe->nr_data);
168 goto do_command;
169 }
170 /* Reset ECC engine */
171 cafe_writel(cafe, 0, NAND_CTRL2);
172
173 /* Emulate NAND_CMD_READOOB on large-page chips */
174 if (mtd->writesize > 512 &&
175 command == NAND_CMD_READOOB) {
176 column += mtd->writesize;
177 command = NAND_CMD_READ0;
178 }
179
180 /* FIXME: Do we need to send read command before sending data
181 for small-page chips, to position the buffer correctly? */
182
183 if (column != -1) {
184 cafe_writel(cafe, column, NAND_ADDR1);
185 adrbytes = 2;
186 if (page_addr != -1)
187 goto write_adr2;
188 } else if (page_addr != -1) {
189 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
190 page_addr >>= 16;
191 write_adr2:
192 cafe_writel(cafe, page_addr, NAND_ADDR2);
193 adrbytes += 2;
194 if (mtd->size > mtd->writesize << 16)
195 adrbytes++;
196 }
197
198 cafe->data_pos = cafe->datalen = 0;
199
200 /* Set command valid bit, mask in the chip select bit */
201 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
202
203 /* Set RD or WR bits as appropriate */
204 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
205 ctl1 |= (1<<26); /* rd */
206 /* Always 5 bytes, for now */
207 cafe->datalen = 4;
208 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
209 adrbytes = 1;
210 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
211 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
212 ctl1 |= 1<<26; /* rd */
213 /* For now, assume just read to end of page */
214 cafe->datalen = mtd->writesize + mtd->oobsize - column;
215 } else if (command == NAND_CMD_SEQIN)
216 ctl1 |= 1<<25; /* wr */
217
218 /* Set number of address bytes */
219 if (adrbytes)
220 ctl1 |= ((adrbytes-1)|8) << 27;
221
222 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
223 /* Ignore the first command of a pair; the hardware
224 deals with them both at once, later */
225 cafe->ctl1 = ctl1;
226 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
227 cafe->ctl1, cafe->datalen);
228 return;
229 }
230 /* RNDOUT and READ0 commands need a following byte */
231 if (command == NAND_CMD_RNDOUT)
232 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
233 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
234 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
235
236 do_command:
237 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
238 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
239
240 /* NB: The datasheet lies -- we really should be subtracting 1 here */
241 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
242 cafe_writel(cafe, 0x90000000, NAND_IRQ);
243 if (usedma && (ctl1 & (3<<25))) {
244 uint32_t dmactl = 0xc0000000 + cafe->datalen;
245 /* If WR or RD bits set, set up DMA */
246 if (ctl1 & (1<<26)) {
247 /* It's a read */
248 dmactl |= (1<<29);
249 /* ... so it's done when the DMA is done, not just
250 the command. */
251 doneint = 0x10000000;
252 }
253 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
254 }
255 cafe->datalen = 0;
256
257 if (unlikely(regdebug)) {
258 int i;
259 printk("About to write command %08x to register 0\n", ctl1);
260 for (i=4; i< 0x5c; i+=4)
261 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
262 }
263
264 cafe_writel(cafe, ctl1, NAND_CTRL1);
265 /* Apply this short delay always to ensure that we do wait tWB in
266 * any case on any machine. */
267 ndelay(100);
268
269 if (1) {
270 int c;
271 uint32_t irqs;
272
273 for (c = 500000; c != 0; c--) {
274 irqs = cafe_readl(cafe, NAND_IRQ);
275 if (irqs & doneint)
276 break;
277 udelay(1);
278 if (!(c % 100000))
279 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
280 cpu_relax();
281 }
282 cafe_writel(cafe, doneint, NAND_IRQ);
283 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
284 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
285 }
286
287 WARN_ON(cafe->ctl2 & (1<<30));
288
289 switch (command) {
290
291 case NAND_CMD_CACHEDPROG:
292 case NAND_CMD_PAGEPROG:
293 case NAND_CMD_ERASE1:
294 case NAND_CMD_ERASE2:
295 case NAND_CMD_SEQIN:
296 case NAND_CMD_RNDIN:
297 case NAND_CMD_STATUS:
298 case NAND_CMD_DEPLETE1:
299 case NAND_CMD_RNDOUT:
300 case NAND_CMD_STATUS_ERROR:
301 case NAND_CMD_STATUS_ERROR0:
302 case NAND_CMD_STATUS_ERROR1:
303 case NAND_CMD_STATUS_ERROR2:
304 case NAND_CMD_STATUS_ERROR3:
305 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
306 return;
307 }
308 nand_wait_ready(mtd);
309 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
310 }
311
312 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
313 {
314 struct cafe_priv *cafe = mtd->priv;
315
316 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
317
318 /* Mask the appropriate bit into the stored value of ctl1
319 which will be used by cafe_nand_cmdfunc() */
320 if (chipnr)
321 cafe->ctl1 |= CTRL1_CHIPSELECT;
322 else
323 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
324 }
325
326 static int cafe_nand_interrupt(int irq, void *id)
327 {
328 struct mtd_info *mtd = id;
329 struct cafe_priv *cafe = mtd->priv;
330 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
331 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
332 if (!irqs)
333 return IRQ_NONE;
334
335 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
336 return IRQ_HANDLED;
337 }
338
339 static void cafe_nand_bug(struct mtd_info *mtd)
340 {
341 BUG();
342 }
343
344 static int cafe_nand_write_oob(struct mtd_info *mtd,
345 struct nand_chip *chip, int page)
346 {
347 int status = 0;
348
349 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
350 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
351 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
352 status = chip->waitfunc(mtd, chip);
353
354 return status & NAND_STATUS_FAIL ? -EIO : 0;
355 }
356
357 /* Don't use -- use nand_read_oob_std for now */
358 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
359 int page, int sndcmd)
360 {
361 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
362 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
363 return 1;
364 }
365 /**
366 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
367 * @mtd: mtd info structure
368 * @chip: nand chip info structure
369 * @buf: buffer to store read data
370 *
371 * The hw generator calculates the error syndrome automatically. Therefor
372 * we need a special oob layout and handling.
373 */
374 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
375 uint8_t *buf)
376 {
377 struct cafe_priv *cafe = mtd->priv;
378
379 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
380 cafe_readl(cafe, NAND_ECC_RESULT),
381 cafe_readl(cafe, NAND_ECC_SYN01));
382
383 chip->read_buf(mtd, buf, mtd->writesize);
384 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
385
386 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
387 unsigned short syn[8], pat[4];
388 int pos[4];
389 u8 *oob = chip->oob_poi;
390 int i, n;
391
392 for (i=0; i<8; i+=2) {
393 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
394 syn[i] = cafe->rs->index_of[tmp & 0xfff];
395 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
396 }
397
398 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
399 pat);
400
401 for (i = 0; i < n; i++) {
402 int p = pos[i];
403
404 /* The 12-bit symbols are mapped to bytes here */
405
406 if (p > 1374) {
407 /* out of range */
408 n = -1374;
409 } else if (p == 0) {
410 /* high four bits do not correspond to data */
411 if (pat[i] > 0xff)
412 n = -2048;
413 else
414 buf[0] ^= pat[i];
415 } else if (p == 1365) {
416 buf[2047] ^= pat[i] >> 4;
417 oob[0] ^= pat[i] << 4;
418 } else if (p > 1365) {
419 if ((p & 1) == 1) {
420 oob[3*p/2 - 2048] ^= pat[i] >> 4;
421 oob[3*p/2 - 2047] ^= pat[i] << 4;
422 } else {
423 oob[3*p/2 - 2049] ^= pat[i] >> 8;
424 oob[3*p/2 - 2048] ^= pat[i];
425 }
426 } else if ((p & 1) == 1) {
427 buf[3*p/2] ^= pat[i] >> 4;
428 buf[3*p/2 + 1] ^= pat[i] << 4;
429 } else {
430 buf[3*p/2 - 1] ^= pat[i] >> 8;
431 buf[3*p/2] ^= pat[i];
432 }
433 }
434
435 if (n < 0) {
436 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
437 cafe_readl(cafe, NAND_ADDR2) * 2048);
438 for (i = 0; i < 0x5c; i += 4)
439 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
440 mtd->ecc_stats.failed++;
441 } else {
442 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
443 mtd->ecc_stats.corrected += n;
444 }
445 }
446
447 return 0;
448 }
449
450 static struct nand_ecclayout cafe_oobinfo_2048 = {
451 .eccbytes = 14,
452 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
453 .oobfree = {{14, 50}}
454 };
455
456 /* Ick. The BBT code really ought to be able to work this bit out
457 for itself from the above, at least for the 2KiB case */
458 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
459 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
460
461 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
462 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
463
464
465 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
466 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
467 | NAND_BBT_2BIT | NAND_BBT_VERSION,
468 .offs = 14,
469 .len = 4,
470 .veroffs = 18,
471 .maxblocks = 4,
472 .pattern = cafe_bbt_pattern_2048
473 };
474
475 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
476 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
477 | NAND_BBT_2BIT | NAND_BBT_VERSION,
478 .offs = 14,
479 .len = 4,
480 .veroffs = 18,
481 .maxblocks = 4,
482 .pattern = cafe_mirror_pattern_2048
483 };
484
485 static struct nand_ecclayout cafe_oobinfo_512 = {
486 .eccbytes = 14,
487 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
488 .oobfree = {{14, 2}}
489 };
490
491 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
492 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
493 | NAND_BBT_2BIT | NAND_BBT_VERSION,
494 .offs = 14,
495 .len = 1,
496 .veroffs = 15,
497 .maxblocks = 4,
498 .pattern = cafe_bbt_pattern_512
499 };
500
501 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
502 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
503 | NAND_BBT_2BIT | NAND_BBT_VERSION,
504 .offs = 14,
505 .len = 1,
506 .veroffs = 15,
507 .maxblocks = 4,
508 .pattern = cafe_mirror_pattern_512
509 };
510
511
512 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
513 struct nand_chip *chip, const uint8_t *buf)
514 {
515 struct cafe_priv *cafe = mtd->priv;
516
517 chip->write_buf(mtd, buf, mtd->writesize);
518 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
519
520 /* Set up ECC autogeneration */
521 cafe->ctl2 |= (1<<30);
522 }
523
524 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
525 const uint8_t *buf, int page, int cached, int raw)
526 {
527 int status;
528
529 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
530
531 if (unlikely(raw))
532 chip->ecc.write_page_raw(mtd, chip, buf);
533 else
534 chip->ecc.write_page(mtd, chip, buf);
535
536 /*
537 * Cached progamming disabled for now, Not sure if its worth the
538 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
539 */
540 cached = 0;
541
542 if (!cached || !(chip->options & NAND_CACHEPRG)) {
543
544 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
545 status = chip->waitfunc(mtd, chip);
546 /*
547 * See if operation failed and additional status checks are
548 * available
549 */
550 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
551 status = chip->errstat(mtd, chip, FL_WRITING, status,
552 page);
553
554 if (status & NAND_STATUS_FAIL)
555 return -EIO;
556 } else {
557 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
558 status = chip->waitfunc(mtd, chip);
559 }
560
561 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
562 /* Send command to read back the data */
563 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
564
565 if (chip->verify_buf(mtd, buf, mtd->writesize))
566 return -EIO;
567 #endif
568 return 0;
569 }
570
571 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
572 {
573 return 0;
574 }
575
576 /* F_2[X]/(X**6+X+1) */
577 static unsigned short __devinit gf64_mul(u8 a, u8 b)
578 {
579 u8 c;
580 unsigned int i;
581
582 c = 0;
583 for (i = 0; i < 6; i++) {
584 if (a & 1)
585 c ^= b;
586 a >>= 1;
587 b <<= 1;
588 if ((b & 0x40) != 0)
589 b ^= 0x43;
590 }
591
592 return c;
593 }
594
595 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
596 static u16 __devinit gf4096_mul(u16 a, u16 b)
597 {
598 u8 ah, al, bh, bl, ch, cl;
599
600 ah = a >> 6;
601 al = a & 0x3f;
602 bh = b >> 6;
603 bl = b & 0x3f;
604
605 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
606 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
607
608 return (ch << 6) ^ cl;
609 }
610
611 static int __devinit cafe_mul(int x)
612 {
613 if (x == 0)
614 return 1;
615 return gf4096_mul(x, 0xe01);
616 }
617
618 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
619 const struct pci_device_id *ent)
620 {
621 struct mtd_info *mtd;
622 struct cafe_priv *cafe;
623 uint32_t ctrl;
624 int err = 0;
625
626 err = pci_enable_device(pdev);
627 if (err)
628 return err;
629
630 pci_set_master(pdev);
631
632 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
633 if (!mtd) {
634 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
635 return -ENOMEM;
636 }
637 cafe = (void *)(&mtd[1]);
638
639 mtd->priv = cafe;
640 mtd->owner = THIS_MODULE;
641
642 cafe->pdev = pdev;
643 cafe->mmio = pci_iomap(pdev, 0, 0);
644 if (!cafe->mmio) {
645 dev_warn(&pdev->dev, "failed to iomap\n");
646 err = -ENOMEM;
647 goto out_free_mtd;
648 }
649 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
650 &cafe->dmaaddr, GFP_KERNEL);
651 if (!cafe->dmabuf) {
652 err = -ENOMEM;
653 goto out_ior;
654 }
655 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
656
657 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
658 if (!cafe->rs) {
659 err = -ENOMEM;
660 goto out_ior;
661 }
662
663 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
664 cafe->nand.dev_ready = cafe_device_ready;
665 cafe->nand.read_byte = cafe_read_byte;
666 cafe->nand.read_buf = cafe_read_buf;
667 cafe->nand.write_buf = cafe_write_buf;
668 cafe->nand.select_chip = cafe_select_chip;
669
670 cafe->nand.chip_delay = 0;
671
672 /* Enable the following for a flash based bad block table */
673 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
674
675 if (skipbbt) {
676 cafe->nand.options |= NAND_SKIP_BBTSCAN;
677 cafe->nand.block_bad = cafe_nand_block_bad;
678 }
679
680 if (numtimings && numtimings != 3) {
681 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
682 }
683
684 if (numtimings == 3) {
685 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
686 timing[0], timing[1], timing[2]);
687 } else {
688 timing[0] = cafe_readl(cafe, NAND_TIMING1);
689 timing[1] = cafe_readl(cafe, NAND_TIMING2);
690 timing[2] = cafe_readl(cafe, NAND_TIMING3);
691
692 if (timing[0] | timing[1] | timing[2]) {
693 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
694 timing[0], timing[1], timing[2]);
695 } else {
696 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
697 timing[0] = timing[1] = timing[2] = 0xffffffff;
698 }
699 }
700
701 /* Start off by resetting the NAND controller completely */
702 cafe_writel(cafe, 1, NAND_RESET);
703 cafe_writel(cafe, 0, NAND_RESET);
704
705 cafe_writel(cafe, timing[0], NAND_TIMING1);
706 cafe_writel(cafe, timing[1], NAND_TIMING2);
707 cafe_writel(cafe, timing[2], NAND_TIMING3);
708
709 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
710 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
711 "CAFE NAND", mtd);
712 if (err) {
713 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
714 goto out_free_dma;
715 }
716
717 /* Disable master reset, enable NAND clock */
718 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
719 ctrl &= 0xffffeff0;
720 ctrl |= 0x00007000;
721 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
722 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
723 cafe_writel(cafe, 0, NAND_DMA_CTRL);
724
725 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
726 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
727
728 /* Set up DMA address */
729 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
730 if (sizeof(cafe->dmaaddr) > 4)
731 /* Shift in two parts to shut the compiler up */
732 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
733 else
734 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
735
736 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
737 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
738
739 /* Enable NAND IRQ in global IRQ mask register */
740 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
741 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
742 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
743
744 /* Scan to find existence of the device */
745 if (nand_scan_ident(mtd, 2)) {
746 err = -ENXIO;
747 goto out_irq;
748 }
749
750 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
751 if (mtd->writesize == 2048)
752 cafe->ctl2 |= 1<<29; /* 2KiB page size */
753
754 /* Set up ECC according to the type of chip we found */
755 if (mtd->writesize == 2048) {
756 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
757 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
758 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
759 } else if (mtd->writesize == 512) {
760 cafe->nand.ecc.layout = &cafe_oobinfo_512;
761 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
762 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
763 } else {
764 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
765 mtd->writesize);
766 goto out_irq;
767 }
768 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
769 cafe->nand.ecc.size = mtd->writesize;
770 cafe->nand.ecc.bytes = 14;
771 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
772 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
773 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
774 cafe->nand.write_page = cafe_nand_write_page;
775 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
776 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
777 cafe->nand.ecc.read_page = cafe_nand_read_page;
778 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
779
780 err = nand_scan_tail(mtd);
781 if (err)
782 goto out_irq;
783
784 pci_set_drvdata(pdev, mtd);
785 add_mtd_device(mtd);
786 goto out;
787
788 out_irq:
789 /* Disable NAND IRQ in global IRQ mask register */
790 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
791 free_irq(pdev->irq, mtd);
792 out_free_dma:
793 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
794 out_ior:
795 pci_iounmap(pdev, cafe->mmio);
796 out_free_mtd:
797 kfree(mtd);
798 out:
799 return err;
800 }
801
802 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
803 {
804 struct mtd_info *mtd = pci_get_drvdata(pdev);
805 struct cafe_priv *cafe = mtd->priv;
806
807 del_mtd_device(mtd);
808 /* Disable NAND IRQ in global IRQ mask register */
809 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
810 free_irq(pdev->irq, mtd);
811 nand_release(mtd);
812 free_rs(cafe->rs);
813 pci_iounmap(pdev, cafe->mmio);
814 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
815 kfree(mtd);
816 }
817
818 static struct pci_device_id cafe_nand_tbl[] = {
819 { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 },
820 { 0, }
821 };
822
823 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
824
825 static struct pci_driver cafe_nand_pci_driver = {
826 .name = "CAFÉ NAND",
827 .id_table = cafe_nand_tbl,
828 .probe = cafe_nand_probe,
829 .remove = __devexit_p(cafe_nand_remove),
830 #ifdef CONFIG_PMx
831 .suspend = cafe_nand_suspend,
832 .resume = cafe_nand_resume,
833 #endif
834 };
835
836 static int cafe_nand_init(void)
837 {
838 return pci_register_driver(&cafe_nand_pci_driver);
839 }
840
841 static void cafe_nand_exit(void)
842 {
843 pci_unregister_driver(&cafe_nand_pci_driver);
844 }
845 module_init(cafe_nand_init);
846 module_exit(cafe_nand_exit);
847
848 MODULE_LICENSE("GPL");
849 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
850 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
Tomato firmware and modifications.